专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07989842B2 Method and apparatus for heterojunction barrier diode detector for ultrahigh sensitivity 有权
标题翻译：用于超高灵敏度的异质结阻挡二极管检测器的方法和装置
公开(公告)号：US07989842B2
公开(公告)日：2011-08-02
申请号：US12395528
申请日：2009-02-27
申请人： Hooman Kazemi , Chanh Nguyen , Berinder Brar
发明人： Hooman Kazemi , Chanh Nguyen , Berinder Brar
IPC分类号： H01L31/0352 , H01L29/205 , H01L21/329
CPC分类号： H01L31/065 , B82Y20/00 , H01L31/035236 , H01L31/108 , H01L31/1085 , Y02E10/50
摘要： The disclosure relates to a zero-bias heterojunction diode detector with varying impedance. The detector includes a substrate supporting a Schottky structure and an Ohmic contact layer. A metallic contact layer is formed over the Ohmic layer. The Schottky structure comprises a plurality of barrier layers and each of the plurality of barriers layers includes a first material and a second material. In one embodiment, the composition percentage of the second material in each of the barrier layers increases among the plurality of barrier layers from the substrate to the metal layer in order to provide a graded periodicity for the Schottky structure.
摘要翻译：本公开涉及具有变化阻抗的零偏置异质结二极管检测器。检测器包括支撑肖特基结构和欧姆接触层的衬底。在欧姆层上形成金属接触层。肖特基结构包括多个阻挡层，并且多个阻挡层中的每一个包括第一材料和第二材料。在一个实施方案中，为了提供肖特基结构的渐变周期性，从衬底到金属层的多个阻挡层中，每个势垒层中的第二材料的组成百分比增加。

2. 发明申请

US20100219449A1 METHOD AND APPARATUS FOR HETEROJUNCTION BARRIER DIODE DETECTOR FOR ULTRAHIGH SENSITIVITY 有权
标题翻译：用于超高灵敏度的异位阻挡二极管检测器的方法和装置
公开(公告)号：US20100219449A1
公开(公告)日：2010-09-02
申请号：US12395528
申请日：2009-02-27
申请人： Hooman Kazemi , Chanh Nguyen , Berinder Brar
发明人： Hooman Kazemi , Chanh Nguyen , Berinder Brar
IPC分类号： H01L31/0352 , H01L29/205 , H01L21/329
CPC分类号： H01L31/065 , B82Y20/00 , H01L31/035236 , H01L31/108 , H01L31/1085 , Y02E10/50
摘要： The disclosure relates to a zero-bias heterojunction diode detector with varying impedance. The detector includes a substrate supporting a Schottky structure and an Ohmic contact layer. A metallic contact layer is formed over the Ohmic layer. The Schottky structure comprises a plurality of barrier layers and each of the plurality of barriers layers includes a first material and a second material. In one embodiment, the composition percentage of the second material in each of the barrier layers increases among the plurality of barrier layers from the substrate to the metal layer in order to provide a graded periodicity for the Schottky structure.
摘要翻译：本公开涉及具有变化阻抗的零偏置异质结二极管检测器。检测器包括支撑肖特基结构和欧姆接触层的衬底。在欧姆层上形成金属接触层。肖特基结构包括多个阻挡层，并且多个阻挡层中的每一个包括第一材料和第二材料。在一个实施方案中，为了提供肖特基结构的渐变周期性，从衬底到金属层的多个阻挡层中，每个势垒层中的第二材料的组成百分比增加。

3. 发明申请

US20070145417A1 High voltage semiconductor device having a lateral channel and enhanced gate-to-drain separation 审中-公开
标题翻译：具有侧向通道和增强的栅 - 漏分离的高电压半导体器件
公开(公告)号：US20070145417A1
公开(公告)日：2007-06-28
申请号：US11711340
申请日：2007-02-27
申请人： Berinder Brar , Wonill Ha , Mariam Sadaka , Chanh Nguyen
发明人： Berinder Brar , Wonill Ha , Mariam Sadaka , Chanh Nguyen
IPC分类号： H01L29/76
CPC分类号： H01L29/66462 , H01L29/4175 , H01L29/41766 , H01L29/7785
摘要： A semiconductor device having a lateral channel with contacts on opposing surfaces thereof. The semiconductor device includes a conductive substrate having a source contact covering a substantial portion of a bottom surface thereof. The semiconductor device also includes an isolation layer above the conductive substrate, a lateral channel above the isolation layer and a drain contact above the lateral channel. The semiconductor device further includes a gate located in a gate recess interposed between the lateral channel and the drain contact and a drain formed by at least one source/drain contact layer interposed between the lateral channel and the drain contact. The drain is offset on one side of the gate by a gate-to-drain separation distance. The semiconductor device still further includes an interconnect that connects the lateral channel to the conductive substrate operable to provide a low resistance coupling between the source contact and the lateral channel.
摘要翻译：一种具有在其相对表面上具有触点的横向通道的半导体器件。半导体器件包括具有覆盖其底表面的大部分的源极接触的导电基底。半导体器件还包括在导电衬底之上的隔离层，隔离层上方的横向沟道和横向沟道上方的漏极接触。所述半导体器件还包括位于所述横向沟道和所述漏极接触之间的栅极凹槽中的栅极和由介于所述侧向沟道和所述漏极接触之间的至少一个源极/漏极接触层形成的漏极。漏极在栅极到漏极间隔距离的一侧偏移。半导体器件还包括将横向沟道连接到导电衬底的互连，其可操作以在源极接触和侧向通道之间提供低电阻耦合。

4. 发明申请

US20080054304A1 Semiconductor Device Including a Lateral Field-Effect Transistor and Schottky Diode 有权
公开(公告)号：US20080054304A1
公开(公告)日：2008-03-06
申请号：US11866259
申请日：2007-10-02
申请人： Mariam Sadaka , Berinder Brar , Wonill Ha , Chanh Nguyen
发明人： Mariam Sadaka , Berinder Brar , Wonill Ha , Chanh Nguyen
IPC分类号： H01L31/0328
CPC分类号： H01L29/7783 , H01L27/0605 , H01L27/0629 , H01L27/0727 , H01L29/66462 , H01L29/872
摘要： A semiconductor device including a lateral field-effect transistor and Schottky diode and method of forming the same. In one embodiment, the lateral field-effect transistor includes a buffer layer having a contact covering a substantial portion of a bottom surface thereof, a lateral channel above the buffer layer, another contact above the lateral channel, and an interconnect that connects the lateral channel to the buffer layer. The semiconductor device also includes a Schottky diode parallel-coupled to the lateral field-effect transistor including a cathode formed from another buffer layer interposed between the buffer layer and the lateral channel, a Schottky interconnect interposed between the another buffer layer and the another contact, and an anode formed on a surface of the Schottky interconnect operable to connect the anode to the another contact. The semiconductor device may also include an isolation layer interposed between the buffer layer and the lateral channel.

5. 发明申请

US20080048174A1 Semiconductor Device Including a Lateral Field-Effect Transistor and Schottky Diode 有权
标题翻译：包括横向场效应晶体管和肖特基二极管的半导体器件
公开(公告)号：US20080048174A1
公开(公告)日：2008-02-28
申请号：US11866270
申请日：2007-10-02
申请人： Mariam Sadaka , Berinder Brar , Wonill Ha , Chanh Nguyen
发明人： Mariam Sadaka , Berinder Brar , Wonill Ha , Chanh Nguyen
IPC分类号： H01L29/15
CPC分类号： H01L29/7783 , H01L27/0605 , H01L27/0629 , H01L27/0727 , H01L29/66462 , H01L29/872
摘要： A semiconductor device including a lateral field-effect transistor and Schottky diode and method of forming the same. In one embodiment, the lateral field-effect transistor includes a buffer layer having a contact covering a substantial portion of a bottom surface thereof, a lateral channel above the buffer layer, another contact above the lateral channel, and an interconnect that connects the lateral channel to the buffer layer. The semiconductor device also includes a Schottky diode parallel-coupled to the lateral field-effect transistor including a cathode formed from another buffer layer interposed between the buffer layer and the lateral channel, a Schottky interconnect interposed between the another buffer layer and the another contact, and an anode formed on a surface of the Schottky interconnect operable to connect the anode to the another contact. The semiconductor device may also include an isolation layer interposed between the buffer layer and the lateral channel.
摘要翻译：包括横向场效应晶体管和肖特基二极管的半导体器件及其形成方法。在一个实施例中，横向场效应晶体管包括缓冲层，该缓冲层具有覆盖其底表面的大部分的接触，缓冲层上方的横向通道，横向通道上方的另一接触件以及将侧向通道到缓冲层。半导体器件还包括并联耦合到横向场效应晶体管的肖特基二极管，该晶体管包括由介于缓冲层和横向沟道之间的另一个缓冲层形成的阴极，插入另一个缓冲层和另一个触点之间的肖特基互连，以及形成在所述肖特基互连件的表面上的阳极，其可操作以将所述阳极连接到所述另一个触点。半导体器件还可以包括插入在缓冲层和横向沟道之间的隔离层。

6. 发明申请

US20080048173A1 Semiconductor Device Including a Lateral Field-Effect Transistor and Schottky Diode 有权
公开(公告)号：US20080048173A1
公开(公告)日：2008-02-28
申请号：US11866249
申请日：2007-10-02
申请人： Mariam Sadaka , Berinder Brar , Wonill Ha , Chanh Nguyen
发明人： Mariam Sadaka , Berinder Brar , Wonill Ha , Chanh Nguyen
IPC分类号： H01L29/15
CPC分类号： H01L27/0605 , H01L27/0629 , H01L27/0727 , H01L29/20 , H01L29/66462 , H01L29/7783 , H01L29/872
摘要： A semiconductor device including a lateral field-effect transistor and Schottky diode and method of forming the same. In one embodiment, the lateral field-effect transistor includes a buffer layer having a contact covering a substantial portion of a bottom surface thereof, a lateral channel above the buffer layer, another contact above the lateral channel, and an interconnect that connects the lateral channel to the buffer layer. The semiconductor device also includes a Schottky diode parallel-coupled to the lateral field-effect transistor including a cathode formed from another buffer layer interposed between the buffer layer and the lateral channel, a Schottky interconnect interposed between the another buffer layer and the another contact, and an anode formed on a surface of the Schottky interconnect operable to connect the anode to the another contact. The semiconductor device may also include an isolation layer interposed between the buffer layer and the lateral channel.

7. 发明申请

US20070187717A1 Semiconductor device having reduced on-resistance and method of forming the same 有权
标题翻译：具有降低的导通电阻的半导体器件及其形成方法
公开(公告)号：US20070187717A1
公开(公告)日：2007-08-16
申请号：US11732301
申请日：2007-04-03
申请人： Mariam Sadaka , Berinder Brar , Wonill Ha , Chanh Nguyen
发明人： Mariam Sadaka , Berinder Brar , Wonill Ha , Chanh Nguyen
IPC分类号： H01L31/00 , H01L21/336
CPC分类号： H01L29/1029 , H01L21/6835 , H01L29/1083 , H01L29/4175 , H01L29/41766 , H01L29/66462 , H01L29/7783 , H01L29/7785 , H01L2221/68318 , H01L2221/68327 , H01L2221/6834 , H01L2221/68381
摘要： A semiconductor device and method of forming the same. The semiconductor device includes an epitaxially grown and conductive buffer layer having a contact covering a substantial portion of a bottom surface thereof and a lateral channel above the buffer layer. The semiconductor device also includes another contact above the lateral channel and an interconnect that connects the lateral channel to the buffer layer, operable to provide a low resistance coupling between the contact and the lateral channel.
摘要翻译：一种半导体器件及其制造方法。半导体器件包括外延生长和导电缓冲层，其具有覆盖其底表面的大部分的接触和缓冲层上方的横向通道。半导体器件还包括在横向通道上方的另一接触件和将横向通道连接到缓冲层的互连件，可操作以在触头和横向通道之间提供低电阻耦合。

8. 发明授权

US07808016B2 Heterogeneous integration of low noise amplifiers with power amplifiers or switches 有权
标题翻译：低噪声放大器与功率放大器或开关的非均匀集成
公开(公告)号：US07808016B2
公开(公告)日：2010-10-05
申请号：US11521011
申请日：2006-09-14
申请人： Berinder Brar , Joshua I. Bergman , Amal Ikhlassi , Gabor Nagy , Gerard J. Sullivan
发明人： Berinder Brar , Joshua I. Bergman , Amal Ikhlassi , Gabor Nagy , Gerard J. Sullivan
IPC分类号： H01L31/109
CPC分类号： H01L27/0605
摘要： A transistor heterogeneously integrating a power amplifier or switch with a low-noise amplifier having a substrate wafer selected from a group consisting of Gallium Arsenide (GaAs), Indium Phosphate (InP) and Gallium Antimonide (GaSb), the substrate wafer having a first end and a second end, a conducting layer above the first end of the substrate wafer, an isolation implant providing lateral isolation in the conducting layer, a first active layer deposited above the conducting layer and configured for the low-noise amplifier, and a buffer layer deposited above the conducting layer and configured for the low-noise amplifier.
摘要翻译：一种将功率放大器或开关与具有选自由砷化镓（GaAs），磷酸铟（InP）和镓锑镓镓（GaSb））组成的组的衬底晶片的低噪声放大器非均匀地集成的晶体管，所述衬底晶片具有第一端以及第二端，在所述衬底晶片的所述第一端上方的导电层，在所述导电层中提供横向隔离的隔离植入物，沉积在所述导电层上方并被配置用于所述低噪声放大器的第一有源层，以及缓冲层沉积在导电层上方并配置用于低噪声放大器。

9. 发明授权

US06414340B1 Field effect transistor and method for making the same 有权
公开(公告)号：US06414340B1
公开(公告)日：2002-07-02
申请号：US09434773
申请日：1999-11-04
申请人： Berinder Brar
发明人： Berinder Brar
IPC分类号： H01L31072
CPC分类号： H01L29/66462 , H01L29/1075 , H01L29/42316 , H01L29/7783
摘要： The field effect device consisting of a substrate, a conducting backplane formed in the substrate, a source and a drain disposed above the conductive backplane, a gate insultatively disposed above the substrate between the source and drain, and a backgate contact electrically coupled to the conducting backplane.

10. 发明授权

US07518165B2 Epitaxial nucleation and buffer sequence for via-compatible InAs/AlGaSb HEMTs 有权
标题翻译：用于通孔兼容InAs / AlGaSb HEMT的外延成核和缓冲序列
公开(公告)号：US07518165B2
公开(公告)日：2009-04-14
申请号：US11521012
申请日：2006-09-14
申请人： Joshua I. Bergman , Berinder Brar , Amal Ikhlassi , Gabor Nagy , Gerard J. Sullivan
发明人： Joshua I. Bergman , Berinder Brar , Amal Ikhlassi , Gabor Nagy , Gerard J. Sullivan
IPC分类号： H01L29/06
CPC分类号： H01L29/7783 , H01L21/02392 , H01L21/02395 , H01L21/02398 , H01L21/02463 , H01L21/02466 , H01L21/02549 , H01L29/201 , H01L29/66462
摘要： A metamorphic high electron mobility transistor having a plurality of high electron mobility transistor layers, a semi-insulating substrate, a ternary metamorphic buffer layer positioned between the semi-insulating substrate and the plurality of high electron mobility transistor layers, the ternary metamorphic buffer layer being Al1-xGaxSb such that x is greater than or equal to 0.2 but less than 0.3, a stabilizing layer positioned between the ternary metamorphic buffer layer and the plurality of high electron mobility transistor layers, the stabilizing layer being Al1-yGaySb such that y is greater than 0.2 but less than or equal to 0.3 and y is greater than x, and a nucleation layer interposed between the semi-insulating substrate and the ternary metamorphic buffer layer.
摘要翻译：具有多个高电子迁移率晶体管层的变质高电子迁移率晶体管，半绝缘衬底，位于半绝缘衬底和多个高电子迁移率晶体管层之间的三元变质缓冲层，三元变质缓冲层为 Al1-xGaxSb，使得x大于或等于0.2但小于0.3，位于三元变质缓冲层和多个高电子迁移率晶体管层之间的稳定层，稳定层为Al1-yGaySb，使得y更大小于或等于0.3且y大于x，并且成核层插入在半绝缘衬底和三元变质缓冲层之间。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式