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1. 发明授权

US5569936A Semiconductor device employing crystallization catalyst 失效
标题翻译：采用结晶催化剂的半导体装置
公开(公告)号：US5569936A
公开(公告)日：1996-10-29
申请号：US207124
申请日：1994-03-08
申请人： Hongyong Zhang , Hideki Uochi , Toru Takayama , Yasuhiko Takemura , Mutsuo Yamamoto
发明人： Hongyong Zhang , Hideki Uochi , Toru Takayama , Yasuhiko Takemura , Mutsuo Yamamoto
IPC分类号： G02F1/1362 , H01L21/20 , H01L21/336 , H01L21/8238 , H01L27/092 , H01L27/12 , H01L29/786 , H01L29/76 , H01L29/04 , H01L31/036 , H01L27/01
CPC分类号： H01L27/1251 , H01L21/2022 , H01L21/8238 , H01L27/0922 , H01L27/1237 , H01L27/1277 , H01L29/66757 , H01L29/78618 , H01L29/78675 , G02F1/13454 , Y10S148/016
摘要： A substance containing a catalyst element is formed so as to closely contact with an amorphous silicon film, or a catalyst element is introduced into the amorphous silicon film. The amorphous silicon film is annealed at a temperature which is lower than a crystallization temperature of usual amorphous silicon, thereby selectively crystallizing the amorphous silicon film. The crystallized region is used as a crystalline silicon TFT which can be used in a peripheral driver circuit of an active matrix circuit. The region which remains amorphous is used as an amorphous silicon TFT which can be used in a pixel circuit. A relatively small amount of a catalyst element for promoting crystallization is added to an amorphous silicon film, and an annealing process is conducted at a temperature which is lower than the distortion temperature of a substrate, thereby crystallizing the amorphous silicon film. A gate insulating film, and a gate electrode are then formed, and an impurity is implanted in a self-alignment manner. A film containing a catalyst element for promoting crystallization is closely contacted with the impurity region, or a relatively large amount of a catalyst element is introduced into the impurity region by an ion implantation or the like. Then, an annealing process is conducted at a temperature which is lower than the distortion temperature of the substrate, thereby activating the doping impurity.
摘要翻译：形成含有催化剂元素的物质，以与非晶硅膜紧密接触，或将催化剂元素引入到非晶硅膜中。非晶硅膜在比通常的非晶硅的结晶温度低的温度下退火，从而选择性地使非晶硅膜结晶。结晶区域用作可用于有源矩阵电路的外围驱动电路的晶体硅TFT。保持非晶形的区域用作可用于像素电路中的非晶硅TFT。在非晶硅膜中添加相对少量的促进结晶的催化剂元素，并且在比基板的变形温度低的温度下进行退火处理，从而使非晶硅膜结晶。然后形成栅极绝缘膜和栅电极，并以自对准的方式注入杂质。含有促进结晶的催化剂元素的膜与杂质区紧密接触，或者通过离子注入等将相对大量的催化剂元素引入杂质区。然后，在比基板的变形温度低的温度下进行退火处理，从而激活掺杂杂质。

2. 发明授权

US5595923A Method of forming a thin film transistor 失效
标题翻译：形成薄膜晶体管的方法
公开(公告)号：US5595923A
公开(公告)日：1997-01-21
申请号：US467986
申请日：1995-06-06
申请人： Hongyong Zhang , Hideki Uochi , Toru Takayama , Yasuhiko Takemura , Mutsuo Yamamoto
发明人： Hongyong Zhang , Hideki Uochi , Toru Takayama , Yasuhiko Takemura , Mutsuo Yamamoto
IPC分类号： G02F1/1362 , H01L21/20 , H01L21/336 , H01L21/8238 , H01L27/092 , H01L27/12 , H01L29/786 , H01L21/84
CPC分类号： H01L27/1251 , H01L21/2022 , H01L21/8238 , H01L27/0922 , H01L27/1237 , H01L27/1277 , H01L29/66757 , H01L29/78618 , H01L29/78675 , G02F1/13454 , Y10S148/016
摘要： A substance containing a catalyst element is formed so as to closely contact with an amorphous silicon film, or a catalyst element is introduced into the amorphous silicon film. The amorphous silicon film is annealed at a temperature which is lower than a crystallization temperature of usual amorphous silicon, thereby selectively crystallizing the amorphous silicon film. The crystallized region is used as a crystalline silicon TFT which can be used in a peripheral driver circuit of an active matrix circuit. The region which remains amorphous is used as an amorphous silicon TFT which can be used in a pixel circuit. A relatively small amount of a catalyst element for promoting crystallization is added to an amorphous silicon film, and an annealing process is conducted at a temperature which is lower than the distortion temperature of a substrate, thereby crystallizing the amorphous silicon film. A gate insulating film, and a gate electrode are then formed, and an impurity is implanted in a self-alignment manner. A film containing a catalyst element for promoting crystallization is closely contacted with the impurity region, or a relatively large amount of a catalyst element is introduced into the impurity region by an ion implantation or the like. Then, an annealing process is conducted at a temperature which is lower than the distortion temperature of the substrate, thereby activating the doping impurity.
摘要翻译：形成含有催化剂元素的物质，以与非晶硅膜紧密接触，或将催化剂元素引入到非晶硅膜中。非晶硅膜在比通常的非晶硅的结晶温度低的温度下退火，从而选择性地使非晶硅膜结晶。结晶区域用作可用于有源矩阵电路的外围驱动电路的晶体硅TFT。保持非晶形的区域用作可用于像素电路中的非晶硅TFT。在非晶硅膜中添加相对少量的促进结晶的催化剂元素，并且在比基板的变形温度低的温度下进行退火处理，从而使非晶硅膜结晶。然后形成栅极绝缘膜和栅电极，并以自对准的方式注入杂质。含有促进结晶的催化剂元素的膜与杂质区紧密接触，或者通过离子注入等将相对大量的催化剂元素引入杂质区。然后，在比基板的变形温度低的温度下进行退火处理，从而激活掺杂杂质。

3. 发明授权

US5608251A Thin film semiconductor integrated circuit and method of fabricating the same 失效
标题翻译：薄膜半导体集成电路及其制造方法
公开(公告)号：US5608251A
公开(公告)日：1997-03-04
申请号：US626578
申请日：1996-04-02
申请人： Toshimitsu Konuma , Masaaki Hiroki , Hongyong Zhang , Mutsuo Yamamoto , Yasuhiko Takemura
发明人： Toshimitsu Konuma , Masaaki Hiroki , Hongyong Zhang , Mutsuo Yamamoto , Yasuhiko Takemura
IPC分类号： G02F1/136 , G02F1/1368 , H01L21/20 , H01L21/28 , H01L21/336 , H01L21/77 , H01L21/84 , H01L27/12 , H01L29/78 , H01L29/786 , H01L29/76 , H01L27/01 , H01L27/13
CPC分类号： H01L21/2026 , H01L21/28079 , H01L27/12 , H01L27/1285 , H01L29/66757 , H01L29/78621 , Y10S438/981
摘要： In a semiconductor integrated circuit, a plurality of thin film transistors (TFTs) are formed on the same substrate having an insulating surface. Since gate electrodes formed in the TFTs are electrically insulated each other, voltages are applied independently to gate electrodes in an electrolytic solution during an anodization, to form an anodic oxide in at least both sides of each gate electrode. A thickness of the anodic oxide is changed in accordance with characteristics of the TFT. A width of high resistance regions formed in an active layer of each TFT is changed by ion doping using the anodic oxide having a desired thickness as a mask.
摘要翻译：在半导体集成电路中，在具有绝缘面的同一基板上形成多个薄膜晶体管（TFT）。由于形成在TFT中的栅电极彼此电绝缘，所以在阳极氧化期间，在电解液中的栅电极独立地施加电压，以在每个栅电极的至少两侧形成阳极氧化物。阳极氧化物的厚度根据TFT的特性而改变。通过使用具有所需厚度的阳极氧化物作为掩模的离子掺杂来改变形成在每个TFT的有源层中的高电阻区域的宽度。

4. 发明授权

US5620905A Method of fabricating thin film semiconductor integrated circuit 失效
标题翻译：制造薄膜半导体集成电路的方法
公开(公告)号：US5620905A
公开(公告)日：1997-04-15
申请号：US413104
申请日：1995-03-29
申请人： Toshimitsu Konuma , Masaaki Hiroki , Hongyong Zhang , Mutsuo Yamamoto , Yasuhiko Takemura
发明人： Toshimitsu Konuma , Masaaki Hiroki , Hongyong Zhang , Mutsuo Yamamoto , Yasuhiko Takemura
IPC分类号： G02F1/136 , G02F1/1368 , H01L21/20 , H01L21/28 , H01L21/336 , H01L21/77 , H01L21/84 , H01L27/12 , H01L29/78 , H01L29/786
CPC分类号： H01L21/2026 , H01L21/28079 , H01L27/12 , H01L27/1285 , H01L29/66757 , H01L29/78621 , Y10S438/981
摘要： In a semiconductor integrated circuit, a plurality of thin film transistors (TFTs) are formed on the same substrate having an insulating surface. Since gate electrodes formed in the TFTs are electrically insulated each other, voltages are applied independently to gate electrodes in an electrolytic solution during an anodization, to form an anodic oxide in at least both sides of each gate electrode. A thickness of the anodic oxide is changed in accordance with characteristics of the TFT. A width of high resistance regions formed in an active layer of each TFT is changed by ion doping using the anodic oxide having a desired thickness as a mask.
摘要翻译：在半导体集成电路中，在具有绝缘面的同一基板上形成多个薄膜晶体管（TFT）。由于形成在TFT中的栅电极彼此电绝缘，所以在阳极氧化期间，在电解液中的栅电极独立地施加电压，以在每个栅电极的至少两侧形成阳极氧化物。阳极氧化物的厚度根据TFT的特性而改变。通过使用具有所需厚度的阳极氧化物作为掩模的离子掺杂来改变形成在每个TFT的有源层中的高电阻区域的宽度。

5. 发明授权

US06743667B2 Method of manufacturing an active matrix type device 失效
标题翻译：制造有源矩阵型器件的方法
公开(公告)号：US06743667B2
公开(公告)日：2004-06-01
申请号：US09773620
申请日：2001-02-02
申请人： Masamitsu Hiroki , Yasuhiko Takemura , Mutsuo Yamamoto , Naoaki Yamaguchi , Satoshi Teramoto
发明人： Masamitsu Hiroki , Yasuhiko Takemura , Mutsuo Yamamoto , Naoaki Yamaguchi , Satoshi Teramoto
IPC分类号： H01L2184
CPC分类号： H01L29/66757 , H01L27/1277 , H01L29/78621
摘要： An amorphous semiconductor film comprising silicon is provided with a metal element which is capable of promoting a crystallization of silicon. Then, the semiconductor film is crystallized by hating at a relatively low temperature. After introducing impurity ions into source and drain regions of the semiconductor film, the source and drain regions are recrystallized by heating. During the recrystallization, the channel region having crystallinity functions as crystalline nuclei. Accordingly, it is possible to avoid defects occurring in the boundary regions between the channel region and source/drain regions.
摘要翻译：包含硅的非晶半导体膜具有能够促进硅结晶的金属元素。然后，半导体膜在相对较低的温度下憎恨而结晶。在将杂质离子引入半导体膜的源极和漏极区域之后，通过加热使源极和漏极区域再结晶。在重结晶期间，具有结晶性的沟道区域作为结晶核发挥作用。因此，可以避免在沟道区域和源极/漏极区域之间的边界区域中发生的缺陷。

6. 发明授权

US06194255B1 Method for manufacturing thin-film transistors 失效
标题翻译：制造薄膜晶体管的方法
公开(公告)号：US06194255B1
公开(公告)日：2001-02-27
申请号：US08839941
申请日：1997-04-18
申请人： Masamitsu Hiroki , Yasuhiko Takemura , Mutsuo Yamamoto , Naoaki Yamaguchi , Satoshi Teramoto
发明人： Masamitsu Hiroki , Yasuhiko Takemura , Mutsuo Yamamoto , Naoaki Yamaguchi , Satoshi Teramoto
IPC分类号： H01L2184
CPC分类号： H01L29/66757 , H01L27/1277 , H01L29/78621
摘要： A method of manufacturing a semiconductor device includes process of introducing a material for promoting crystallization of an amorphous semiconductor film, crystallizing the amorphous semiconductor film to form a crystalline semiconductor film, introducing phosphorus to form a source region, a drain region, a pair of light doped regions and a channel region being defined between the pair of the light doped region, heating the crystalline semiconductor film so that the material is diffused from the channel region to each of the source and drain regions through each of the pair of light doped region.
摘要翻译：一种制造半导体器件的方法包括引入用于促进非晶半导体膜的结晶的材料的工艺，使非晶半导体膜结晶以形成晶体半导体膜，引入磷以形成源极区，漏极区，一对光掺杂区域和沟道区域之间限定在所述一对掺杂光区域之间，加热所述晶体半导体膜，使得所述材料通过所述一对光掺杂区域中的每一个从所述沟道区域扩散到所述源极和漏极区域中的每一个。

7. 发明授权

US07105898B2 Electronic circuit 失效
公开(公告)号：US07105898B2
公开(公告)日：2006-09-12
申请号：US11022882
申请日：2004-12-28
申请人： Minoru Miyazaki , Akane Murakami , Baochun Cui , Mutsuo Yamamoto
发明人： Minoru Miyazaki , Akane Murakami , Baochun Cui , Mutsuo Yamamoto
IPC分类号： H01L27/01 , H01L27/12 , H01L31/0392
CPC分类号： H01L23/53223 , G02F1/1368 , H01L27/12 , H01L27/124 , H01L29/458 , H01L2224/45124 , H01L2924/00014 , H01L2924/10253 , H01L2924/13091 , H01L2924/00 , H01L2224/48
摘要： An electronic circuit formed on an insulating substrate and having thin-film transistors (TFTs) comprising semiconductor layers. The thickness of the semiconductor layer is less than 1500 Å, e.g., between 100 and 750 Å. A first layer consisting mainly of titanium and nitrogen is formed on the semiconductor layer. A second layer consisting of aluminum is formed on top of the first layer. The first and second layers are patterned into conductive interconnects. The bottom surface of the second layer is substantially totally in intimate contact with the first layer. The interconnects have good contacts with the semiconductor layer.

8. 发明授权

US5811326A Method for manufacturing thin film transistor 失效
标题翻译：制造薄膜晶体管的方法
公开(公告)号：US5811326A
公开(公告)日：1998-09-22
申请号：US372911
申请日：1995-01-17
申请人： Mutsuo Yamamoto
发明人： Mutsuo Yamamoto
IPC分类号： H01L21/316 , H01L21/336 , H01L21/77 , H01L21/84 , H01L29/49 , H01L29/786
CPC分类号： H01L29/66757 , H01L21/31687 , H01L27/1214 , H01L29/4908 , H01L29/78621
摘要： In a thin film transistor (TFT), a part of a surface or a whole surface of aluminum used as a gate electrode is covered by anodic oxide. In a process after anodization process, ultraviolet light is irradiated to a gate electrode in an oxidizing atmosphere containing oxygen, ozone, or nitrous oxide. Or, in a process after anodization process, a TFT is leaved (placed) in plasma in an oxidizing atmosphere. Or, ultraviolet light is irradiated to a gate electrode in plasma in an oxidizing atmosphere. A substrate temperature is a room temperature (50.degree. C.) to 500.degree. C., for example, 200.degree. to 300.degree. C. By ultraviolet light irradiation or plasma processing, metallic aluminum contained in anodic oxide is oxidized.
摘要翻译：在薄膜晶体管（TFT）中，用作栅电极的铝的一部分表面或整个表面被阳极氧化物覆盖。在阳极氧化处理之后的过程中，紫外线在含有氧，臭氧或一氧化二氮的氧化气氛中照射到栅电极。或者，在阳极氧化处理之后的过程中，在氧化气氛中将TFT留在等离子体中。或者，在氧化气氛中将紫外线照射到等离子体中的栅电极。基板温度为室温（50℃）至500℃，例如200℃至300℃。通过紫外光照射或等离子体处理，阳极氧化物中所含的金属铝被氧化。

9. 发明授权

US07897972B2 Electronic circuit 失效
标题翻译：电子电路
公开(公告)号：US07897972B2
公开(公告)日：2011-03-01
申请号：US12476445
申请日：2009-06-02
申请人： Minoru Miyazaki , Akane Murakami , Baochun Cui , Mutsuo Yamamoto
发明人： Minoru Miyazaki , Akane Murakami , Baochun Cui , Mutsuo Yamamoto
IPC分类号： H01L29/04 , H01L29/10
CPC分类号： H01L23/53223 , G02F1/1368 , H01L27/12 , H01L27/124 , H01L29/458 , H01L2224/45124 , H01L2924/00014 , H01L2924/10253 , H01L2924/13091 , H01L2924/00 , H01L2224/48
摘要： An electronic circuit formed on an insulating substrate and having thin-film transistors (TFTs) comprising semiconductor layers. The thickness of the semiconductor layer is less than 1500 Å, e.g., between 100 and 750 Å. A first layer consisting mainly of titanium and nitrogen is formed on the semiconductor layer. A second layer consisting of aluminum is formed on top of the first layer. The first and second layers are patterned into conductive interconnects. The bottom surface of the second layer is substantially totally in intimate contact with the first layer. The interconnects have good contacts with the semiconductor layer.
摘要翻译：一种形成在绝缘衬底上并具有包括半导体层的薄膜晶体管（TFT）的电子电路。半导体层的厚度小于1500，例如在100和750之间。主要由钛和氮组成的第一层形成在半导体层上。由铝构成的第二层形成在第一层的顶部。第一层和第二层被图案化成导电互连。第二层的底表面基本上完全与第一层完全接触。互连件与半导体层具有良好的接触。

10. 发明授权

US07045399B2 Electronic circuit 有权
公开(公告)号：US07045399B2
公开(公告)日：2006-05-16
申请号：US10620420
申请日：2003-07-17
申请人： Minoru Miyazaki , Akane Murakami , Baochun Cui , Mutsuo Yamamoto
发明人： Minoru Miyazaki , Akane Murakami , Baochun Cui , Mutsuo Yamamoto
IPC分类号： H01L21/00 , H01L21/8242 , H01L29/80 , H01L33/00
CPC分类号： H01L23/53223 , G02F1/1368 , H01L27/12 , H01L27/124 , H01L29/458 , H01L2224/45124 , H01L2924/00014 , H01L2924/10253 , H01L2924/13091 , H01L2924/00 , H01L2224/48
摘要： An electronic circuit formed on an insulating substrate and having thin-film transistors (TFTs) comprising semiconductor layers. The thickness of the semiconductor layers is less than 1500 Å, e.g., between 100 and 750 Å. A first layer consisting mainly of titanium and nitrogen is formed on the semiconductor layer. A second layer consisting aluminum is formed on top of the first layer. The first and second layers are patterned into conductive interconnects. The bottom surface of the second layer is substantially totally in intimate contact with the first layer. The interconnects have good contacts with the semiconductor layer.

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