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1. 发明授权

US07071094B2 Dual layer barrier film techniques to prevent resist poisoning 有权
标题翻译：双层阻挡膜技术，以防止中毒
公开(公告)号：US07071094B2
公开(公告)日：2006-07-04
申请号：US10893659
申请日：2004-07-16
申请人： Hong-Qiang Lu , Wei-Jen Hsia , Wilbur G. Catabay
发明人： Hong-Qiang Lu , Wei-Jen Hsia , Wilbur G. Catabay
IPC分类号： H01L21/4763
CPC分类号： H01L21/76829 , H01L21/31144 , H01L21/3148 , H01L21/76807 , H01L21/76808 , H01L21/7681 , H01L21/76832
摘要： Provided is a process for forming a barrier film to prevent resist poisoning in a semiconductor device by depositing a second nitrogen-free barrier layer on top of a first barrier layer containing nitrogen. A low-k dielectric layer is formed over the second barrier layer. This technique maintains the low electrical leakage characteristics of the first barrier layer and reduces nitrogen poisoning of a photoresist layer subsequently applied.
摘要翻译：本发明提供一种通过在含有氮的第一阻挡层的顶部沉积第二无氮阻挡层来形成阻挡膜以防止半导体器件中的中毒的方法。在第二阻挡层上形成低k电介质层。该技术保持了第一阻挡层的低漏电特性，并且减少随后施加的光致抗蚀剂层的氮中毒。

2. 发明授权

US06812134B1 Dual layer barrier film techniques to prevent resist poisoning 有权
标题翻译：双层阻挡膜技术，以防止中毒
公开(公告)号：US06812134B1
公开(公告)日：2004-11-02
申请号：US09896363
申请日：2001-06-28
申请人： Hong-Qiang Lu , Wei-Jen Hsia , Wilbur G. Catabay
发明人： Hong-Qiang Lu , Wei-Jen Hsia , Wilbur G. Catabay
IPC分类号： H01K214763
CPC分类号： H01L21/76829 , H01L21/31144 , H01L21/3148 , H01L21/76807 , H01L21/76808 , H01L21/7681 , H01L21/76832
摘要： Provided is a process for forming a barrier film to prevent resist poisoning in a semiconductor device by depositing a second nitrogen-free barrier layer on top of a first barrier layer containing nitrogen. A low-k dielectric layer is formed over the second barrier layer. This technique maintains the low electrical leakage characteristics of the first barrier layer and reduces nitrogen poisoning of a photoresist layer subsequently applied.
摘要翻译：本发明提供一种通过在含有氮的第一阻挡层的顶部沉积第二无氮阻挡层来形成阻挡膜以防止半导体器件中的中毒的方法。在第二阻挡层上形成低k电介质层。该技术保持了第一阻挡层的低漏电特性，并且减少随后施加的光致抗蚀剂层的氮中毒。

3. 发明授权

US06774057B1 Method and structure for forming dielectric layers having reduced dielectric constants 有权
标题翻译：用于形成具有降低的介电常数的介电层的方法和结构
公开(公告)号：US06774057B1
公开(公告)日：2004-08-10
申请号：US10180661
申请日：2002-06-25
申请人： Hong-Qiang Lu , Wei-Jen Hsia , Wilbur G. Catabay
发明人： Hong-Qiang Lu , Wei-Jen Hsia , Wilbur G. Catabay
IPC分类号： H01L2131
CPC分类号： H01L21/02126 , H01L21/02203 , H01L21/02321 , H01L21/02351 , H01L21/312 , H01L21/31695 , H01L21/7682
摘要： The present invention is directed to a semiconductor structure including a semiconductor substrate having at least one overlying layer formed thereon. The at least one overlying layer including at least one layer of dielectric material. The at least one layer of dielectric material including a protected region having a first dielectric constant and another porous region having a second dielectric constant wherein the value for the second dielectric constant is less than the first dielectric constant. The porous region having been formed by the implantation of a porosity inducing material into the porous region and subsequent annealing. A method for forming such structures is also included.
摘要翻译：本发明涉及包括其上形成有至少一个上覆层的半导体衬底的半导体结构。所述至少一个覆盖层包括至少一层电介质材料。所述至少一层介电材料包括具有第一介电常数的保护区和具有第二介电常数的另一多孔区，其中所述第二介电常数的值小于所述第一介电常数。已经通过将孔隙率诱导材料注入多孔区域并随后进行退火而形成多孔区域。还包括形成这种结构的方法。

4. 发明授权

US06503840B2 Process for forming metal-filled openings in low dielectric constant dielectric material while inhibiting via poisoning 有权
公开(公告)号：US06503840B2
公开(公告)日：2003-01-07
申请号：US09848758
申请日：2001-05-02
申请人： Wilbur G. Catabay , Wei-Jen Hsia , Hong-Qiang Lu , Yong-Bae Kim , Kiran Kumar , Kai Zhang , Richard Schinella , Philippe Schoenborn
发明人： Wilbur G. Catabay , Wei-Jen Hsia , Hong-Qiang Lu , Yong-Bae Kim , Kiran Kumar , Kai Zhang , Richard Schinella , Philippe Schoenborn
IPC分类号： H01L21302
CPC分类号： H01L21/31144 , H01L21/02063 , H01L21/31116 , H01L21/31138 , H01L21/31633 , H01L21/76802 , H01L21/76814 , H01L21/76826 , H01L21/76843
摘要： A composite layer of dielectric material is first formed over the integrated circuit structure, comprising a thin barrier layer of dielectric material, a layer of low k dielectric material over the barrier layer, and a thin capping layer of dielectric material over the layer of low k dielectric material. A photoresist mask, formed over the capping layer, is baked in the presence of UV light to cross-link the mask material. The composite layer is then etched through the resist mask using an etchant gas mixture including CO, but not oxygen. Newly exposed surfaces of low k dielectric material are then optionally densified to harden them. The resist mask is then removed using a plasma of a neutral or reducing gas. Exposed surfaces of low k dielectric material are then passivated by a low power oxygen plasma. Preferably, optional densification, mask removal, and passivation are all done in the same vacuum apparatus. The substrate is then solvent cleaned to remove etch residues and then annealed to degasify the low k dielectric material. The substrate is then RF cleaned and a thin layer of PVD titanium is then formed in the same chamber over the surfaces of the openings. CVD titanium nitride is then formed over the titanium in the same vacuum apparatus. The coated openings are then filled with aluminum, tungsten, or copper.

5. 发明授权

US07393780B2 Dual layer barrier film techniques to prevent resist poisoning 有权
标题翻译：双层阻挡膜技术，以防止中毒
公开(公告)号：US07393780B2
公开(公告)日：2008-07-01
申请号：US11418873
申请日：2006-05-04
申请人： Hong-Qiang Lu , Wei-Jen Hsia , Wilbur G. Catabay
发明人： Hong-Qiang Lu , Wei-Jen Hsia , Wilbur G. Catabay
IPC分类号： H01L21/4763
CPC分类号： H01L21/76829 , H01L21/31144 , H01L21/3148 , H01L21/76807 , H01L21/76808 , H01L21/7681 , H01L21/76832
摘要： Provided is a process for forming a barrier film to prevent resist poisoning in a semiconductor device by depositing a second nitrogen-free barrier layer on top of a first barrier layer containing nitrogen. A low-k dielectric layer is formed over the second barrier layer. This technique maintains the low electrical leakage characteristics of the first barrier layer and reduces nitrogen poisoning of a photoresist layer subsequently applied.
摘要翻译：本发明提供一种通过在含有氮的第一阻挡层的顶部沉积第二无氮阻挡层来形成阻挡膜以防止半导体器件中的中毒的方法。在第二阻挡层上形成低k电介质层。该技术保持了第一阻挡层的低漏电特性，并且减少随后施加的光致抗蚀剂层的氮中毒。

6. 发明授权

US06613665B1 Process for forming integrated circuit structure comprising layer of low k dielectric material having antireflective properties in an upper surface 有权
标题翻译：一种用于形成集成电路结构的方法，其包括在上表面具有抗反射特性的低k电介质材料层
公开(公告)号：US06613665B1
公开(公告)日：2003-09-02
申请号：US10002981
申请日：2001-10-26
申请人： Wilbur G. Catabay , Wei-Jen Hsia
发明人： Wilbur G. Catabay , Wei-Jen Hsia
IPC分类号： H01L214763
CPC分类号： H01L21/31144 , H01L21/0276 , H01L21/76807 , H01L21/76826
摘要： A process is disclosed for forming an integrated circuit structure characterized by formation of a combined dielectric layer and antireflective coating layer. The process comprises forming a layer of dielectric material over an integrated circuit structure, and treating the surface of the layer of dielectric material to form an antireflective coating (ARC) surface therein. When a layer of photoresist is then formed over the ARC surface, and the layer of photoresist is exposed to a pattern of radiation, the ARC surface improves the accuracy of the replication, in the photoresist layer, of the pattern of radiation. Preferably, the surface of the dielectric layer is treated with a plasma comprising ions of elements and/or compounds to form the ARC surface.
摘要翻译：公开了一种用于形成集成电路结构的方法，其特征在于形成组合的电介质层和抗反射涂层。该方法包括在集成电路结构上形成介电材料层，以及处理介电材料层的表面以在其中形成抗反射涂层（ARC）表面。当然后在ARC表面上形成一层光致抗蚀剂，并且光致抗蚀剂层暴露于辐射图形时，ARC表面提高了光致抗蚀剂层中辐射图案复制的准确性。优选地，用包含元素和/或化合物的离子的等离子体处理介电层的表面以形成ARC表面。

7. 发明授权

US06204192B1 Plasma cleaning process for openings formed in at least one low dielectric constant insulation layer over copper metallization in integrated circuit structures 有权
标题翻译：在集成电路结构中的铜金属化的至少一个低介电常数绝缘层中形成的开口的等离子体清洁工艺
公开(公告)号：US06204192B1
公开(公告)日：2001-03-20
申请号：US09281602
申请日：1999-03-29
申请人： Joe W. Zhao , Wei-Jen Hsia , Wilbur G. Catabay
发明人： Joe W. Zhao , Wei-Jen Hsia , Wilbur G. Catabay
IPC分类号： H01L2100
CPC分类号： H01L21/02063 , H01L21/31116 , H01L21/7681 , H01L21/76814 , H01L21/76826
摘要： A process is provided for removing etch residues from one or more openings formed in one or more layers of a low dielectric constant insulation material over a copper metal interconnect layer of an integrated circuit structure which includes cleaning exposed portions of the surface of the copper interconnect layer at the bottom of the one or more openings, the process comprising providing an anisotropic hydrogen plasma to cause a chemical reaction between ions in the plasma and the etch residues in the bottom of the one or more opening, including copper oxide on the exposed copper surface, to thereby clean the exposed portions of the copper surface, and to remove the etch residues without sputtering the copper at the bottom of the opening.
摘要翻译：提供了一种用于从集成电路结构的铜金属互连层上去除在低介电常数绝缘材料的一层或多层中形成的一个或多个开口的蚀刻残留物的工艺，其包括清洁铜互连层的表面的暴露部分在一个或多个开口的底部，该方法包括提供各向异性氢等离子体以引起等离子体中的离子与一个或多个开口底部的蚀刻残留物（包括暴露的铜表面上的氧化铜）的化学反应，从而清洁铜表面的暴露部分，并且在不溅射开口底部的铜的情况下除去蚀刻残留物。

8. 发明授权

US5789028A Method for eliminating peeling at end of semiconductor substrate in metal organic chemical vapor deposition of titanium nitride 失效
标题翻译：在氮化钛的金属有机化学气相沉积中消除半导体衬底端部剥离的方法
公开(公告)号：US5789028A
公开(公告)日：1998-08-04
申请号：US811818
申请日：1997-03-04
申请人： Joe W. Zhao , Wei-Jen Hsia , Wilbur G. Catabay
发明人： Joe W. Zhao , Wei-Jen Hsia , Wilbur G. Catabay
IPC分类号： C23C16/34 , C23C16/44 , C23C16/455 , H01L21/28 , H01L21/285
CPC分类号： C23C16/45521 , C23C16/34 , C23C16/455
摘要： A process and apparatus are described for inhibiting, but not completely eliminating, the deposition of titanium nitride by MOCVD on the end edge of a semiconductor substrate which comprises directing toward such substrate end edge a flow of one or more deposition-inhibiting gases in a direction which substantially opposes the flow of process gases toward the end edges of the substrate. This flow of deposition-inhibiting gases toward the end edges of the substrate reduces the deposition of the titanium nitride at the end edge of the semiconductor substrate either by directing some of the flow of process gases away from such end edge of the substrate, or by locally diluting such process gases in the region of the deposition chamber adjacent the end edge of the substrate, or by some combination of the foregoing. Such flow of deposition-inhibiting gas or gases may be directed toward the end edge of the substrate by flowing such deposition-inhibiting gas or gases through bores provided in the underlying substrate support pedestal which bores have openings peripherally spaced around the pedestal, adjacent the top of the pedestal, through which such gas or gases then exit beneath the plane of the top surface of the substrate and adjacent the end edge of the substrate.
摘要翻译：描述了一种方法和装置，用于通过MOCVD在半导体衬底的端部边缘上抑制但不完全消除氮化钛的沉积，该方法包括将一个或多个沉积抑制气体沿着方向其基本上反对处理气体朝向基板的端部边缘的流动。这种沉积抑制气体朝向衬底的端部边缘的流动减少了氮化钛在半导体衬底的端部边缘处的沉积，或者通过将一些工艺气体流从衬底的这种端部边缘引导，或者通过在邻近衬底的端边缘的沉积室的区域中或通过前述的某些组合来局部稀释这些工艺气体。这种沉积抑制气体或气体的流动可以通过使这种沉积抑制气体或气体通过设置在下面的基底支撑基座中的孔而被引向衬底的端部边缘，孔中具有围绕基座周向间隔开的开口，邻近顶部基座的这种气体或气体然后在衬底的顶表面的平面之下离开并且靠近衬底的端边缘。

9. 发明授权

US07259462B1 Interconnect dielectric tuning 有权
标题翻译：互连电介质调谐
公开(公告)号：US07259462B1
公开(公告)日：2007-08-21
申请号：US11419548
申请日：2006-05-22
申请人： Wai Lo , Hong Lin , Shiqun Gu , Wilbur G. Catabay , Zhihai Wang , Wei-Jen Hsia
发明人： Wai Lo , Hong Lin , Shiqun Gu , Wilbur G. Catabay , Zhihai Wang , Wei-Jen Hsia
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/7682 , H01L21/76838 , H01L23/5222 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An improvement to a method of forming an integrated circuit. An etch stop layer is formed to overlie the front end processing layers of the integrated circuit. Support structures are formed that are disposed so as to support electrically conductive interconnects on various levels of the integrated circuit. Substantially all of the non electrically conductive layers above the etch stop layer that were formed during the fabrication of the interconnects are removed.
摘要翻译：对形成集成电路的方法的改进。形成蚀刻停止层以覆盖集成电路的前端处理层。形成支撑结构，其被布置为支撑集成电路的各个级别上的导电互连。基本上去除了在制造互连期间形成的蚀刻停止层上方的所有非导电层。

10. 发明授权

US06930056B1 Plasma treatment of low dielectric constant dielectric material to form structures useful in formation of metal interconnects and/or filled vias for integrated circuit structure 失效
标题翻译：低介电常数介电材料的等离子体处理，以形成用于形成用于集成电路结构的金属互连和/或填充通孔的结构
公开(公告)号：US06930056B1
公开(公告)日：2005-08-16
申请号：US09884736
申请日：2001-06-19
申请人： Wilbur G. Catabay , Wei-Jen Hsia
发明人： Wilbur G. Catabay , Wei-Jen Hsia
IPC分类号： H01L21/3105 , H01L21/311 , H01L21/768 , H01L21/31 , H01L21/469
CPC分类号： H01L21/76829 , H01L21/31058 , H01L21/31138 , H01L21/76801 , H01L21/76807 , H01L21/7681 , H01L21/76825
摘要： A process for forming an integrated circuit structure comprises forming a layer of low k dielectric material over a previously formed integrated circuit structure, and treating the upper surface of the layer of low k dielectric material with a plasma to form a layer of densified dielectric material over the remainder of the underlying layer of low k dielectric material, forming a second layer of low k dielectric material over the layer of densified dielectric material, and treating this second layer of low k dielectric material to form a second layer of densified dielectric material over the second layer of low k dielectric material. The layer or layers of densified dielectric material formed from the low k dielectric material provide mechanical support and can then function as etch stop and mask layers for the formation of vias and/or trenches.
摘要翻译：一种用于形成集成电路结构的工艺包括在先前形成的集成电路结构上形成低k电介质材料层，并用等离子体处理低k电介质材料层的上表面以形成一层致密的电介质材料，低k介电材料的下层的剩余部分，在致密化介电材料层上形成第二层低k电介质材料层，并处理该第二层低k电介质材料以形成第二层致密电介质材料第二层低k电介质材料。由低k电介质材料形成的致密化介电材料的层或层提供机械支撑，并且然后可以用作用于形成通孔和/或沟槽的蚀刻停止层和掩模层。

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