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1. 发明授权

US07427563B2 Dielectric barrier films for use as copper barrier layers in semiconductor trench and via structures 有权
标题翻译：用作半导体沟槽和通孔结构中的铜阻挡层的介电阻挡膜
公开(公告)号：US07427563B2
公开(公告)日：2008-09-23
申请号：US11131003
申请日：2005-05-16
申请人： Hong-Qiang Lu , Peter A. Burke , Wilbur G. Catabay
发明人： Hong-Qiang Lu , Peter A. Burke , Wilbur G. Catabay
IPC分类号： H01L21/4763
CPC分类号： H01L21/02211 , H01L21/02126 , H01L21/02167 , H01L21/02315 , H01L21/02348 , H01L21/02351 , H01L21/3121 , H01L21/76807 , H01L21/76826 , H01L21/76831 , H01L21/76832 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： The present invention is directed to improved dielectric copper barrier layer and related interconnect structures. One structure includes a semiconductor substrate having a copper line. An insulating layer formed of at least one of silicon and carbon is formed on the underlying copper line. An opening is formed in the insulating layer to expose a portion of the copper line. The inner surface of the opening in the insulating layer has a dielectric barrier layer formed thereon to prevent the diffusion of copper into the insulating layer. A copper plug is formed to fill the opening and make electrical contact with the underlying copper interconnect structure. Aspects of the invention also include methods for forming the dielectric copper barrier layers and associate copper interconnects to the underlying copper lines.
摘要翻译：本发明涉及改进的介电铜阻挡层和相关互连结构。一种结构包括具有铜线的半导体衬底。在下面的铜线上形成由硅和碳中的至少一种形成的绝缘层。在绝缘层中形成开口以露出铜线的一部分。绝缘层中的开口的内表面具有形成在其上的电介质阻挡层，以防止铜扩散到绝缘层中。形成铜塞以填充开口并与下面的铜互连结构电接触。本发明的方面还包括用于形成电介质铜阻挡层和将铜互连连接到下面的铜线的方法。

2. 发明授权

US07646077B2 Methods and structure for forming copper barrier layers integral with semiconductor substrates structures 有权
标题翻译：用于形成与半导体衬底结构成一体的铜阻挡层的方法和结构
公开(公告)号：US07646077B2
公开(公告)日：2010-01-12
申请号：US12191171
申请日：2008-08-13
申请人： Hong-Qiang Lu , Peter A. Burke , Wilbur G. Catabay
发明人： Hong-Qiang Lu , Peter A. Burke , Wilbur G. Catabay
IPC分类号： H01L23/58 , H01L21/4763
CPC分类号： H01L21/02211 , H01L21/02126 , H01L21/02167 , H01L21/02315 , H01L21/02348 , H01L21/02351 , H01L21/3121 , H01L21/76807 , H01L21/76826 , H01L21/76831 , H01L21/76832 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： The present invention is directed to improved dielectric copper barrier layer and related interconnect structures. One structure includes a semiconductor substrate having a copper line. An insulating layer formed of at least one of silicon and carbon is formed on the underlying copper line. An opening is formed in the insulating layer to expose a portion of the copper line. The inner surface of the opening in the insulating layer has a dielectric barrier layer formed thereon to prevent the diffusion of copper into the insulating layer. A copper plug is formed to fill the opening and make electrical contact with the underlying copper interconnect structure. Aspects of the invention also include methods for forming the dielectric copper barrier layers and associate copper interconnects to the underlying copper lines.
摘要翻译：本发明涉及改进的介电铜阻挡层和相关互连结构。一种结构包括具有铜线的半导体衬底。在下面的铜线上形成由硅和碳中的至少一种形成的绝缘层。在绝缘层中形成开口以露出铜线的一部分。绝缘层中的开口的内表面具有形成在其上的电介质阻挡层，以防止铜扩散到绝缘层中。形成铜塞以填充开口并与下面的铜互连结构电接触。本发明的方面还包括用于形成电介质铜阻挡层和将铜互连连接到下面的铜线的方法。

3. 发明授权

US06939800B1 Dielectric barrier films for use as copper barrier layers in semiconductor trench and via structures 失效
公开(公告)号：US06939800B1
公开(公告)日：2005-09-06
申请号：US10321938
申请日：2002-12-16
申请人： Hong-Qiang Lu , Peter A. Burke , Wilbur G. Catabay
发明人： Hong-Qiang Lu , Peter A. Burke , Wilbur G. Catabay
IPC分类号： H01L21/312 , H01L21/44 , H01L21/4763 , H01L21/768 , H01L23/532
CPC分类号： H01L21/02211 , H01L21/02126 , H01L21/02167 , H01L21/02315 , H01L21/02348 , H01L21/02351 , H01L21/3121 , H01L21/76807 , H01L21/76826 , H01L21/76831 , H01L21/76832 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： The present invention is directed to improved dielectric copper barrier layer and related interconnect structures. One structure includes a semiconductor substrate having a copper line. An insulating layer formed of at least one of silicon and carbon is formed on the underlying copper line. An opening is formed in the insulating layer to expose a portion of the copper line. The inner surface of the opening in the insulating layer has a dielectric barrier layer formed thereon to prevent the diffusion of copper into the insulating layer. A copper plug is formed to fill the opening and make electrical contact with the underlying copper interconnect structure. Aspects of the invention also include methods for forming the dielectric copper barrier layers and associate copper interconnects to the underlying copper lines.

4. 发明申请

US20100200993A1 DIELECTRIC BARRIER LAYER FOR INCREASING ELECTROMIGRATION LIFETIMES IN COPPER INTERCONNECT STRUCTURES 有权
标题翻译：用于增加铜互连结构中电磁寿命的电介质障碍层
公开(公告)号：US20100200993A1
公开(公告)日：2010-08-12
申请号：US12764004
申请日：2010-04-20
申请人： Hao Cui , Peter A. Burke , Wilbur G. Catabay
发明人： Hao Cui , Peter A. Burke , Wilbur G. Catabay
IPC分类号： H01L23/532 , H01L21/31
CPC分类号： H01L21/76832 , H01L21/76825 , H01L21/76826 , H01L21/76834 , H01L21/76883
摘要： Embodiments of the invention include a copper interconnect structure having increased electromigration lifetime. Such structures can include a semiconductor substrate having a copper layer formed thereon. A dielectric barrier stack is formed on the copper layer. The dielectric barrier stack includes a first portion formed adjacent to the copper layer and a second portion formed on the first portion, the first portion having improved adhesion to copper relative to the second portion and both portions are formed having resistance to copper diffusion. The invention also includes several embodiments for constructing such structures. Adhesion of the dielectric barrier stack to copper can be increased by plasma treating or ion implanting selected portions of the dielectric barrier stack with adhesion enhancing materials to increase the concentration of such materials in the stack.
摘要翻译：本发明的实施例包括具有增加的电迁移寿命的铜互连结构。这种结构可以包括其上形成有铜层的半导体衬底。在铜层上形成介电阻挡层叠体。电介质势垒叠层包括邻近铜层形成的第一部分和形成在第一部分上的第二部分，第一部分具有相对于第二部分具有改善的对铜的粘合性，并且两个部分形成为具有耐铜扩散性。本发明还包括用于构造这种结构的几个实施例。可以通过等离子体处理或离子注入电介质阻挡层的选定部分与粘合增强材料来增加电介质阻挡层与铜的附着，以增加堆叠中这种材料的浓度。

5. 发明授权

US08043968B2 Dielectric barrier layer for increasing electromigration lifetimes in copper interconnect structures 有权
标题翻译：用于增加铜互连结构中的电迁移寿命的介电阻挡层
公开(公告)号：US08043968B2
公开(公告)日：2011-10-25
申请号：US12764004
申请日：2010-04-20
申请人： Hao Cui , Peter A. Burke , Wilbur G. Catabay
发明人： Hao Cui , Peter A. Burke , Wilbur G. Catabay
IPC分类号： H01L21/00
CPC分类号： H01L21/76832 , H01L21/76825 , H01L21/76826 , H01L21/76834 , H01L21/76883
摘要： Embodiments of the invention include a copper interconnect structure having increased electromigration lifetime. Such structures can include a semiconductor substrate having a copper layer formed thereon. A dielectric barrier stack is formed on the copper layer. The dielectric barrier stack includes a first portion formed adjacent to the copper layer and a second portion formed on the first portion, the first portion having improved adhesion to copper relative to the second portion and both portions are formed having resistance to copper diffusion. The invention also includes several embodiments for constructing such structures. Adhesion of the dielectric barrier stack to copper can be increased by plasma treating or ion implanting selected portions of the dielectric barrier stack with adhesion enhancing materials to increase the concentration of such materials in the stack.
摘要翻译：本发明的实施例包括具有增加的电迁移寿命的铜互连结构。这种结构可以包括其上形成有铜层的半导体衬底。在铜层上形成介电阻挡层叠体。电介质势垒叠层包括邻近铜层形成的第一部分和形成在第一部分上的第二部分，第一部分具有相对于第二部分提高的对铜的粘附性，并且两个部分形成为具有耐铜扩散性。本发明还包括用于构造这种结构的几个实施例。可以通过等离子体处理或离子注入电介质阻挡层的选定部分与粘合增强材料来增加电介质阻挡层与铜的附着，以增加堆叠中这种材料的浓度。

6. 发明授权

US07728433B2 Dielectric barrier layer for increasing electromigration lifetimes in copper interconnect structures 失效
标题翻译：用于增加铜互连结构中的电迁移寿命的介电阻挡层
公开(公告)号：US07728433B2
公开(公告)日：2010-06-01
申请号：US11736402
申请日：2007-04-17
申请人： Hao Cui , Peter A. Burke , Wilbur G. Catabay
发明人： Hao Cui , Peter A. Burke , Wilbur G. Catabay
IPC分类号： H01L29/40
CPC分类号： H01L21/76832 , H01L21/76825 , H01L21/76826 , H01L21/76834 , H01L21/76883
摘要： Embodiments of the invention include a copper interconnect structure having increased electromigration lifetime. Such structures can include a semiconductor substrate having a copper layer formed thereon. A dielectric barrier stack is formed on the copper layer. The dielectric barrier stack includes a first portion formed adjacent to the copper layer and a second portion formed on the first portion, the first portion having improved adhesion to copper relative to the second portion and both portions are formed having resistance to copper diffusion. The invention also includes several embodiments for constructing such structures. Adhesion of the dielectric barrier stack to copper can be increased by plasma treating or ion implanting selected portions of the dielectric barrier stack with adhesion enhancing materials to increase the concentration of such materials in the stack.
摘要翻译：本发明的实施例包括具有增加的电迁移寿命的铜互连结构。这种结构可以包括其上形成有铜层的半导体衬底。在铜层上形成介电阻挡层叠体。电介质势垒叠层包括邻近铜层形成的第一部分和形成在第一部分上的第二部分，第一部分具有相对于第二部分具有改善的对铜的粘合性，并且两个部分形成为具有耐铜扩散性。本发明还包括用于构造这种结构的几个实施例。可以通过等离子体处理或离子注入电介质阻挡层的选定部分与粘合增强材料来增加电介质阻挡层与铜的附着，以增加堆叠中这种材料的浓度。

7. 发明授权

US07276441B1 Dielectric barrier layer for increasing electromigration lifetimes in copper interconnect structures 有权
标题翻译：用于增加铜互连结构中的电迁移寿命的介电阻挡层
公开(公告)号：US07276441B1
公开(公告)日：2007-10-02
申请号：US10414601
申请日：2003-04-15
申请人： Hao Cui , Peter A. Burke , Wilbur G. Catabay
发明人： Hao Cui , Peter A. Burke , Wilbur G. Catabay
IPC分类号： H01L21/44 , H01L29/40 , H01L23/532
CPC分类号： H01L21/76832 , H01L21/76825 , H01L21/76826 , H01L21/76834 , H01L21/76883
摘要： Embodiments of the invention include a copper interconnect structure having increased electromigration lifetime. Such structures can include a semiconductor substrate having a copper layer formed thereon. A dielectric barrier stack is formed on the copper layer. The dielectric barrier stack includes a first portion formed adjacent to the copper layer and a second portion formed on the first portion, the first portion having improved adhesion to copper relative to the second portion and both portions are formed having resistance to copper diffusion. The invention also includes several embodiments for constructing such structures. Adhesion of the dielectric barrier stack to copper can be increased by plasma treating or ion implanting selected portions of the dielectric barrier stack with adhesion enhancing materials to increase the concentration of such materials in the stack.
摘要翻译：本发明的实施例包括具有增加的电迁移寿命的铜互连结构。这种结构可以包括其上形成有铜层的半导体衬底。在铜层上形成介电阻挡层叠体。电介质势垒叠层包括邻近铜层形成的第一部分和形成在第一部分上的第二部分，第一部分具有相对于第二部分具有改善的对铜的粘合性，并且两个部分形成为具有耐铜扩散性。本发明还包括用于构造这种结构的几个实施例。可以通过等离子体处理或离子注入电介质阻挡层的选定部分与粘合增强材料来增加电介质阻挡层与铜的附着，以增加堆叠中这种材料的浓度。

8. 发明授权

US06905909B2 Ultra low dielectric constant thin film 失效
标题翻译：超低介电常数薄膜
公开(公告)号：US06905909B2
公开(公告)日：2005-06-14
申请号：US10691400
申请日：2003-10-22
申请人： Hao Cui , Peter A. Burke , Wilbur G. Catabay
发明人： Hao Cui , Peter A. Burke , Wilbur G. Catabay
IPC分类号： C23C16/32 , H01L21/00 , H01L21/314 , H01L21/46 , H01L21/768 , H01L29/15
CPC分类号： H01L21/02167 , C23C16/325 , H01L21/022 , H01L21/02274 , H01L21/3148 , H01L21/76801 , H01L21/76807 , H01L21/76826 , H01L21/76828
摘要： A method for forming a substantially oxygen-free silicon carbide layer on a substrate, where the silicon carbide layer has a dielectric constant of less than about four. The substrate is held at a deposition temperature of between about zero centigrade and about one hundred centigrade, and a gas flow of tetramethylsilane is introduced at a rate of no more than about one thousand scientific cubic centimeters per minute. The deposition pressure is held between about one milli Torr and about one hundred Torr, and a radio frequency plasma discharge is produced with a power of no more than about two kilowatts. The plasma discharge is halted when a desired thickness of the silicon carbide layer has been formed.
摘要翻译：在基底上形成基本上无氧的碳化硅层的方法，其中碳化硅层的介电常数小于约4。基板保持在约零摄氏度和约百摄氏度之间的沉积温度，并且以不超过约一千科学立方厘米每分钟的速率引入四甲基硅烷的气流。沉积压力保持在约1毫乇至约100乇之间，并且以不大于约2千瓦的功率产生射频等离子体放电。当形成所需的碳化硅层厚度时，等离子体放电停止。

9. 发明授权

US06955937B1 Carbon nanotube memory cell for integrated circuit structure with removable side spacers to permit access to memory cell and process for forming such memory cell 失效
标题翻译：用于集成电路结构的碳纳米管存储单元，其具有可拆卸侧面间隔件，以允许访问存储器单元和用于形成这种存储器单元的
公开(公告)号：US06955937B1
公开(公告)日：2005-10-18
申请号：US10917551
申请日：2004-08-12
申请人： Peter A. Burke , Sey-Shing Sun , Hong-Qiang Lu
发明人： Peter A. Burke , Sey-Shing Sun , Hong-Qiang Lu
IPC分类号： G11C13/02 , H01L21/00 , H01L27/10
CPC分类号： H01L27/10 , B82Y10/00 , G11C13/025 , G11C2213/16 , Y10S977/943
摘要： A carbon nanotube memory cell for an integrated circuit wherein a chamber is constructed in a layer of a dielectric material such as silicon nitride down to a first electrical contact. This chamber is filled with polysilicon. A layer of a carbon nanotube mat or ribbon is formed over the silicon nitride layer and the chamber. A dielectric material, such as an oxide layer, is formed over the nanotube strips and patterned to form an upper chamber down to the ribbon layer to permit the ribbon to move into the upper chamber or into the lower chamber. The upper chamber is then filled with polysilicon. A silicon nitride layer is formed over the oxide layer and a contact opening is formed down to the ribbon and filled with tungsten that is then patterned to form metal lines. Any exposed silicon nitride is removed. A polysilicon layer is formed over the tungsten lines and anisotropically etched to remove polysilicon on the horizontal surfaces but leave polysilicon sidewall spacers. A silicon oxide layer is deposited over the structure and also anisotropically etched forming silicon oxide sidewall spacers on the polysilicon sidewall spacers. The polysilicon is wet etched with an etchant selective to adjacent materials to remove the polysilicon sidewalls spacers and all of the polysilicon in the chambers. Silicon oxide is formed over the structure and into the upper portion of the openings to seal the now empty chambers. A passivation layer may then be formed.
摘要翻译：一种用于集成电路的碳纳米管存储单元，其中室被构造成电介质材料如氮化硅的层，直到第一电接触。这个房间里充满了多晶硅。在氮化硅层和室之上形成一层碳纳米管垫或带。在纳米管条之上形成电介质材料，例如氧化物层，并被图案化以形成一个向下到带状层的上部腔室，以使带状物移动到上部腔室或下部腔室中。然后，上部室充满多晶硅。在氧化物层上形成氮化硅层，并且向下形成接触开口，并且填充有钨，然后将其图案化以形成金属线。任何暴露的氮化硅被去除。在钨线上形成多晶硅层，并进行各向异性蚀刻以去除水平表面上的多晶硅，但留下多晶硅侧壁间隔物。在结构上沉积氧化硅层，并且还各向异性地蚀刻在多晶硅侧壁间隔物上形成氧化硅侧壁间隔物。用对相邻材料选择性的蚀刻剂湿式蚀刻多晶硅以去除多晶硅侧壁间隔物和室中的所有多晶硅。在结构上形成氧化硅并进入开口的上部，以密封现在的空腔。然后可以形成钝化层。

10. 发明授权

US08552535B2 Trench shielding structure for semiconductor device and method 有权
标题翻译：半导体器件的沟槽屏蔽结构及方法
公开(公告)号：US08552535B2
公开(公告)日：2013-10-08
申请号：US12271068
申请日：2008-11-14
申请人： Peter A. Burke , Brian Pratt , Prasad Venkatraman
发明人： Peter A. Burke , Brian Pratt , Prasad Venkatraman
IPC分类号： H01L29/66
CPC分类号： H01L29/4236 , H01L29/0696 , H01L29/401 , H01L29/407 , H01L29/41741 , H01L29/41766 , H01L29/42372 , H01L29/4238 , H01L29/456 , H01L29/4925 , H01L29/4933 , H01L29/66734 , H01L29/7811 , H01L29/7813 , H01L2924/0002 , H01L2924/00
摘要： A shielding structure for a semiconductor device includes a plurality of trenches. The trenches include passivation liners and shield electrodes, which are formed therein. In one embodiment, the shielding structure is placed beneath a control pad. In another embodiment, the shielding structure is placed beneath a control runner.
摘要翻译：用于半导体器件的屏蔽结构包括多个沟槽。沟槽包括形成在其中的钝化衬垫和屏蔽电极。在一个实施例中，屏蔽结构位于控制板下方。在另一个实施例中，屏蔽结构放置在控制转轮下方。

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