专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06355971B2 Semiconductor switch devices having a region with three distinct zones and their manufacture 失效
标题翻译：具有具有三个不同区域的区域及其制造的半导体开关器件
公开(公告)号：US06355971B2
公开(公告)日：2002-03-12
申请号：US09257631
申请日：1999-02-25
申请人： Holger Schligtenhorst , Godefridus A. M. Hurkx , Andrew M. Warwick
发明人： Holger Schligtenhorst , Godefridus A. M. Hurkx , Andrew M. Warwick
IPC分类号： H01L2970
CPC分类号： H01L29/66136 , H01L29/66295 , H01L29/7325 , H01L29/868
摘要： In a semiconductor switch device such as an NPN transistor (T) or a power switching diode (D), a multiple-zone first region (1) of one conductivity type forms a switchable p-n junction (12) with a second region (2) of opposite conductivity type. In accordance with the invention, this first region (1) includes three distinct zones, namely a low-doped zone (23), a high-doped zone (25), and an intermediate additional zone (24). The low-doped zone (23) is provided by a semiconductor body portion (11) having a substantially uniform p-type doping concentration (P−) and forms the p-n junction (12) with the second region (2). The distinct additional zone (24) is present between the low-doped zone (23) and the high-doped zone (25). The high-doped zone (25) which may form a contact zone has a doping concentration (P++) which is higher than that of the low-doped zone (23) and which decreases towards the low-doped zone (23). The distinct additional zone (24) has an additional doping concentration (P+) which is lower than the doping concentration (P++) of the high-doped zone (25) and which decreases towards the low-doped zone (23). This triple-zone formation for the first region (1) permits an improvement in switching behaviour, e.g. in terms of fall-time and energy dissipation during turn-off of the device (T, D). A very low doping (P−) can be used for low-doped zone (23) so that, in the off-state of the device (T, D), this zone (23) and also the additional zone (24) can be fully depleted. The additional zone (24) having its additional doping concentration provides a path for extracting residual charge carriers from the low-doped zone (23) when the device (T, D) is being switched off.
摘要翻译：在诸如NPN晶体管（T）或功率开关二极管（D）的半导体开关器件中，一个导电类型的多区域第一区域（1）形成具有第二区域（2）的可切换pn结（12）的相反导电类型。根据本发明，该第一区域（1）包括三个不同的区域，即低掺杂区域（23），高掺杂区域（25）和中间附加区域（24）。低掺杂区域（23）由具有基本均匀的p型掺杂浓度（P-）的半导体本体部分（11）提供，并与第二区域（2）形成p-n结（12）。不同的附加区（24）存在于低掺杂区（23）和高掺杂区（25）之间。可形成接触区的高掺杂区（25）具有高于低掺杂区（23）的掺杂浓度（P ++），并且朝向低掺杂区（23）减小。不同的附加区域（24）具有低于高掺杂区域（25）的掺杂浓度（P ++）的附加掺杂浓度（P +），并且朝向低掺杂区域（23）减小。用于第一区域（1）的这种三区形成允许改变开关行为，例如，在设备（T，D）关闭期间的下降时间和能量耗散方面。对于低掺杂区域（23），可以使用非常低的掺杂（P-），使得在器件（T，D）的截止状态下，该区域（23）以及附加区域（24）可以充分耗尽具有其附加掺杂浓度的附加区域（24）提供了当器件（T，D）被切断时从低掺杂区域（23）提取残余电荷载流子的路径。

2. 发明授权

US5387528A Method of manufacturing a semiconductor device comprising an insulated gate field effect device 失效
标题翻译：制造包括绝缘栅场效应器件的半导体器件的方法
公开(公告)号：US5387528A
公开(公告)日：1995-02-07
申请号：US95972
申请日：1993-07-22
申请人： Keith M. Hutchings , Andrew L. Goodyear , Andrew M. Warwick
发明人： Keith M. Hutchings , Andrew L. Goodyear , Andrew M. Warwick
IPC分类号： H01L21/336 , H01L29/06 , H01L29/10 , H01L29/78 , H01L21/265
CPC分类号： H01L29/1095 , H01L29/7813 , H01L29/0696 , Y10S148/126
摘要： A semiconductor body (3) has a first region (4) of one conductivity type adjacent one major surface (5). A first masking layer (6) comprising at least one first mask window (6a) spaced from a second mask window (6b) is defined on the surface (5). Opposite conductivity type impurities are then introduced through the first masking layer (6) and a second masking layer (8) which is selectively removable with respect to the first masking layer (6) is subsequently provided on the first masking layer and patterned to leave a mask area (8a) covering the first mask window (6a). The semiconductor body (3) is then etched through the second mask window (6b) to define a recess (9) extending into the first region (4) while leaving the introduced impurities beneath the masked first mask window (6a) to form a relatively highly doped second region (7). The first and second masking layers (6 and 8) are removed and an insulated gate structure (10) is provided by defining a gate insulating layer (10a) on the recess walls (9a) and providing a gate conductive region (10b) on the insulating layer (10a). A relatively lowly doped third region (11) of the opposite conductivity type is provided to extend between the relatively highly doped second region (7) and the recess (9) to provide a conduction channel area (11a) adjacent the insulated gate structure (10). A fourth region (12) is provided to form a potential barrier (12a) with the relatively lowly doped third region (11) so that the conduction channel area (11a) provides a conductive path between the fourth and first regions (12 and 4).
摘要翻译：半导体本体（3）具有邻近一个主表面（5）的一种导电类型的第一区域（4）。在表面（5）上限定包括与第二掩模窗口（6b）间隔开的至少一个第一掩模窗口（6a）的第一掩模层（6）。然后通过第一掩模层（6）引入相对导电类型的杂质，随后在第一掩模层（6）上选择性地除去第二掩模层（8），并且图案化以留下掩蔽区域（8a）覆盖第一掩模窗口（6a）。然后，通过第二掩模窗口（6b）蚀刻半导体本体（3），以限定延伸到第一区域（4）中的凹陷（9），同时在被掩蔽的第一掩模窗口（6a）之下留下引入的杂质以形成相对高度掺杂的第二区域（7）。去除第一和第二掩蔽层（6和8），并且通过在凹壁（9a）上限定栅极绝缘层（10a）并在其上提供栅极导电区域（10b）来提供绝缘栅极结构（10）绝缘层（10a）。提供相对导电类型的相对低掺杂的第三区域（11）以在相对高度掺杂的第二区域（7）和凹部（9）之间延伸，以提供邻近绝缘栅极结构（10）的导电沟道区域（11a））。第四区域（12）被提供以形成具有相对低掺杂的第三区域（11）的势垒（12a），使得导通通道区域（11a）在第四区域和第一区域（12和4）之间提供导电路径，。

3. 发明授权

US06515332B1 Insulated-gate field-effect semiconductor device 失效
标题翻译：绝缘栅场效应半导体器件
公开(公告)号：US06515332B1
公开(公告)日：2003-02-04
申请号：US09505987
申请日：2000-02-16
申请人： Andrew M. Warwick
发明人： Andrew M. Warwick
IPC分类号： H01L2701
CPC分类号： H01L29/7824 , H01L27/1203 , H01L29/1079 , H01L29/402 , H01L29/41733 , H01L29/41758 , H01L29/41775 , H01L29/42356 , H01L29/4236 , H01L29/42372 , H01L29/42376 , H01L29/78 , H01L29/7818 , H01L29/78612 , H01L29/78624 , H01L29/78645 , H01L2924/0002 , H01L2924/00
摘要： An insulated-gate field-effect semiconductor device, preferably of the SOI type, has source (3) and drain (4) regions in a semiconductor body portion (1) at a first major surface of a semiconductor substrate (10). The gate-terminal metallisation (25) is present at an opposite second major surface (12) of the substrate (10). A gate connection (15,55) is present between the gate electrode (5) and the substrate (10) to connect the gate electrode (5) to the gate-terminal metallisation (25). This arrangement permits better use of the layout area for source-terminal and drain-terminal metallisations, and their connections, at the upper major surface (11) of the body portion (1), without introducing an on-resistance penalty. The part of the gate connection provided by the substrate (10) does not increase the on-resistance of the main current path through the device, i.e. between the source (3) and drain (4). Furthermore, a p-n junction diode can be readily integrated between the channel region (2) and the gate connection (15,55).
摘要翻译：优选为SOI型的绝缘栅场效应半导体器件在半导体衬底（10）的第一主表面处的半导体主体部分（1）中具有源极（3）和漏极（4）。栅极端子金属化（25）存在于衬底（10）的相对的第二主表面（12）处。在栅电极（5）和衬底（10）之间存在栅极连接（15,55），以将栅电极（5）连接到栅极端子金属化（25）。这种布置允许在主体部分（1）的上主表面（11）处更好地使用用于源极端子和漏极端子金属的布局区域以及它们的连接，而不引入导通电阻损失。由衬底（10）提供的栅极连接的部分不增加通过器件的主电流通路，即在源极（3）和漏极（4）之间的导通电阻。此外，p-n结二极管可以容易地集成在沟道区域（2）和栅极连接（15,55）之间。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式