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1. 发明申请

US20180130898A1 Ruggedized Symmetrically Bidirectional Bipolar Power Transistor 审中-公开
公开(公告)号：US20180130898A1
公开(公告)日：2018-05-10
申请号：US15604822
申请日：2017-05-25
申请人： Ideal Power, Inc.
发明人： Richard A. Blanchard , William C. Alexander
IPC分类号： H01L29/747 , H01L29/74 , H01L29/06 , H01L29/40 , H01L29/66
CPC分类号： H01L29/747 , H01L29/0623 , H01L29/0649 , H01L29/0696 , H01L29/1004 , H01L29/16 , H01L29/404 , H01L29/407 , H01L29/408 , H01L29/66234 , H01L29/66295 , H01L29/66386 , H01L29/705 , H01L29/73 , H01L29/732 , H01L29/7424
摘要： The present application teaches, among other innovations, power semiconductor devices in which breakdown initiation regions, on BOTH sides of a die, are located inside the emitter/collector regions, but laterally spaced away from insulated trenches which surround the emitter/collector regions. Preferably this is part of a symmetrically-bidirectional power device of the “B-TRAN” type. In one advantageous group of embodiments (but not all), the breakdown initiation regions are defined by dopant introduction through the bottom of trench portions which lie within the emitter/collector region. In one group of embodiments (but not all), these can advantageously be separated trench portions which are not continuous with the trench(es) surrounding the emitter/collector region(s).

2. 发明申请

US20170338324A1 MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：US20170338324A1
公开(公告)日：2017-11-23
申请号：US15672097
申请日：2017-08-08
申请人： Renesas Electronics Corporation
发明人： Toshikazu HANAWA
IPC分类号： H01L29/66 , H01L29/423 , H01L29/417 , H01L29/08 , H01L21/02 , H01L21/311 , H01L21/266 , H01L29/732 , H01L29/10
CPC分类号： H01L29/66295 , H01L21/0206 , H01L21/02238 , H01L21/02255 , H01L21/266 , H01L21/31111 , H01L21/31116 , H01L29/0692 , H01L29/0804 , H01L29/1004 , H01L29/41708 , H01L29/42304 , H01L29/66272 , H01L29/732
摘要： Provided is a method for manufacturing a semiconductor device that improves the reliability of the semiconductor device. An opening is formed in an insulating film formed over a semiconductor substrate. At that time, a mask layer for formation of the opening is formed over the insulating film. The insulating film is dry etched and then wet etched. The dry etching step is finished before the semiconductor substrate is exposed at the bottom of the opening, and the wet etching step is finished after the semiconductor substrate is exposed at the bottom of the opening.

3. 发明授权

US09755043B2 Trench gate power semiconductor field effect transistor 有权
公开(公告)号：US09755043B2
公开(公告)日：2017-09-05
申请号：US14771089
申请日：2014-12-04
申请人： Shuk-Wa Fung
发明人： Xianda Zhou , Shuk-Wa Fung , Johnny Kin On Sin
IPC分类号： H01L29/739 , H01L29/78 , H01L29/66 , H01L29/08 , H01L21/265 , H01L21/285 , H01L21/3065 , H01L21/324 , H01L29/06 , H01L29/10 , H01L29/417
CPC分类号： H01L29/66348 , H01L21/265 , H01L21/28556 , H01L21/3065 , H01L21/324 , H01L29/0649 , H01L29/0804 , H01L29/0821 , H01L29/0856 , H01L29/1095 , H01L29/41766 , H01L29/66295 , H01L29/66333 , H01L29/6634 , H01L29/66727 , H01L29/66734 , H01L29/7397 , H01L29/78 , H01L29/7813
摘要： Provided in the present invention is a trench gate power MOSFET (TMOS/UMOS) structure with a heavily doped polysilicon source region. The polysilicon source region is formed by deposition, and a trench-shaped contact hole is used at the source region, in order to attain low contact resistance and small cell pitch. The present invention may also be implemented in an IGBT.

4. 发明授权

US09679999B2 Bidirectional bipolar transistors with two-surface cellular geometries 有权
公开(公告)号：US09679999B2
公开(公告)日：2017-06-13
申请号：US15090582
申请日：2016-04-04
申请人： Ideal Power Inc.
发明人： Richard A. Blanchard
IPC分类号： H01L27/082 , H01L29/66 , H01L29/747 , H01L29/40 , H01L29/06 , H01L29/16
CPC分类号： H01L29/747 , H01L27/082 , H01L27/0823 , H01L29/0619 , H01L29/0692 , H01L29/0813 , H01L29/0821 , H01L29/1004 , H01L29/16 , H01L29/407 , H01L29/66234 , H01L29/66295 , H01L29/66303 , H01L29/73 , H01L29/732
摘要： A two-surface bidirectional power bipolar transistor is constructed with a two-surface cellular layout. Each emitter/collector region (e.g. doped n-type) is a local center of the repeated pattern, and is surrounded by a trench with an insulated field plate, which is tied to the potential of the emitter/collector region. The outer (other) side of this field plate trench is preferably surrounded by a base connection region (e.g. p-type), which provides an ohmic connection to the substrate. The substrate itself serves as the transistor's base.

5. 发明授权

US08860126B2 Semiconductor device with a low ohmic current path 有权
标题翻译：具有低欧姆电流通路的半导体器件
公开(公告)号：US08860126B2
公开(公告)日：2014-10-14
申请号：US13776799
申请日：2013-02-26
申请人： Infineon Technologies Austria AG
发明人： Franz Hirler , Andreas Meiser
IPC分类号： H01L21/66
CPC分类号： H01L29/7827 , H01L21/76898 , H01L21/823487 , H01L29/0649 , H01L29/0653 , H01L29/0878 , H01L29/42304 , H01L29/42372 , H01L29/66295 , H01L29/66348 , H01L29/66734 , H01L29/732 , H01L29/7397 , H01L29/781 , H01L29/7811 , H01L29/7813 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a semiconductor substrate having a main horizontal surface, a back surface arranged opposite the main horizontal surface, a vertical transistor structure including a doped region and a control electrode arranged next to the main horizontal surface, an insulating region arranged at or close to the back surface, a deep vertical trench extending from the main horizontal surface through the semiconductor substrate and to the insulating region, an insulating layer arranged on a side wall of the deep vertical trench, and a low ohmic current path extending at least partially along the insulating layer and between the main horizontal surface and the back surface. A first metallization is in ohmic contact with the doped region and arranged on the main horizontal surface. A control metallization is arranged on the back surface and in ohmic contact with the control electrode via the low ohmic current path.
摘要翻译：半导体器件包括具有主水平表面的半导体衬底，与主水平表面相对布置的背表面，包括布置在主水平表面旁边的掺杂区域和控制电极的垂直晶体管结构，布置在或接近的绝缘区域到后表面，从主水平表面穿过半导体衬底延伸到绝缘区域的深垂直沟槽，布置在深垂直沟槽的侧壁上的绝缘层，以及至少部分延伸的低欧姆电流路径绝缘层和主水平表面和后表面之间。第一金属化与掺杂区域欧姆接触并且布置在主水平表面上。控制金属化被布置在背表面上并经由低欧姆电流路径与控制电极欧姆接触。

6. 发明申请

US20020130362A1 High voltage semiconductor device having high breakdown voltage and method of fabricating the same 审中-公开
标题翻译：具有高击穿电压的高电压半导体器件及其制造方法
公开(公告)号：US20020130362A1
公开(公告)日：2002-09-19
申请号：US10024475
申请日：2001-12-21
发明人： Chan-ho Park
IPC分类号： H01L031/119 , H01L031/113 , H01L031/062 , H01L029/94 , H01L029/76
CPC分类号： H01L29/66295 , H01L29/0661 , H01L29/732
摘要： A high voltage semiconductor device, including: a high concentration collector area of a first conductive type; a low concentration collector area of a first conductive type formed on the high concentration collector area; a base area of a second conductive type formed on the low concentration collector area and having a trench perforating the low concentration collector area in a vertical direction at the edge of the trench; a high concentration emitter area of a first conductive type formed on a predetermined upper surface of the base area; and an emitter electrode, a base electrode, and a collector electrode isolated from one another and connected to the emitter area, the base area, and the collector area, respectively. High breakdown voltage can be obtained with a narrow junction termination area due to the trench.
摘要翻译：一种高电压半导体器件，包括：第一导电类型的高浓度集电极区域; 形成在高浓度集电区上的第一导电类型的低浓度集电区; 第二导电类型的基极区域，形成在所述低浓度集电区域上，并且在所述沟槽的边缘处具有在垂直方向上穿透所述低浓度集电极区域的沟槽; 形成在所述基部区域的预定上表面上的第一导电类型的高浓度发射极区域; 以及彼此分离并分别连接到发射极区域，基极区域和集电极区域的发射极电极，基极电极和集电极电极。由于沟槽，可以获得具有窄结终止面积的高击穿电压。

7. 发明授权

US06355971B2 Semiconductor switch devices having a region with three distinct zones and their manufacture 失效
标题翻译：具有具有三个不同区域的区域及其制造的半导体开关器件
公开(公告)号：US06355971B2
公开(公告)日：2002-03-12
申请号：US09257631
申请日：1999-02-25
申请人： Holger Schligtenhorst , Godefridus A. M. Hurkx , Andrew M. Warwick
发明人： Holger Schligtenhorst , Godefridus A. M. Hurkx , Andrew M. Warwick
IPC分类号： H01L2970
CPC分类号： H01L29/66136 , H01L29/66295 , H01L29/7325 , H01L29/868
摘要： In a semiconductor switch device such as an NPN transistor (T) or a power switching diode (D), a multiple-zone first region (1) of one conductivity type forms a switchable p-n junction (12) with a second region (2) of opposite conductivity type. In accordance with the invention, this first region (1) includes three distinct zones, namely a low-doped zone (23), a high-doped zone (25), and an intermediate additional zone (24). The low-doped zone (23) is provided by a semiconductor body portion (11) having a substantially uniform p-type doping concentration (P−) and forms the p-n junction (12) with the second region (2). The distinct additional zone (24) is present between the low-doped zone (23) and the high-doped zone (25). The high-doped zone (25) which may form a contact zone has a doping concentration (P++) which is higher than that of the low-doped zone (23) and which decreases towards the low-doped zone (23). The distinct additional zone (24) has an additional doping concentration (P+) which is lower than the doping concentration (P++) of the high-doped zone (25) and which decreases towards the low-doped zone (23). This triple-zone formation for the first region (1) permits an improvement in switching behaviour, e.g. in terms of fall-time and energy dissipation during turn-off of the device (T, D). A very low doping (P−) can be used for low-doped zone (23) so that, in the off-state of the device (T, D), this zone (23) and also the additional zone (24) can be fully depleted. The additional zone (24) having its additional doping concentration provides a path for extracting residual charge carriers from the low-doped zone (23) when the device (T, D) is being switched off.
摘要翻译：在诸如NPN晶体管（T）或功率开关二极管（D）的半导体开关器件中，一个导电类型的多区域第一区域（1）形成具有第二区域（2）的可切换pn结（12）的相反导电类型。根据本发明，该第一区域（1）包括三个不同的区域，即低掺杂区域（23），高掺杂区域（25）和中间附加区域（24）。低掺杂区域（23）由具有基本均匀的p型掺杂浓度（P-）的半导体本体部分（11）提供，并与第二区域（2）形成p-n结（12）。不同的附加区（24）存在于低掺杂区（23）和高掺杂区（25）之间。可形成接触区的高掺杂区（25）具有高于低掺杂区（23）的掺杂浓度（P ++），并且朝向低掺杂区（23）减小。不同的附加区域（24）具有低于高掺杂区域（25）的掺杂浓度（P ++）的附加掺杂浓度（P +），并且朝向低掺杂区域（23）减小。用于第一区域（1）的这种三区形成允许改变开关行为，例如，在设备（T，D）关闭期间的下降时间和能量耗散方面。对于低掺杂区域（23），可以使用非常低的掺杂（P-），使得在器件（T，D）的截止状态下，该区域（23）以及附加区域（24）可以充分耗尽具有其附加掺杂浓度的附加区域（24）提供了当器件（T，D）被切断时从低掺杂区域（23）提取残余电荷载流子的路径。

8. 发明授权

US6040219A Method of fabricating power semiconductor device using semi-insulating polycrystalline silicon (SIPOS) film 有权
标题翻译：使用半绝缘多晶硅（SIPOS）薄膜制造功率半导体器件的方法
公开(公告)号：US6040219A
公开(公告)日：2000-03-21
申请号：US150171
申请日：1998-09-09
申请人： Chan-ho Park , Jae-hong Park
发明人： Chan-ho Park , Jae-hong Park
IPC分类号： H01L21/28 , H01L21/306 , H01L21/329 , H01L21/331 , H01L29/06 , H01L29/40 , H01L29/73 , H01L29/732 , H01L21/336
CPC分类号： H01L29/405 , H01L29/66136 , H01L29/66295
摘要： A method for manufacturing a power semiconductor device including a semi-insulating polycrystalline silicon (SIPOS) film is provided. According to this method, first, a conductive collector region is formed in a semiconductor substrate. Then, a first insulating film, which exposes a portion of the semiconductor substrate in which a base region is to be formed, is formed on said semiconductor substrate in which the collector region is formed. A conductive base region is formed in the collector region. A second insulating film is formed over the entire surface of the semiconductor substrate. After exposing a portion of the semiconductor substrate in which an emitter region and a channel stop region are to be formed, impurities for the emitter region are implanted into the base region. Simultaneously, a third insulating film is formed over the entire surface of the semiconductor substrate, while a conductive emitter region is formed by diffusing the impurities. At least one of the first to third insulating films is left only in a field region between the base region and the channel stop region. Parts of the base region, the emitter region, and the channel stop region are exposed after forming a semi-insulating polycrystalline silicon (SIPOS) film on the entire surface of the resultant structure. A base electrode, an emitter electrode, and an equipotential metal ring are then formed, respectively contacting the base region, the emitter region, and the channel stop region.
摘要翻译：提供一种用于制造包括半绝缘多晶硅（SIPOS）膜的功率半导体器件的方法。根据该方法，首先，在半导体衬底中形成导电性集电极区域。然后，在形成集电极区域的所述半导体基板上形成露出要形成有基极区域的半导体衬底的一部分的第一绝缘膜。在集电区域形成导电基区。在半导体基板的整个表面上形成第二绝缘膜。在将要形成发射极区域和沟道停止区域的半导体衬底的一部分暴露之后，将发射极区域的杂质注入基极区域。同时，在半导体衬底的整个表面上形成第三绝缘膜，同时通过扩散杂质形成导电发射极区域。第一至第三绝缘膜中的至少一个绝缘膜仅留在基极区域和沟道停止区域之间的场区域中。在所得结构的整个表面上形成半绝缘多晶硅（SIPOS）膜之后，露出基极区域，发射极区域和沟道停止区域的部分。然后形成分别接触基极区域，发射极区域和沟道停止区域的基极，发射极和等电位金属环。

9. 发明授权

US6028329A Bipolar junction transistor device and a method of fabricating the same 失效
标题翻译：双极结晶体管器件及其制造方法
公开(公告)号：US6028329A
公开(公告)日：2000-02-22
申请号：US925357
申请日：1997-09-08
申请人： Chungpin Liao
发明人： Chungpin Liao
IPC分类号： H01L21/261 , H01L21/331 , H01L21/761 , H01L29/737 , H01L31/0328
CPC分类号： H01L29/66295 , H01L21/261 , H01L21/761 , H01L29/7375
摘要： A novel bipolar junction transistor device and a method of fabricating the same are proposed. In accordance with the present invention, a p-type silicon substrate is vertically all-through transmuted into an n-type region locally by using neutron transmutation doping, such that the epitaxy layer and buried layer used in conventional BJT devices can be replaced and isolation between devices can be easily achieved. Consequently, the present invention is characterized by a higher voltage rating than that which can be achieved isolation; and the present invention is also characterized as having compatibility with the MOS.
摘要翻译：提出了一种新颖的双极结型晶体管器件及其制造方法。根据本发明，通过使用中子转换掺杂，p型硅衬底被垂直地全部变换为n型区域，使得可以替代和隔离常规BJT器件中使用的外延层和掩埋层设备之间可以轻松实现。因此，本发明的特征在于比可实现隔离的额定电压更高的电压额定值; 本发明的特征还在于与MOS的兼容性。

10. 发明授权

US5688714A Method of fabricating a semiconductor device having a top layer and base layer joined by wafer bonding 失效
标题翻译：制造具有通过晶片接合连接的顶层和底层的半导体器件的方法
公开(公告)号：US5688714A
公开(公告)日：1997-11-18
申请号：US612201
申请日：1996-03-07
申请人： Franciscus P. Widdershoven , Jan Haisma , Arie J. R. De Kock , Aart A. Van Gorkum
发明人： Franciscus P. Widdershoven , Jan Haisma , Arie J. R. De Kock , Aart A. Van Gorkum
IPC分类号： H01L21/02 , H01L21/18 , H01L21/225 , H01L21/329 , H01L21/331 , H01L21/38
CPC分类号： H01L29/6609 , H01L21/187 , H01L29/66295 , Y10S148/012
摘要： A method is set forth of manufacturing a silicon body (5) having an n-type top layer (1') and an adjoining, more highly doped n-type base layer (2'), by which a first, n-type silicon slice (1) and a second, more highly doped n-type silicon slice (2) are put one on the other and then bonded together by heating. To obtain a low contact resistance between top layer (1') and base layer (2'), a boundary layer having a higher doping than the to player (1') is provided in the top layer (1') adjoining the base layer (2'). According to the invention, the boundary layer is formed by diffusion of an n-type dopant (11, 14) into the first slice (1) from the second slice (2) during heating. The concentration of the n-type dopant (11, 14) is taken to be so high in this case that boron (12) present as an impurity is overdoped, so that undesired pn transitions cannot occur. Measures according to the invention present the advantage that pollution of the first slice (1) is counteracted, while in addition the boundary layer is given a steep concentration profile. Semiconductor devices manufactured in body (5) will as a result have a comparatively high switching speed and a comparatively low forward bias.
摘要翻译：提出了制造具有n型顶层（1'）和邻接的更高掺杂的n型基极层（2'）的硅体（5）的方法，通过该方法，第一n型硅将切片（1）和第二更高掺杂的n型硅片（2）放在一起，然后通过加热结合在一起。为了获得顶层（1'）和基底层（2'）之间的低接触电阻，在与基底层（1'）相邻的顶层（1'）中提供具有比玩家（1'）更高掺杂的边界层（2'）。根据本发明，通过在加热期间从第二切片（2）将n型掺杂剂（11,14）扩散到第一切片（1）中形成边界层。在这种情况下，n型掺杂剂（11,14）的浓度被认为是非常高的，因为作为杂质存在的硼（12）被过度掺杂，从而不会发生不期望的pn转变。根据本发明的措施具有抵消第一切片（1）的污染的优点，另外边界层被赋予陡峭的浓度分布。结果，在本体（5）中制造的半导体器件具有较高的开关速度和较低的正向偏压。

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