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1. 发明授权

US5387528A Method of manufacturing a semiconductor device comprising an insulated gate field effect device 失效
标题翻译：制造包括绝缘栅场效应器件的半导体器件的方法
公开(公告)号：US5387528A
公开(公告)日：1995-02-07
申请号：US95972
申请日：1993-07-22
申请人： Keith M. Hutchings , Andrew L. Goodyear , Andrew M. Warwick
发明人： Keith M. Hutchings , Andrew L. Goodyear , Andrew M. Warwick
IPC分类号： H01L21/336 , H01L29/06 , H01L29/10 , H01L29/78 , H01L21/265
CPC分类号： H01L29/1095 , H01L29/7813 , H01L29/0696 , Y10S148/126
摘要： A semiconductor body (3) has a first region (4) of one conductivity type adjacent one major surface (5). A first masking layer (6) comprising at least one first mask window (6a) spaced from a second mask window (6b) is defined on the surface (5). Opposite conductivity type impurities are then introduced through the first masking layer (6) and a second masking layer (8) which is selectively removable with respect to the first masking layer (6) is subsequently provided on the first masking layer and patterned to leave a mask area (8a) covering the first mask window (6a). The semiconductor body (3) is then etched through the second mask window (6b) to define a recess (9) extending into the first region (4) while leaving the introduced impurities beneath the masked first mask window (6a) to form a relatively highly doped second region (7). The first and second masking layers (6 and 8) are removed and an insulated gate structure (10) is provided by defining a gate insulating layer (10a) on the recess walls (9a) and providing a gate conductive region (10b) on the insulating layer (10a). A relatively lowly doped third region (11) of the opposite conductivity type is provided to extend between the relatively highly doped second region (7) and the recess (9) to provide a conduction channel area (11a) adjacent the insulated gate structure (10). A fourth region (12) is provided to form a potential barrier (12a) with the relatively lowly doped third region (11) so that the conduction channel area (11a) provides a conductive path between the fourth and first regions (12 and 4).
摘要翻译：半导体本体（3）具有邻近一个主表面（5）的一种导电类型的第一区域（4）。在表面（5）上限定包括与第二掩模窗口（6b）间隔开的至少一个第一掩模窗口（6a）的第一掩模层（6）。然后通过第一掩模层（6）引入相对导电类型的杂质，随后在第一掩模层（6）上选择性地除去第二掩模层（8），并且图案化以留下掩蔽区域（8a）覆盖第一掩模窗口（6a）。然后，通过第二掩模窗口（6b）蚀刻半导体本体（3），以限定延伸到第一区域（4）中的凹陷（9），同时在被掩蔽的第一掩模窗口（6a）之下留下引入的杂质以形成相对高度掺杂的第二区域（7）。去除第一和第二掩蔽层（6和8），并且通过在凹壁（9a）上限定栅极绝缘层（10a）并在其上提供栅极导电区域（10b）来提供绝缘栅极结构（10）绝缘层（10a）。提供相对导电类型的相对低掺杂的第三区域（11）以在相对高度掺杂的第二区域（7）和凹部（9）之间延伸，以提供邻近绝缘栅极结构（10）的导电沟道区域（11a））。第四区域（12）被提供以形成具有相对低掺杂的第三区域（11）的势垒（12a），使得导通通道区域（11a）在第四区域和第一区域（12和4）之间提供导电路径，。

2. 发明授权

US5352915A Semiconductor component having two integrated insulated gate field effect devices 失效
标题翻译：具有两个集成绝缘栅场效应器件的半导体元件
公开(公告)号：US5352915A
公开(公告)日：1994-10-04
申请号：US103943
申请日：1993-08-09
申请人： Keith M. Hutchings , Andrew L. Goodyear , Paul A. Gough
发明人： Keith M. Hutchings , Andrew L. Goodyear , Paul A. Gough
IPC分类号： H01L27/06 , H01L27/02 , H01L27/04 , H01L29/78 , H01L29/10
CPC分类号： H01L29/7813 , H01L27/0251 , H01L29/7802
摘要： A semiconductor component (1a) has first and second insulated gate field effect devices (T1 and T2) formed within the same seminconductor body (2). The devices (T1 and T2) have a common first main electrode (D) and an arrangement (20) provides a resistive connection (20b) between a second main electrode (S2)of the second device (T2) and the insulated gate (G1) of the first device (T1). The second device (T2) is formed so as to be more susceptible than the first device (T1) to parasitic bipolar transistor action for causing, when the first and second devices (T1 and T2) are turned off and a voltage exceeding a critical voltage (V.sub.c) is applied to the common first main electrode (D), the parasitic bipolar transistor (B) within the second device (T2) to turn on producing a current for causing, by virtue of the resistive connection (20b) between the second main electrode (S2) of the second device (T2) and the insulated gate (G1) of the first device (T1), the voltage at the insulated gage (G1) of the first device (T1) to alter to cause the device (T1) to turn on. This allows the energy of the overvoltage to be dissipated by conduction of the first insulated gate field effect device to avoid any potentially damaging effects, such as irreversible bipolar breakdown or performance degradation due to hot carrier injection into the gate oxide.
摘要翻译：半导体部件（1a）具有形成在同一半导体体（2）内的第一和第二绝缘栅场效应器件（T1和T2）。器件（T1和T2）具有共同的第一主电极（D），并且布置（20）在第二器件（T2）的第二主电极（S2）和绝缘栅极（G1）之间提供电阻连接（20b））的第一设备（T1）。第二器件（T2）形成为比第一器件（T1）更易受到寄生双极晶体管的作用，当第一和第二器件（T1和T2）截止并且电压超过临界电压时（Vc）施加到公共第一主电极（D），第二器件（T2）内的寄生双极晶体管（B），以产生用于使第二器件（T2）内的电阻连接（20b）第二装置（T2）的主电极（S2）和第一装置（T1）的绝缘栅极（G1），第一装置（T1）的绝缘规格（G1）的电压改变以使装置 T1）打开。这允许通过第一绝缘栅场效应器件的导通来消除过电压的能量，以避免任何潜在的破坏性影响，例如由于热载流子注入到栅极氧化物中的不可逆双极击穿或性能劣化。

3. 发明授权

US5527720A Method of forming a semiconductor device having a vertical insulated gate FET and a breakdown region remote from the gate 失效
标题翻译：形成具有垂直绝缘栅极FET和远离栅极的击穿区域的半导体器件的方法
公开(公告)号：US5527720A
公开(公告)日：1996-06-18
申请号：US471298
申请日：1995-06-06
申请人： Andrew L. Goodyear , Keith M. Hutchings
发明人： Andrew L. Goodyear , Keith M. Hutchings
IPC分类号： H01L21/336 , H01L27/02 , H01L27/04 , H01L29/06 , H01L29/08 , H01L29/739 , H01L29/78 , H01L21/8232
CPC分类号： H01L29/7808 , H01L27/0255 , H01L29/0626 , H01L29/7811 , H01L29/7813 , H01L29/0696 , H01L29/0847 , H01L29/4238
摘要： A semiconductor device (1) includes a vertical insulated gate field effect device (2) and has a semiconductor body (3) with a first semiconductor region (4) of one conductivity type adjacent one major surface (5). A second semiconductor region (6) of the opposite conductivity type is formed within the first region (4) adjacent the surface (5) and a third region (7) forms with the second region (6) a rectifying junction (8) meeting the one major surface (5). A recess (9) extends into the first region (4) from the one major surface (5) so that the second and third regions (6 and 7) abut the recess (9), and an insulated gate (10) is formed within the recess (9) for controlling conduction between the first and third regions (4 and 7) along a conduction channel area (61) of the second region (6). A fourth region (11) of the one conductivity type forms with a portion (6b) of the second region (6) of the opposite conductivity type remote from the recess (9) a further rectifying junction (12) which is reverse-biassed in at least one mode of operation of the device and has a predetermined breakdown voltage for causing the device to breakdown in the vicinity of the further rectifying junction (12) away from the recess (9) when a critical voltage is exceeded.
摘要翻译：半导体器件（1）包括垂直绝缘栅场效应器件（2），并且具有半导体本体（3），其具有与一个主表面（5）相邻的一个导电类型的第一半导体区域（4）。在相邻表面（5）的第一区域（4）内形成相反导电类型的第二半导体区域（6），并且与第二区域（6）形成第三区域（7），整流结（8）与一个主要表面（5）。凹部（9）从一个主表面（5）延伸到第一区域（4）中，使得第二和第三区域（6和7）邻接凹部（9），并且在内部形成绝缘栅极（10）所述凹部（9）用于沿着所述第二区域（6）的导电通道区域（61）控制所述第一和第三区域（4和7）之间的导通。一个导电类型的第四区域（11）与远离凹部（9）的相反导电类型的第二区域（6）的部分（6b）形成另一整流结（12），该整流结所述装置的至少一种操作模式具有预定的击穿电压，以在超过临界电压时使所述装置在所述另外的整流结（12）附近与所述凹部（9）分开。

4. 发明授权

US5656843A Semiconductor device having a vertical insulated gate field effect device and a breakdown region remote from the gate 失效
标题翻译：具有垂直绝缘栅场效应器件和远离栅极的击穿区域的半导体器件
公开(公告)号：US5656843A
公开(公告)日：1997-08-12
申请号：US668426
申请日：1996-06-13
申请人： Andrew L. Goodyear , Keith M. Hutchings
发明人： Andrew L. Goodyear , Keith M. Hutchings
IPC分类号： H01L21/336 , H01L27/02 , H01L27/04 , H01L29/06 , H01L29/08 , H01L29/739 , H01L29/78 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H01L29/7808 , H01L27/0255 , H01L29/0626 , H01L29/7811 , H01L29/7813 , H01L29/0696 , H01L29/0847 , H01L29/4238
摘要： A semiconductor device (1) includes a vertical insulated gate field effect device (2) and has a semiconductor body (3) with a first semiconductor region (4) of one conductivity type adjacent one major surface (5). A second semiconductor region (6) of the opposite conductivity type is former within the first region (4) adjacent the surface (5) and a third region (7) forms with the second region (6) a rectifying junction (8) meeting the one major surface (5). A recess (9) extends into the first region (4) from the one major surface (5) so that the second and third regions (6 and 7) abut the recess (9), and an insulated gate (10) is formed within the recess (9) for controlling conduction between the first and third regions (4 and 7) along a conduction channel area (61) of the second region (6). A fourth region (11) of the one conductivity type forms with a portion (6b) of the second region (6) of the opposite conductivity type remote from the recess (9) a further rectifying junction (12) which is reverse-biassed in at least one mode of operation of the device and has a predetermined breakdown voltage for causing the device to breakdown in the vicinity of the further rectifying junction (12) away from the recess (9) when a critical voltage is exceeded.
摘要翻译：半导体器件（1）包括垂直绝缘栅场效应器件（2），并且具有半导体本体（3），其具有与一个主表面（5）相邻的一个导电类型的第一半导体区域（4）。在相邻表面（5）的第一区域（4）内具有相反导电类型的第二半导体区域（6），并且第三区域（7）与第二区域（6）形成一个整流结（8）一个主要表面（5）。凹部（9）从一个主表面（5）延伸到第一区域（4）中，使得第二和第三区域（6和7）邻接凹部（9），并且在内部形成绝缘栅极（10）所述凹部（9）用于沿着所述第二区域（6）的导电通道区域（61）控制所述第一和第三区域（4和7）之间的导通。一个导电类型的第四区域（11）与远离凹部（9）的相反导电类型的第二区域（6）的部分（6b）形成另一整流结（12），该整流结所述装置的至少一种操作模式具有预定的击穿电压，以在超过临界电压时使所述装置在所述另外的整流结（12）附近与所述凹部（9）分开。

5. 发明授权

US5378655A Method of manufacturing a semiconductor device comprising an insulated gate field effect device 失效
标题翻译：制造包括绝缘栅场效应器件的半导体器件的方法
公开(公告)号：US5378655A
公开(公告)日：1995-01-03
申请号：US221293
申请日：1994-03-31
申请人： Keith M. Hutchings , Kenneth R. Whight
发明人： Keith M. Hutchings , Kenneth R. Whight
IPC分类号： H01L21/225 , H01L21/331 , H01L21/336 , H01L29/06 , H01L29/739 , H01L29/78 , H01L21/44
CPC分类号： H01L29/7813 , H01L29/66348 , H01L29/66719 , H01L29/66727 , H01L29/7397 , H01L21/2255 , H01L21/2257 , H01L29/0696 , Y10S148/126
摘要： A mask (4) defining at least one window (4a) is provided on one major surface (1a) of a semiconductor body (1). The semiconductor body (1) is etched to define a groove (5) into a first region (2) of one conductivity type through a second region (3) of the opposite conductivity type. A relatively thin layer of gate insulator (6) is provided on the surface (5a) of the groove (5). A gate conductive region (7) of an oxidizable conductive material is provided within the groove (5) to define with the gate insulator layer an insulated gate structure (8) bounded by a conduction channel-defining area (30) of the second region (3). A step (15) in the surface structure is then defined by causing the insulated gate structure (8) to extend beyond the surrounding surface by oxidizing the exposed (7a) gate conductive material to define an insulating capping region (9) on the gate conductive region (3). A layer (10) is formed over the surface structure and etched anisotropically to leave portions (10a) of the layer on the side wall (8'a) of the step (15) defined by the insulated gate structure (8) and to define beneath the portions (10a) third regions (11) of the one conductivity type within the second region (3). An electrically conductive layer (12) is deposited to contact both the second and the third regions (3 and 11).
摘要翻译：限定至少一个窗口（4a）的掩模（4）设置在半导体主体（1）的一个主表面（1a）上。蚀刻半导体本体（1），以通过相反导电类型的第二区域（3）将沟槽（5）限定成一种导电类型的第一区域（2）。在槽（5）的表面（5a）上设置相对薄的栅极绝缘体（6）。在所述凹槽（5）内设置可氧化导电材料的栅极导电区域（7），以与所述栅极绝缘体层一起限定由所述第二区域的导电通道限定区域（30）限定的绝缘栅极结构（8） 3）。然后通过使绝缘栅极结构（8）延伸超过周围表面，通过氧化暴露的（7a）栅极导电材料来限定栅极导电上的绝缘覆盖区域（9）来限定表面结构中的台阶（15）区域（3）。在表面结构上方形成一层（10）并各向异性地蚀刻，以留下由绝缘栅极结构（8）限定的台阶（15）的侧壁（8'）上的层的部分（10a）并限定在第二区域（3）内的一个导电类型的部分（10a）第三区域（11）的下方。沉积导电层（12）以接触第二和第三区域（3和11）。

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