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1. 发明申请

US20050128680A1 Method of manufacturing multilayered ceramic capacitor by spin coating and multilayered ceramic capacitor 失效
标题翻译：通过旋涂和多层陶瓷电容器制造多层陶瓷电容器的方法
公开(公告)号：US20050128680A1
公开(公告)日：2005-06-16
申请号：US11011092
申请日：2004-12-15
申请人： Hyo Shin , Seung Ra , Yong Kim , Hyoung Kim , Ho Choo , Jung Lee
发明人： Hyo Shin , Seung Ra , Yong Kim , Hyoung Kim , Ho Choo , Jung Lee
IPC分类号： H01G4/12 , C04B35/468 , H01G4/30 , H01G9/00 , H01G13/00 , H01G13/04
CPC分类号： H01G4/30 , H01G4/1227 , Y10T29/417 , Y10T29/43 , Y10T29/435
摘要： Disclosed herein is a method of manufacturing a multilayered ceramic capacitor by a spin coating process, and a multilayered ceramic capacitor obtained by the above method. The method of the current invention provides a plurality of dielectric layers formed by spin coating, in which the process of coating the dielectric layer and the process of printing the inner electrode can be provided as a single process. Therefore, the thickness of the dielectric layer is easily controlled while the dielectric layer is formed to be thin. Further, since the dielectric layers and the inner electrodes are formed successively, the processes of separating and layering the dielectric layers, and the process of compressing the ceramic multilayered body can be omitted. Thereby, the ceramic multilayered body need not be compressed, and thus, a pillowing phenomenon does not occur in the multilayered ceramic capacitor.
摘要翻译：本文公开了通过旋涂工艺制造多层陶瓷电容器的方法和通过上述方法获得的多层陶瓷电容器。本发明的方法提供了通过旋涂形成的多个电介质层，其中涂覆介电层的过程和印刷内电极的过程可以作为单一工艺提供。因此，在电介质层形成得较薄的同时容易控制电介质层的厚度。此外，由于电介质层和内部电极依次形成，所以可以省略介电层的分离和分层工艺以及压缩陶瓷多层体的工艺。因此，陶瓷多层体不需要被压缩，因此在多层陶瓷电容器中不会发生卷绕现象。

2. 发明申请

US20050132548A1 Method for manufacturing multilayer ceramic capacitor 失效
标题翻译：多层陶瓷电容器制造方法
公开(公告)号：US20050132548A1
公开(公告)日：2005-06-23
申请号：US11002183
申请日：2004-12-03
申请人： Ho Choo , Seung Ra , Yong Kim , Jung Lee , Hyo Shin , Hyoung Kim
发明人： Ho Choo , Seung Ra , Yong Kim , Jung Lee , Hyo Shin , Hyoung Kim
IPC分类号： H01G4/005 , H01G4/12 , H01G4/232 , H01G4/30 , H01G9/00 , H01G4/06
CPC分类号： H01G4/005 , H01G4/12 , H01G4/30 , Y10T29/417
摘要： A method for manufacturing a multilayer ceramic capacitor, in which internal electrodes printed on each of a plurality of dielectric sheets have reduced thicknesses using an absorption member, thereby allowing the multilayer ceramic capacitor to have a high capacity and be minimized. The method includes printing the internal electrodes on each of the dielectric sheets, and stacking the dielectric sheets, wherein the internal electrodes formed on each of the dielectric sheets have a reduced thickness by causing an absorptive member to contact the surface of each of the dielectric sheets provided with the internal electrodes and then separating the absorptive member from the surface so that portions of the internal electrodes having a designated thickness are eliminated, and the dielectric sheets provided with the internal electrodes having the reduced thickness are stacked to form a chip element.
摘要翻译：一种制造多层陶瓷电容器的方法，其中印刷在多个电介质片材的每一个上的内部电极使用吸收构件具有减小的厚度，从而允许多层陶瓷电容器具有高容量并且被最小化。该方法包括在每个电介质片上印刷内部电极，并叠放电介质片，其中形成在每个电介质片上的内部电极通过使吸收构件接触每个电介质片的表面而具有减小的厚度设置有内部电极，然后将吸收构件从表面分离，使得部分具有指定厚度的内部电极被去除，并且设置有具有减小的厚度的内部电极的电介质层被堆叠以形成芯片元件。

3. 发明申请

US20060121258A1 Sol composition for dielectric ceramic, and dielectric ceramic and multilayered ceramic capacitor using the same 审中-公开
标题翻译：电介质陶瓷的溶胶组合物，以及使用其的介电陶瓷和多层陶瓷电容器
公开(公告)号：US20060121258A1
公开(公告)日：2006-06-08
申请号：US11052796
申请日：2005-02-09
申请人： Yong Kim , Hyo Shin , Hyoung Kim , Ho Choo , Jung Lee
发明人： Yong Kim , Hyo Shin , Hyoung Kim , Ho Choo , Jung Lee
IPC分类号： B32B18/00 , B32B15/04
CPC分类号： C04B35/624 , C04B35/468 , C04B35/62218 , C04B35/62615 , C04B35/6325 , C04B2235/449 , C04B2235/77 , C04B2235/79 , Y10T428/24926
摘要： Disclosed herein is a sol composition for ultrathin dielectric ceramic films, and dielectric ceramic and a multilayered ceramic capacitor manufactured using the same. The sol composition, composed of BaTiO3 as a main ingredient and an auxiliary ingredient, includes a polymeric sol having a metal precursor solution of BaTiO3 and an organic solvent, and an organic additive dissolved in the organic solvent to act as the auxiliary ingredient, in which the amount of the organic additive corresponds to the required amount of the auxiliary ingredient of the dielectric ceramic. Further, the ultrathin dielectric ceramic film, which is manufactured by a sol-gel process, includes the auxiliary ingredient, and hence, is advantageous in making low temperature sintering possible, and having a high dielectric constant, a high sintered density, and TCC characteristic meeting the X5R of EIA standard.
摘要翻译：本文公开了一种用于超薄介电陶瓷膜的溶胶组合物，以及使用其制造的介电陶瓷和多层陶瓷电容器。以BaTiO 3 3 +作为主要成分和辅助成分组成的溶胶组合物包括具有BaTiO 3 3金属前体溶液和有机溶剂的聚合物溶胶，和溶解在有机溶剂中的有机添加剂用作辅助成分，其中有机添加剂的量对应于所需量的电介质陶瓷的辅助成分。此外，通过溶胶 - 凝胶法制造的超薄介电陶瓷膜包括辅助成分，因此有利于低温烧结成为可能，并且具有高介电常数，高烧结密度和TCC特性符合EIA标准的X5R。

4. 发明申请

US20060139848A1 Multilayer chip capacitor and method for manufacturing the same 失效
标题翻译：多层片式电容器及其制造方法
公开(公告)号：US20060139848A1
公开(公告)日：2006-06-29
申请号：US11272893
申请日：2005-11-15
申请人： Hyoung Kim , Hyo Shin , Ho Choo
发明人： Hyoung Kim , Hyo Shin , Ho Choo
IPC分类号： H01G4/228
CPC分类号： H01G4/232 , H01G4/012 , Y10T29/413 , Y10T29/417 , Y10T29/435
摘要： A multilayer chip capacitor, and a method for manufacturing the same are Provided. The capacitor comprises a capacitor body having a plurality of dielectric layers stacked therein, a plurality of first and second internal electrodes formed on the dielectric layers, each of the internal electrodes including a main electrode portion and a lead portion, chip-protecting side members formed on both sides of the capacitor body to contact both sides of the first and second internal electrodes, and a pair of external electrodes formed on the outer surface of the capacitor body. The width of the main electrode portion is the same as that of the dielectric layers, and the width of the lead portion is smaller than that of the dielectric layers.
摘要翻译：提供了一种多层片状电容器及其制造方法。所述电容器包括电容体，所述电容体具有堆叠的多个电介质层，形成在所述电介质层上的多个第一和第二内部电极，每个所述内部电极包括主电极部分和引线部分，形成芯片保护侧部件在电容器本体的两侧接触第一和第二内部电极的两侧，以及形成在电容器本体的外表面上的一对外部电极。主电极部的宽度与电介质层的宽度相同，引线部的宽度小于电介质层的宽度。

5. 发明申请

US20070251066A1 Multilayer chip capacitor and method for manufacturing the same 失效
标题翻译：多层片式电容器及其制造方法
公开(公告)号：US20070251066A1
公开(公告)日：2007-11-01
申请号：US11822189
申请日：2007-07-03
申请人： Hyoung Kim , Hyo Shin , Ho Choo
发明人： Hyoung Kim , Hyo Shin , Ho Choo
IPC分类号： H01G9/00
CPC分类号： H01G4/232 , H01G4/012 , Y10T29/413 , Y10T29/417 , Y10T29/435
摘要： A multilayer chip capacitor, and a method for manufacturing the same are Provided. The capacitor comprises a capacitor body having a plurality of dielectric layers stacked therein, a plurality of first and second internal electrodes formed on the dielectric layers, each of the internal electrodes including a main electrode portion and a lead portion, chip-protecting side members formed on both sides of the capacitor body to contact both sides of the first and second internal electrodes, and a pair of external electrodes formed on the outer surface of the capacitor body. The width of the main electrode portion is the same as that of the dielectric layers, and the width of the lead portion is smaller than that of the dielectric layers.
摘要翻译：提供了一种多层片状电容器及其制造方法。所述电容器包括电容体，所述电容体具有堆叠的多个电介质层，形成在所述电介质层上的多个第一和第二内部电极，每个所述内部电极包括主电极部分和引线部分，形成芯片保护侧部件在电容器本体的两侧接触第一和第二内部电极的两侧，以及形成在电容器本体的外表面上的一对外部电极。主电极部的宽度与电介质层的宽度相同，引线部的宽度小于电介质层的宽度。

6. 发明申请

US20060270078A1 Method of fabricating light emitting diode package 有权
标题翻译：制造发光二极管封装的方法
公开(公告)号：US20060270078A1
公开(公告)日：2006-11-30
申请号：US11439189
申请日：2006-05-24
申请人： Yong Kim , Seog Choi , Hyoung Kim , Yong Kim
发明人： Yong Kim , Seog Choi , Hyoung Kim , Yong Kim
IPC分类号： H01L21/00
CPC分类号： H01L33/52 , H01L2224/48091 , H01L2224/48227 , Y10S438/974 , H01L2924/00014
摘要： The invention relates to an LED package and proposes a method of fabricating an LED package including steps of providing a package substrate having a mounting area of an LED and a metal pattern to be connected with the LED, and plasma-treating the package substrate to reform at least a predetermined surface area of the package substrate where a resin-molded part will be formed. The method also includes mounting the LED on the mounting area on the substrate package and electrically connecting the LED with the metal pattern, and forming the resin-molded part in the mounting area of the LED to seal the LED package.
摘要翻译：本发明涉及一种LED封装，并提出了一种制造LED封装的方法，包括以下步骤：提供具有LED的安装区域和与LED连接的金属图案的封装基板，以及等离子体处理封装基板以改造至少形成将形成树脂成型部件的封装基板的预定表面积。该方法还包括将LED安装在基板封装上的安装区域上，并将LED与金属图形电连接，并在LED的安装区域中形成树脂模制部件以密封LED封装。

7. 发明申请

US20070018190A1 LED package and fabricating method thereof 有权
标题翻译： LED封装及其制造方法
公开(公告)号：US20070018190A1
公开(公告)日：2007-01-25
申请号：US11489578
申请日：2006-07-20
申请人： Yong Kim , Young Oh , Hyoung Kim , Taek Lee , Seog Choi
发明人： Yong Kim , Young Oh , Hyoung Kim , Taek Lee , Seog Choi
IPC分类号： H01L33/00
CPC分类号： H01L33/642 , H01L33/486 , H01L33/641 , H01L2224/16225
摘要： The invention provides an LED package capable of effectively releasing heat emitted from an LED chip out of the package and a fabrication method thereof. For this purpose, at least one groove is formed on an underside surface of the substrate to package the LED chip and the groove is filled with carbon nanotube material. In the LED package, a substrate having at least one groove on the underside surface is prepared. A plurality of electrodes are formed on a top surface of the substrate. Also, at least the one LED chip is mounted over the substrate to have both terminals electrically connected to the upper electrodes. In addition, carbon nanotube filler is filled in the groove of the substrate.
摘要翻译：本发明提供一种LED封装，其能够有效地从LED封装中散发从LED芯片发出的热量及其制造方法。为此，在基板的下侧表面上形成至少一个凹槽以封装LED芯片，并且凹槽填充有碳纳米管材料。在LED封装中，准备在底面上具有至少一个沟槽的衬底。多个电极形成在基板的顶表面上。此外，至少将一个LED芯片安装在基板上，以使两个端子电连接到上电极。此外，碳纳米管填料填充在基板的槽中。

8. 发明申请

US20070038438A1 Context knowledge modeling method for sharing and reusing context knowledge in context-aware system 审中-公开
标题翻译：上下文知识建模方法，用于在上下文感知系统中共享和重用上下文知识
公开(公告)号：US20070038438A1
公开(公告)日：2007-02-15
申请号：US11438855
申请日：2006-05-23
申请人： Joon Cho , Hyun Kim , Hyoung Kim , Joo Lee , Chung Hong , Jin Jung
发明人： Joon Cho , Hyun Kim , Hyoung Kim , Joo Lee , Chung Hong , Jin Jung
IPC分类号： G06F17/27
CPC分类号： G06F16/367
摘要： A context knowledge modeling method is provided. The context knowledge modeling method includes the steps of: a) defining a context knowledge space as a two-dimensional space based on an abstract level and an application domain of knowledge; b) locating a share ontology as a highest level of the abstract level for defining a common ontology concept at a plurality of applications and services performed in various environment and domains; c) locating at least one of domain ontologies as a lower abstract level than the share ontology by taking over the ontology concept defined at the share ontology and defining a class and an attribute specialized at a corresponding domain and a developing application; and d) locating one or more instance bases expressing knowledge about real objects to have a lower abstract level than the domain ontologies.
摘要翻译：提供了上下文知识建模方法。上下文知识建模方法包括以下步骤：a）基于知识的抽象层次和应用领域，将上下文知识空间定义为二维空间; b）将共享本体定位为在各种环境和域中执行的多个应用和服务中定义共同本体概念的抽象级别的最高级别; c）通过接管共享本体定义的本体概念并定义专门在相应域和开发应用的类和属性，将至少一个域本体定位为比共享本体更低的抽象级别; 以及d）找到一个或多个表示关于真实对象的知识的实例基础具有比领域本体更低的抽象级别。

9. 发明申请

US20060141722A1 Method of sequentially forming silicide layer and contact barrier in semiconductor integrated circuit device 审中-公开
标题翻译：在半导体集成电路器件中依次形成硅化物层和接触屏障的方法
公开(公告)号：US20060141722A1
公开(公告)日：2006-06-29
申请号：US11319709
申请日：2005-12-29
申请人： Hyoung Kim
发明人： Hyoung Kim
IPC分类号： H01L21/336
CPC分类号： H01L29/6656 , H01L21/28518 , H01L21/76843 , H01L29/66515 , H01L29/7833
摘要： A method of sequentially forming a silicide layer and a contact barrier in a semiconductor device is provided. In the method, a pre-metal dielectric layer is deposited over an underlying structure that has a silicon substrate, a gate electrode on the substrate, and source/drain regions in the substrate. Contact holes are formed toward the gate electrode and the source/drain regions in the dielectric layer. Then, a metal layer for the silicide layer is selectively deposited on the bottom of the contact holes by using ion implantation, for example. Thereafter, the contact barrier is conformally deposited on entire exposed surface, and a heat-treatment process is performed to form the silicide layer from the metal layer.
摘要翻译：提供了一种在半导体器件中顺序地形成硅化物层和接触屏障的方法。在该方法中，将金属前介电层沉积在具有硅衬底，衬底上的栅极电极和衬底中的源极/漏极区域的下面的结构上。电介质层中的栅极电极和源极/漏极区域形成接触孔。然后，例如，通过使用离子注入，在接触孔的底部选择性地沉积硅化物层的金属层。此后，将接触屏障保形地沉积在整个暴露表面上，并进行热处理工艺以从金属层形成硅化物层。

10. 发明申请

US20050260528A1 Liquid composition for immersion lithography and lithography method using the same 审中-公开
标题翻译：用于浸没式光刻的液体组合物及使用其的光刻方法
公开(公告)号：US20050260528A1
公开(公告)日：2005-11-24
申请号：US10999528
申请日：2004-11-30
申请人： Keun Kong , Hyoung Kim , Hyeong Kim , Jae Jung , Sung Lee
发明人： Keun Kong , Hyoung Kim , Hyeong Kim , Jae Jung , Sung Lee
IPC分类号： G03F7/20 , C11D1/72 , G03F7/00 , H01L21/027
CPC分类号： G03F7/2041
摘要： Disclosed herein are a liquid composition for immersion lithography and a lithography method using the composition. The liquid composition includes at least one nonionic surfactant selected from the group comprising of a polyvinyl alcohol, a pentaerythritol-based compound, a polymer containing an alkylene oxide, and a compound represented by Formula I: wherein R is a linear or branched, substituted C1-C40 alkyl, and n is an integer ranging from 10 to 10,000. The surface tension of the liquid composition is reduced by the nonionic surfactant, thereby solving the problem that the liquid composition is not completely filled or is partially concentrated on a wafer having a fine topology and removing micro bubbles between the photoresist film and the liquid composition.
摘要翻译：本文公开了用于浸没式光刻的液体组合物和使用该组合物的光刻方法。液体组合物包含至少一种非离子表面活性剂，其选自聚乙烯醇，季戊四醇基化合物，含有烯化氧的聚合物和由式I表示的化合物：其中R是直链或支链的取代的C C 1 -C 40烷基，n是10至10,000的整数。通过非离子表面活性剂降低液体组合物的表面张力，从而解决液体组合物未完全填充或部分浓缩在具有细微拓扑结构的晶片上并且去除光致抗蚀剂膜和液体组合物之间的微小气泡的问题。

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