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    • 1. 发明申请
    • Method for manufacturing capacitor of semiconductor element
    • 制造半导体元件电容器的方法
    • US20060134856A1
    • 2006-06-22
    • US11089122
    • 2005-03-24
    • Ho ChoJun ChangEun LeeSu ChaeYoung Kim
    • Ho ChoJun ChangEun LeeSu ChaeYoung Kim
    • H01L21/8242
    • H01L21/02312H01L21/02178H01L21/02181H01L21/022H01L21/3144H01L28/60
    • A method for manufacturing a capacitor of a semiconductor element including: forming a bottom electrode of the capacitor on a semiconductor substrate; performing rapid thermal nitrification (RTN) on the upper surface of the bottom electrode; performing a thermal process on the obtained structure having the bottom electrode in a furnace under a nitride atmosphere to eliminate stress generated by the RTN; forming Al2O3 and HfO2 dielectric films on the nitrified bottom electrode; and forming a plate electrode of the capacitor on the Al2O3 and HfO2 dielectric films. The thermal process is performed after the RTN performed on the surface of the bottom electrode, so that stress, generated from the RTN, is alleviated, thereby allowing the capacitor to obtain a high capacitance and lowering leakage current.
    • 一种制造半导体元件的电容器的方法,包括:在半导体衬底上形成电容器的底部电极; 在底电极的上表面进行快速热硝化(RTN); 对所获得的在氮化物气氛下的炉中具有底部电极的结构进行热处理以消除由RTN产生的应力; 在硝化的底部电极上形成Al 2 O 3 N 3和HfO 2 N 2电介质膜; 以及在Al 2 O 3和HfO 2 N 2电介质膜上形成电容器的平板电极。 在底电极表面进行RTN之后进行热处理,从而可以减轻由RTN产生的应力,从而使电容器获得高电容,降低漏电流。
    • 2. 发明申请
    • Gate structure of semiconductor device and method for forming the same
    • 半导体器件的栅极结构及其形成方法
    • US20060151839A1
    • 2006-07-13
    • US11268846
    • 2005-11-08
    • Young KimJun ChangMin LeeYong Eun
    • Young KimJun ChangMin LeeYong Eun
    • H01L29/78H01L21/4763
    • H01L27/10876H01L21/2815H01L29/66636
    • Disclosed herein is a method for forming a gate structure of a semiconductor device. The method comprises forming a plurality of gates including a first gate dielectric film, a first gate conductive film, and a gate silicide film sequentially stacked on a silicon substrate having a field oxide film, forming a thermal oxide film on a side of the first gate conductive film, etching the silicon substrate exposed between the plurality of gates to a predetermined depth to form a plurality of trenches, forming a second gate oxide film on the interior wall of the trenches, and forming a second gate conductive film in a spacer shape on a predetermined region of the second gate oxide film, and on a side of the first gate conductive film, the gate silicide film, and the thermal oxide film.
    • 本文公开了一种用于形成半导体器件的栅极结构的方法。 该方法包括形成多个栅极,其包括依次层叠在具有场氧化膜的硅基板上的第一栅极电介质膜,第一栅极导电膜和栅极硅化物膜,在第一栅极的一侧形成热氧化膜 将暴露在所述多个栅极之间的硅衬底蚀刻到预定深度以形成多个沟槽,在所述沟槽的内壁上形成第二栅极氧化膜,并且形成间隔物形状的第二栅极导电膜 第二栅极氧化膜的预定区域,以及第一栅极导电膜,栅极硅化物膜和热氧化物膜的一侧。
    • 6. 发明申请
    • On-chip network interfacing apparatus and method
    • 片上网络接口设备及方法
    • US20060146811A1
    • 2006-07-06
    • US11300731
    • 2005-12-14
    • Jin HanYoung BaeHan ChoJun Chang
    • Jin HanYoung BaeHan ChoJun Chang
    • H04L12/50
    • H04L49/10H04L49/109H04L49/3009H04L49/3018H04L49/503
    • An on-chip network interfacing apparatus and method are provided. The apparatus includes a plurality of on-chip network ports; a switch receiving data from a first on-chip network port of the on-chip network ports and transmitting the received data to a second on-chip network port of the on-chip network ports; and an interface unit interfacing an advanced microcontroller bus architecture (AMBA) signal received from an Internet protocol module, which is designed according to an AMBA on-chip bus protocol, and outputting the interfacing result to the first on-chip network port; and interfacing the on-chip network signal received from the first on-chip network port, and outputting the interfacing result to the Internet protocol module. Accordingly, it is possible to establish communications at increased speeds by interfacing a signal according to the AMBA 2.0 on-chip bus protocol with a signal according to the on-chip network protocol.
    • 提供了片上网络接口设备和方法。 该装置包括多个片上网络端口; 从所述片上网络端口的第一片上网络端口接收数据并将所接收的数据发送到所述片上网络端口的第二片上网络端口; 以及接口单元,其连接从根据AMBA片上总线协议设计的因特网协议模块接收的先进的微控制器总线架构(AMBA)信号,并将接口结果输出到第一片上网络端口; 并且连接从第一片上网络端口接收的片上网络信号,并将接口结果输出到因特网协议模块。 因此,可以通过将根据AMBA 2.0片上总线协议的信号与根据片上网络协议的信号进行接口来以增加的速度建立通信。
    • 10. 发明申请
    • In-plane switching liquid crystal display having simple structure
    • 面内切换液晶显示器结构简单
    • US20070024792A1
    • 2007-02-01
    • US11493025
    • 2006-07-26
    • Jun ChangByoung JeonSoo Jang
    • Jun ChangByoung JeonSoo Jang
    • G02F1/1343
    • G02F1/134363G02F1/13363G02F2001/133635G02F2413/03
    • An IPS-LCD, in which the direction of an optical axis and retardation values are adjusted according to the disposition of a phase retardation film replacing one protective film, obtains a contrast ratio similar to that of an IPS-LCD having upper and lower protective films, and has a small thickness. The IPS-LCD includes first and second polarizing plates (1, 2), an IPS panel (3), and a first protective film. Absorption axes (4, 5) of the first and second polarizing plates (1, 2) are orthogonal to each other, and an optical axis of a liquid crystal in the IPS panel (3) and the absorption axis (4) are parallel with each other. A second phase retardation film, obtained by coating a biaxial film (17) with a uniaxial C film (11), is disposed between the second polarizing plate (2) and the IPS panel (3) and is used as a second protective film.
    • 根据更换一个保护膜的相位延迟膜的配置来调整光轴方向和延迟值的IPS-LCD获得与具有上保护膜和下保护膜的IPS-LCD类似的对比度 ,厚度小。 IPS-LCD包括第一和第二偏振片(1,2),IPS面板(3)和第一保护膜。 第一和第二偏振板(1,2)的吸收轴(4,5)彼此正交,并且IPS面板(3)和吸收轴(4)中的液晶的光轴与 彼此。 通过用单轴C膜(11)涂布双轴膜(17)而获得的第二相位延迟膜设置在第二偏振片(2)和IPS面板(3)之间,并用作第二保护膜。