专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07110305B2 Nonvolatile semiconductor memory device for outputting a status signal having an output data width wider than an input data width 有权
标题翻译：非易失性半导体存储器件，用于输出具有比输入数据宽度宽的输出数据宽度的状态信号
公开(公告)号：US07110305B2
公开(公告)日：2006-09-19
申请号：US11099605
申请日：2005-04-06
申请人： Hitoshi Suwa , Manabu Komiya , Yasuhiro Tomita
发明人： Hitoshi Suwa , Manabu Komiya , Yasuhiro Tomita
IPC分类号： G11C7/10
CPC分类号： G11C16/10
摘要： An n-bit status signal indicating an execution state of a write command is outputted from a status register. At the time of data writing, an output switching circuit outputs (n×m)-bit data in which a status signal pattern repeats m times. At the time of data reading, the output switching circuit outputs data stored in a memory cell array.
摘要翻译：从状态寄存器输出表示写命令执行状态的n位状态信号。在数据写入时，输出切换电路输出状态信号模式重复m次的（n×m）位数据。在数据读取时，输出切换电路输出存储在存储单元阵列中的数据。

2. 发明申请

US20050286299A1 Flash memory and program verify method for flash memory 有权
标题翻译：闪存的闪存和程序验证方法
公开(公告)号：US20050286299A1
公开(公告)日：2005-12-29
申请号：US11116440
申请日：2005-04-28
申请人： Yasuhiro Tomita , Hitoshi Suwa , Manabu Komiya , Tamas Toth , Jeffrey Jacob , Avi Parvin , Noam Eshel
发明人： Yasuhiro Tomita , Hitoshi Suwa , Manabu Komiya , Tamas Toth , Jeffrey Jacob , Avi Parvin , Noam Eshel
IPC分类号： G11C11/34 , G11C16/34
CPC分类号： G11C16/3454
摘要： In conventional memory arrays in which a bit line is shared by memory cells, a cell current flows over into neighbor cell(s) in a program verify process, and therefore, the threshold of a memory cell to be programmed is erroneously determined to be lower. Therefore, in a program verify process, a control circuit 3 writes a fail value to a neighbor cell buffer 5 when all neighbor cell(s) having an offset of n or less from a memory cell to be programmed are in the erased state, and when otherwise, writes a pass value to the neighbor cell buffer 5. The control circuit 3 verifies input write data and also verifies data stored in the neighbor cell buffer(s). In the latter verify process, a verify voltage higher than an ordinary one is used to compensate for the leakage of cell current.
摘要翻译：在存储器单元共享位线的常规存储器阵列中，在程序验证过程中，单元电流流过相邻单元，因此，要被编程的存储器单元的阈值被错误地确定为较低。因此，在程序验证处理中，当从要被编程的存储单元的偏移量为n以下的所有相邻单元都处于被擦除状态时，控制电路3向相邻单元缓冲器5写入失败值，否则，将通过值写入邻居单元缓冲器5。控制电路3验证输入写入数据，并验证存储在相邻单元缓冲器中的数据。在后一验证过程中，使用高于常规验证电压的验证电压来补偿电池电流的泄漏。

3. 发明授权

US07310277B2 Non-volatile semiconductor storage device with specific command enable/disable control signal 有权
标题翻译：具有特定命令的非易失性半导体存储器件使能/禁止控制信号
公开(公告)号：US07310277B2
公开(公告)日：2007-12-18
申请号：US11113046
申请日：2005-04-25
申请人： Manabu Komiya , Yasuhiro Tomita , Hitoshi Suwa
发明人： Manabu Komiya , Yasuhiro Tomita , Hitoshi Suwa
IPC分类号： G11C7/00
CPC分类号： G11C16/22
摘要： The non-volatile semiconductor storage device 101 includes the specific command Enable/Disable signal lines 120 connected to the command decoder 108. The specific command Enable/Disable signals are externally inputted to the command decoder 108 through the signal lines 120. Thereby, when the device 101 is initialized, the command decoder 108 enables the specific command and the device 101 can shift to a mode corresponding to the specific command. On the other hand, the command decoder 108 can disable the specific command, for example, when a user uses the device 101, thereby preventing the specific command from being executed even when the specific command is erroneously issued.
摘要翻译：非易失性半导体存储装置101包括连接到命令解码器108的特定命令启用/禁止信号线120。特定命令使能/禁止信号通过信号线120被外部输入到命令解码器108。因此，当初始化设备101时，命令解码器108启用特定命令，并且设备101可以转换到与特定命令相对应的模式。另一方面，命令解码器108可以例如当用户使用设备101时禁止特定命令，从而即使在特定命令被错误地发出时也防止特定命令被执行。

4. 发明授权

US07446549B2 Semiconductor leakage current detector and leakage current measurement method, semiconductor leakage current detector with voltage trimming function and reference voltage trimming method, and semiconductor integrated circuit thereof 有权
标题翻译：半导体漏电流检测器和漏电流测量方法，具有调压功能和参考电压调整方法的半导体漏电检测器及其半导体集成电路
公开(公告)号：US07446549B2
公开(公告)日：2008-11-04
申请号：US11614127
申请日：2006-12-21
申请人： Yasuhiro Tomita , Manabu Komiya , Hitoshi Suwa , Toshiki Mori
发明人： Yasuhiro Tomita , Manabu Komiya , Hitoshi Suwa , Toshiki Mori
IPC分类号： G01R31/02 , G01R19/14 , G01R31/08 , H03K5/22 , G08B21/00
CPC分类号： G01R31/3008 , G11C29/02 , G11C29/025 , G11C29/028 , G11C29/50 , G11C2029/1204 , G11C2029/5006
摘要： A semiconductor leakage current detector of the present invention includes a first analog switch which causes a current to be measured to flow or to be cut off, a second analog switch which causes a reference current to flow or to be cut off, an integral capacitance element which is connected by the first analog switch and the second analog switch and is charged with the current to be measured or the reference current, a discharge unit which discharges the integral capacitor, and a comparison unit which compares the reference voltage with each of an integral voltage generated in the integral capacitor by a reference current after the discharge of the integral capacitor and an integral voltage generated in the integral capacitance element by the current to be measured after the discharge of the integral capacitor.
摘要翻译：本发明的半导体泄漏电流检测器包括使得测量电流流动或切断的第一模拟开关，引起参考电流流动或被切断的第二模拟开关，积分电容元件其通过第一模拟开关和第二模拟开关连接，并对被测量电流或参考电流进行充电;放电单元，其对积分电容器进行放电;以及比较单元，其将参考电压与积分电压在积分电容器放电之后，在积分电容器中产生的电压由积分电容器放电后的基准电流产生，积分电容元件中产生的积分电压由积分电容器放电后的待测电流产生。

5. 发明授权

US07313649B2 Flash memory and program verify method for flash memory 有权
标题翻译：闪存的闪存和程序验证方法
公开(公告)号：US07313649B2
公开(公告)日：2007-12-25
申请号：US11116440
申请日：2005-04-28
申请人： Yasuhiro Tomita , Hitoshi Suwa , Manabu Komiya , Tamas Toth , Jeffrey Allan Jacob , Avi Parvin , Noam Eshel
发明人： Yasuhiro Tomita , Hitoshi Suwa , Manabu Komiya , Tamas Toth , Jeffrey Allan Jacob , Avi Parvin , Noam Eshel
IPC分类号： G06F12/00
CPC分类号： G11C16/3454
摘要： In conventional memory arrays in which a bit line is shared by memory cells, a cell current flows over into neighbor cell(s) in a program verify process, and therefore, the threshold of a memory cell to be programmed is erroneously determined to be lower. Therefore, in a program verify process, a control circuit 3 writes a fail value to a neighbor cell buffer 5 when all neighbor cell(s) having an offset of n or less from a memory cell to be programmed are in the erased state, and when otherwise, writes a pass value to the neighbor cell buffer 5. The control circuit 3 verifies input write data and also verifies data stored in the neighbor cell buffer(s). In the latter verify process, a verify voltage higher than an ordinary one is used to compensate for the leakage of cell current.
摘要翻译：在存储器单元共享位线的常规存储器阵列中，在程序验证过程中，单元电流流过相邻单元，因此，要被编程的存储器单元的阈值被错误地确定为较低。因此，在程序验证处理中，当从要被编程的存储单元的偏移量为n以下的所有相邻单元都处于被擦除状态时，控制电路3向相邻单元缓冲器5写入失败值，否则，将通过值写入邻居单元缓冲器5。控制电路3验证输入写入数据，并验证存储在相邻单元缓冲器中的数据。在后一验证过程中，使用高于常规验证电压的验证电压来补偿电池电流的泄漏。

6. 发明申请

US20050237826A1 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20050237826A1
公开(公告)日：2005-10-27
申请号：US11099605
申请日：2005-04-06
申请人： Hitoshi Suwa , Manabu Komiya , Yasuhiro Tomita
发明人： Hitoshi Suwa , Manabu Komiya , Yasuhiro Tomita
IPC分类号： G11C16/06 , G11C7/00 , G11C11/34 , G11C16/10
CPC分类号： G11C16/10
摘要： An n-bit status signal indicating an execution state of a write command is outputted from a status register. At the time of data writing, an output switching circuit outputs (n×m)-bit data in which a status signal pattern repeats m times. At the time of data reading, the output switching circuit outputs data stored in a memory cell array.
摘要翻译：从状态寄存器输出表示写命令执行状态的n位状态信号。在数据写入时，输出切换电路输出状态信号模式重复m次的（n×m）位数据。在数据读取时，输出切换电路输出存储在存储单元阵列中的数据。

7. 发明申请

US20050243616A1 Non-volatile semiconductor storage device 有权
标题翻译：非易失性半导体存储装置
公开(公告)号：US20050243616A1
公开(公告)日：2005-11-03
申请号：US11113046
申请日：2005-04-25
申请人： Manabu Komiya , Yasuhiro Tomita , Hitoshi Suwa
发明人： Manabu Komiya , Yasuhiro Tomita , Hitoshi Suwa
IPC分类号： G11C16/02 , G11C11/34 , G11C16/22
CPC分类号： G11C16/22
摘要： The non-volatile semiconductor storage device 101 includes the specific command Enable/Disable signal lines 120 connected to the command decoder 108. The specific command Enable/Disable signals are externally inputted to the command decoder 108 through the signal lines 120. Thereby, when the device 101 is initialized, the command decoder 108 enables the specific command and the device 101 can shift to a mode corresponding to the specific command. On the other hand, the command decoder 108 can disable the specific command, for example, when a user uses the device 101, thereby preventing the specific command from being executed even when the specific command is erroneously issued.
摘要翻译：非易失性半导体存储装置101包括连接到命令解码器108的特定命令启用/禁止信号线120。特定命令使能/禁止信号通过信号线120被外部输入到命令解码器108。因此，当初始化设备101时，命令解码器108启用特定命令，并且设备101可以转换到与特定命令相对应的模式。另一方面，命令解码器108可以例如当用户使用设备101时禁止特定命令，从而即使在特定命令被错误地发出时也防止特定命令被执行。

8. 发明授权

US07042275B2 Booster circuit 有权
标题翻译：增压电路
公开(公告)号：US07042275B2
公开(公告)日：2006-05-09
申请号：US10783025
申请日：2004-02-23
申请人： Hitoshi Suwa , Yukimasa Hamamoto
发明人： Hitoshi Suwa , Yukimasa Hamamoto
IPC分类号： H02M3/15 , G05F3/02
CPC分类号： H02M3/073
摘要： Each boosting cell includes: a first n-transistor having a diode connection; a second n-transistor whose gate and drain are connected to a power supply voltage and whose source is connected to the source of the first n-transistor; and a boosting capacitor provided between the drain of the first n-transistor and a boosting clock input terminal to which a clock signal is input. The boosting capacitor is connected to n auxiliary boosting capacitors in parallel via connection switching circuits controlled with boosting ability switching signals as control signals input from the outside.
摘要翻译：每个升压单元包括：具有二极管连接的第一n型晶体管; 栅极和漏极连接到电源电压并且其源极连接到第一n型晶体管的源极的第二n型晶体管; 以及设置在第一n型晶体管的漏极和输入时钟信号的升压时钟输入端之间的升压电容器。升压电容器通过作为从外部输入的控制信号的升压能力切换信号控制的连接开关电路并联连接到n个辅助升压电容器。

9. 发明申请

US20070133277A1 Non-volatile semiconductor memory device 审中-公开
标题翻译：非易失性半导体存储器件
公开(公告)号：US20070133277A1
公开(公告)日：2007-06-14
申请号：US11602272
申请日：2006-11-21
申请人： Ken Kawai , Ryotaro Azuma , Akifumi Kawahara , Hitoshi Suwa , Hoshihide Haruyama
发明人： Ken Kawai , Ryotaro Azuma , Akifumi Kawahara , Hitoshi Suwa , Hoshihide Haruyama
IPC分类号： G11C16/04
CPC分类号： G11C16/12 , G11C11/5628 , G11C16/16 , G11C16/3454 , G11C16/3459 , G11C2211/5621 , G11C2211/5641
摘要： A memory cell transistor array is composed of a plurality of memory cells having three or more threshold voltage distribution states in a single electric charge accumulation portion. A program sequence control circuit associates each piece of data included in a data set composed of a plurality of data values with any threshold voltage distribution of the three or more threshold voltage distributions, to store the data in the memory cell, and when rewriting the data stored in the memory cell, shifting threshold voltage distributions used for data storage in one direction to perform the data rewrite operation.
摘要翻译：存储单元晶体管阵列由在单个电荷累积部分中具有三个或更多个阈值电压分布状态的多个存储单元组成。程序序列控制电路将由多个数据值组成的数据组中包括的每条数据与三个或更多阈值电压分布的任何阈值电压分布相关联，以将数据存储在存储单元中，并且当重写数据时存储在存储单元中，用于在一个方向上用于数据存储的阈值电压分布，以执行数据重写操作。

10. 发明申请

US20120002485A1 SEMICONDUCTOR MEMORY DEVICE 审中-公开
标题翻译：半导体存储器件
公开(公告)号：US20120002485A1
公开(公告)日：2012-01-05
申请号：US13233789
申请日：2011-09-15
申请人： Hitoshi Suwa , Takafumi Maruyama , Takashi Ono , Tadashi Nitta , Kazuyo Nishikawa , Masahiro Ueminami
发明人： Hitoshi Suwa , Takafumi Maruyama , Takashi Ono , Tadashi Nitta , Kazuyo Nishikawa , Masahiro Ueminami
IPC分类号： G11C16/10 , G11C16/14
CPC分类号： G11C16/10 , G11C16/30 , G11C16/3404
摘要： In a semiconductor memory circuit, a write voltage generation circuit receives an output voltage of a voltage boosting circuit to generate a write voltage to a memory cell. When the write voltage is low, a number-of-bits adjustment circuit increases the number of write bits of memory cells before write operation is performed. On the other hand, when the write voltage to a memory cell is high, the number-of-bits adjustment circuit decreases the number of write bits of memory cells before write operation is performed. The area and write time of the voltage boosting circuit can be reduced while the current supply capability of the voltage boosting circuit is efficiently used.
摘要翻译：在半导体存储器电路中，写入电压产生电路接收升压电路的输出电压以向存储单元产生写入电压。当写入电压低时，位数调节电路在执行写入操作之前增加存储器单元的写入位数。另一方面，当存储单元的写入电压为高时，位数调节电路在执行写入操作之前减少存储器单元的写入位数。可以降低升压电路的面积和写入时间，同时有效地使用升压电路的电流供给能力。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式