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1. 发明授权

US07313649B2 Flash memory and program verify method for flash memory 有权
标题翻译：闪存的闪存和程序验证方法
公开(公告)号：US07313649B2
公开(公告)日：2007-12-25
申请号：US11116440
申请日：2005-04-28
申请人： Yasuhiro Tomita , Hitoshi Suwa , Manabu Komiya , Tamas Toth , Jeffrey Allan Jacob , Avi Parvin , Noam Eshel
发明人： Yasuhiro Tomita , Hitoshi Suwa , Manabu Komiya , Tamas Toth , Jeffrey Allan Jacob , Avi Parvin , Noam Eshel
IPC分类号： G06F12/00
CPC分类号： G11C16/3454
摘要： In conventional memory arrays in which a bit line is shared by memory cells, a cell current flows over into neighbor cell(s) in a program verify process, and therefore, the threshold of a memory cell to be programmed is erroneously determined to be lower. Therefore, in a program verify process, a control circuit 3 writes a fail value to a neighbor cell buffer 5 when all neighbor cell(s) having an offset of n or less from a memory cell to be programmed are in the erased state, and when otherwise, writes a pass value to the neighbor cell buffer 5. The control circuit 3 verifies input write data and also verifies data stored in the neighbor cell buffer(s). In the latter verify process, a verify voltage higher than an ordinary one is used to compensate for the leakage of cell current.
摘要翻译：在存储器单元共享位线的常规存储器阵列中，在程序验证过程中，单元电流流过相邻单元，因此，要被编程的存储器单元的阈值被错误地确定为较低。因此，在程序验证处理中，当从要被编程的存储单元的偏移量为n以下的所有相邻单元都处于被擦除状态时，控制电路3向相邻单元缓冲器5写入失败值，否则，将通过值写入邻居单元缓冲器5。控制电路3验证输入写入数据，并验证存储在相邻单元缓冲器中的数据。在后一验证过程中，使用高于常规验证电压的验证电压来补偿电池电流的泄漏。

2. 发明申请

US20050286299A1 Flash memory and program verify method for flash memory 有权
标题翻译：闪存的闪存和程序验证方法
公开(公告)号：US20050286299A1
公开(公告)日：2005-12-29
申请号：US11116440
申请日：2005-04-28
申请人： Yasuhiro Tomita , Hitoshi Suwa , Manabu Komiya , Tamas Toth , Jeffrey Jacob , Avi Parvin , Noam Eshel
发明人： Yasuhiro Tomita , Hitoshi Suwa , Manabu Komiya , Tamas Toth , Jeffrey Jacob , Avi Parvin , Noam Eshel
IPC分类号： G11C11/34 , G11C16/34
CPC分类号： G11C16/3454
摘要： In conventional memory arrays in which a bit line is shared by memory cells, a cell current flows over into neighbor cell(s) in a program verify process, and therefore, the threshold of a memory cell to be programmed is erroneously determined to be lower. Therefore, in a program verify process, a control circuit 3 writes a fail value to a neighbor cell buffer 5 when all neighbor cell(s) having an offset of n or less from a memory cell to be programmed are in the erased state, and when otherwise, writes a pass value to the neighbor cell buffer 5. The control circuit 3 verifies input write data and also verifies data stored in the neighbor cell buffer(s). In the latter verify process, a verify voltage higher than an ordinary one is used to compensate for the leakage of cell current.
摘要翻译：在存储器单元共享位线的常规存储器阵列中，在程序验证过程中，单元电流流过相邻单元，因此，要被编程的存储器单元的阈值被错误地确定为较低。因此，在程序验证处理中，当从要被编程的存储单元的偏移量为n以下的所有相邻单元都处于被擦除状态时，控制电路3向相邻单元缓冲器5写入失败值，否则，将通过值写入邻居单元缓冲器5。控制电路3验证输入写入数据，并验证存储在相邻单元缓冲器中的数据。在后一验证过程中，使用高于常规验证电压的验证电压来补偿电池电流的泄漏。

3. 发明授权

US06981188B2 Non-volatile memory device with self test 失效
标题翻译：具有自检功能的非易失性存储器件
公开(公告)号：US06981188B2
公开(公告)日：2005-12-27
申请号：US09931848
申请日：2001-08-16
申请人： Ori Galzur , Tamas Toth
发明人： Ori Galzur , Tamas Toth
IPC分类号： G11C29/38 , G11C29/44 , G11C29/00
CPC分类号： G11C29/44 , G11C29/38
摘要： Self-test instructions are loaded from a tester into a configuration array of a memory device, and then a control circuit of the memory device sequentially reads and executes the self-test instructions while the tester is in an idle state. Data patterns are written to a main memory array of the memory device the internal self-test process. The control circuit includes a comparator for detecting defective memory cells by comparing data values read from the main array with the data pattern previously written into the main memory array. A BIN counter identifies the currently-executed self-test instruction, and is read and transmitted to the tester when an error is detected.
摘要翻译：自检指令从测试器加载到存储器件的配置阵列中，然后当测试器处于空闲状态时，存储器件的控制电路顺序读取并执行自检指令。数据模式被写入存储器件的主存储器阵列的内部自检过程。控制电路包括比较器，用于通过将从主阵列读取的数据值与先前写入主存储器阵列的数据图案进行比较来检测缺陷存储器单元。 BIN计数器识别当前执行的自检指令，并在检测到错误时读取并发送给测试仪。

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