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1. 发明授权

US5828860A Data processing device equipped with cache memory and a storage unit for storing data between a main storage or CPU cache memory 失效
标题翻译：配备有高速缓冲存储器的数据处理装置和用于在主存储器或CPU缓存存储器之间存储数据的存储单元
公开(公告)号：US5828860A
公开(公告)日：1998-10-27
申请号：US739062
申请日：1996-10-28
申请人： Hitoshi Miyaoku , Atsuhiro Suga , Koichi Sasamori , Kazuhide Yoshino
发明人： Hitoshi Miyaoku , Atsuhiro Suga , Koichi Sasamori , Kazuhide Yoshino
IPC分类号： G06F9/312 , G06F9/38 , G06F12/08
CPC分类号： G06F9/3814 , G06F12/0855 , G06F12/0862 , G06F9/30043 , G06F9/3802 , G06F9/3824 , G06F9/383 , G06F2212/6022 , G06F2212/6028
摘要： A data processing device includes a cache memory, a load buffer primary (LBP) for storing 1-line instruction data including an instruction requested to be transmitted by an instruction processing unit and transmitted from a main storage or a secondary cache memory, and a load buffer secondary (LBS) for storing 1-line instruction data preceded by the above described 1-line data. With this configuration, the device may determine the validity of prefetched data in the LBP using lower order bits of the addresses of the data. If the data are determined to be valid, the data stored in the LBS are stored in the cache memory. A cache storage device, hierarchically provided between a central processing unit a n d a main storage device, includes a cache memory, a storage buffer, a write-in buffer and a cache storage control unit. The cache storage device fast writes storage data into a write-in buffer instead of directly into cache memory. In the case of a miss in an access to a cache tag during the execution of a load command, move-in data are read out from the main storage device or a cache storage device of a different hierarchy, for storage into a write-in buffer. The data stored in the write-in buffer are then written into cache memory when the central processing unit executes another store command.
摘要翻译：数据处理装置包括高速缓存存储器，用于存储包括由指令处理单元请求发送并从主存储器或辅助高速缓存存储器发送的指令的1行指令数据的加载缓冲器初级（LBP）和负载用于存储在上述1行数据之前的1行指令数据的缓存次级（LBS）。利用该配置，设备可以使用数据的地址的低位来确定LBP中预取数据的有效性。如果数据被确定为有效，则存储在LBS中的数据被存储在高速缓冲存储器中。分层地设置在主存储装置的中央处理单元之间的高速缓存存储装置包括高速缓冲存储器，存储缓冲器，写入缓冲器和高速缓存存储控制单元。高速缓存存储设备将存储数据快速写入写入缓冲区，而不是直接写入高速缓存。在执行加载命令期间访问高速缓存标签的错误的情况下，从主存储设备或不同层次的高速缓存存储设备读出移入数据，以存储到写入缓冲。当中央处理单元执行另一个存储命令时，存储在写入缓冲器中的数据被写入高速缓冲存储器。

2. 发明授权

US6076145A Data supplying apparatus for independently performing hit determination and data access 有权
标题翻译：用于独立执行命中确定和数据访问的数据提供装置
公开(公告)号：US6076145A
公开(公告)日：2000-06-13
申请号：US211045
申请日：1998-12-15
申请人： Takuya Iwata , Atsuhiro Suga
发明人： Takuya Iwata , Atsuhiro Suga
IPC分类号： G06F12/08 , G06F9/38
CPC分类号： G06F9/3802 , G06F12/0855 , G06F12/0875
摘要： An address buffer that stores information used to access a data memory is disposed in a cache unit that supplies data such as an instruction code to an instruction executing unit. A tag memory and a data memory are independently accessed. The data memory is accessed corresponding to access information stored in the address buffer. Data is output from the data memory in the input order of data requests. When a data release signal is not received from the instruction executing unit, since access information is buffered in the address buffer, a large data buffer for storing the output data of the data memory is not required. In addition, in an associative type cache unit, the tag memory and the address buffer can be formed in the same memory.
摘要翻译：存储用于访问数据存储器的信息的地址缓冲器设置在向指令执行单元提供诸如指令代码的数据的高速缓存单元中。标签存储器和数据存储器被独立地访问。对应于存储在地址缓冲器中的访问信息访问数据存储器。数据以数据请求的输入顺序从数据存储器输出。当没有从指令执行单元接收到数据释放信号时，由于访问信息被缓存在地址缓冲器中，所以不需要用于存储数据存储器的输出数据的大数据缓冲器。此外，在关联型高速缓存单元中，标签存储器和地址缓冲器可以形成在同一存储器中。

3. 发明申请

US20090217247A1 Program performance analysis apparatus 有权
标题翻译：程序性能分析仪
公开(公告)号：US20090217247A1
公开(公告)日：2009-08-27
申请号：US12382753
申请日：2009-03-23
申请人： Teruhiko Kamigata , Atsuhiro Suga , Shigeru Kimura
发明人： Teruhiko Kamigata , Atsuhiro Suga , Shigeru Kimura
IPC分类号： G06F9/44
CPC分类号： G06F11/3612 , G06F11/3428 , G06F2201/865
摘要： To provide a program performance analysis apparatus that can present to a user whether tuning made to a program operating on a predetermined hardware is either good or bad, a performance information acquisition unit for obtaining the performance information of a program, a difference information generation unit for generating difference information by making a comparison between the performance information of a first program and that of a second program obtained by making a change to the first program, and a change evaluation unit for evaluating whether the change is either good or bad are comprised.
摘要翻译：为了提供一种程序性能分析装置，其可以向用户呈现无论对在预定硬件上操作的程序的调谐是好还是坏，执行信息获取单元用于获得程序的性能信息，差异信息生成单元，用于通过对第一程序的性能信息和通过对第一程序进行改变而获得的第二程序的性能信息进行比较来生成差异信息，以及用于评估变化是好还是坏的变化评估单元。

4. 发明申请

US20090007087A1 PROGRAM ANALYZING METHOD, PROGRAM ANALYZING APPARATUS AND PROGRAM ANALYZING PROGRAM 有权
标题翻译：程序分析方法，程序分析装置和程序分析程序
公开(公告)号：US20090007087A1
公开(公告)日：2009-01-01
申请号：US12191623
申请日：2008-08-14
申请人： Makiko Ito , Hideo Miyake , Atsuhiro Suga
发明人： Makiko Ito , Hideo Miyake , Atsuhiro Suga
IPC分类号： G06F9/45
CPC分类号： G06F11/3604
摘要： A dependent element group which is invertibly contractible is found by using program analysis information including a plurality of dependent elements representing dependent relationships of statement and control, the statement and the control being included in a program. Next, a program dependence graph in which dependent elements are made to be contracted is generated by contracting the found dependent element group. The number of vertices and the number of edges of the program dependence graph are reduced by the contraction of the dependent elements, so that a program dependence graph with a rough granularity can be generated. As a result, a calculation amount (calculation time) necessary for optimization processing such as parallel processing of the program can be reduced. That is, by generating the contracted program dependence graph having invertibility, it is possible to realize the analysis and optimization of large-scale software in a realistic time.
摘要翻译：通过使用包括表示语句和控制的依赖关系的多个依赖元素的程序分析信息，语句和控件被包括在程序中，可以发现可逆收缩的依赖元素组。接下来，通过收合找到的依赖元素组来生成依赖元素被收缩的程序依赖图。通过依赖元素的收缩减少程序依赖图的顶点数和边数，从而可以生成具有粗略粒度的程序依赖图。结果，可以减少诸如程序的并行处理的优化处理所需的计算量（计算时间）。也就是说，通过生成具有可逆性的合同程序依赖图，可以在实际的时间内实现大规模软件的分析和优化。

5. 发明申请

US20080215859A1 Computer with high-speed context switching 审中-公开
标题翻译：具有高速上下文切换的计算机
公开(公告)号：US20080215859A1
公开(公告)日：2008-09-04
申请号：US12073042
申请日：2008-02-28
申请人： Hideo Miyake , Atsuhiro Suga , Yasuki Nakamura , Masayuki Tsuji , Yasuhiro Yamazaki , Yoshimasa Takebe , Taizo Sato , Shinichiro Tago
发明人： Hideo Miyake , Atsuhiro Suga , Yasuki Nakamura , Masayuki Tsuji , Yasuhiro Yamazaki , Yoshimasa Takebe , Taizo Sato , Shinichiro Tago
IPC分类号： G06F9/312 , G06F9/302
CPC分类号： G06F7/535 , G06F9/3001 , G06F9/30043 , G06F9/3013 , G06F9/3814 , G06F9/3836 , G06F9/3857 , G06F9/3861 , G06F9/3867 , G06F9/3877 , G06F9/461 , G06F9/5016 , G06F2207/5353 , Y02D10/22
摘要： A computer which performs parallel processing of a plurality of programs in a time-division fashion includes hardware resources divided into a plurality of areas, an evacuation unit which records identification information identifying a first program, and evacuates information stored in an area of said plurality of areas if the area is necessary for execution of a second program and is being used for execution of the first program, and a restoration unit which restores the evacuated information to the area based on the identification information when the second program comes to a halt or to an end.
摘要翻译：以时分方式执行多个程序的并行处理的计算机包括划分为多个区域的硬件资源，记录识别第一程序的识别信息的撤离单元，以及排除存储在所述多个区域的区域中的信息如果该区域是执行第二程序所必需的并被用于执行第一程序的区域，以及恢复单元，其在第二程序停止时基于识别信息将该撤离信息恢复到该区域，或者结束。

6. 发明授权

US07376820B2 Information processing unit, and exception processing method for specific application-purpose operation instruction 有权
标题翻译：信息处理单元和特殊应用目的操作指令的异常处理方法
公开(公告)号：US07376820B2
公开(公告)日：2008-05-20
申请号：US09741802
申请日：2000-12-22
申请人： Michihide Kimura , Atsuhiro Suga , Hideo Miyake , Satoshi Imai , Yasuki Nakamura
发明人： Michihide Kimura , Atsuhiro Suga , Hideo Miyake , Satoshi Imai , Yasuki Nakamura
IPC分类号： G06F9/44 , G06F9/54
CPC分类号： G06F9/3838 , G06F9/3836 , G06F9/3857 , G06F9/3859 , G06F9/3861 , G06F9/3879
摘要： In the control section, an operation instruction not prescribing a functional specification, and a unit for processing the specific application-purpose operation instruction is provided within the processor core. The structure of this unit can be changed based on a flexible pipeline structure, and is separately designed for each application field. A register that prescribes a latency from when an instruction of the above unit is issued till when a result can be utilized is also provided in the processor core so as to prevent contention of an output port. Another register that prescribes a latency relating to a constraint of an interval of issuing an instruction of the above unit is also provided in the processor core so as to prevent contention of a resource with the preceding instructions.
摘要翻译：在处理器核心中，在控制部分中提供不指定功能规格的操作指令和用于处理特定应用目的操作指令的单元。该单元的结构可以基于灵活的管道结构进行更改，并为每个应用领域单独设计。在处理器核心中还设置有从上述单元的指令发出到可以利用结果的延迟的寄存器，以防止输出端口的争用。规定与发布上述单元的指令的间隔的约束有关的延迟的另一个寄存器也被提供在处理器核心中，以便防止具有前面指令的资源的争用。

7. 发明授权

US08549227B2 Multiprocessor system and operating method of multiprocessor system 有权
标题翻译：多处理器系统的多处理器系统和操作方法
公开(公告)号：US08549227B2
公开(公告)日：2013-10-01
申请号：US12199240
申请日：2008-08-27
申请人： Shinichiro Tago , Atsuhiro Suga
发明人： Shinichiro Tago , Atsuhiro Suga
IPC分类号： G06F13/00
CPC分类号： G06F12/0811 , G06F2212/271 , G06F2212/601
摘要： According to one aspect of embodiments, a multiprocessor system includes a cache memory corresponding to each of the processors, a hierarchy setting register in which the hierarchical level of each cache memory is set, an access control unit that controls access between each cache memory. The hierarchical level of the cache memory for each processor is stored in a rewritable hierarchy setting register. Each processor handles a cache memory corresponding to another processor as the cache memory having a deeper hierarchy than the cache memory corresponding to the each processor. As the result, each processor can access all the cache memories, and therefore the efficiency of cache memory utilization can be improved and the hierarchical level can be set so that the latency becomes optimal for each application.
摘要翻译：根据实施例的一个方面，多处理器系统包括对应于每个处理器的高速缓存存储器，其中设置每个高速缓存存储器的层级的层次结构设置寄存器，控制每个高速缓冲存储器之间的访问的访问控制单元。每个处理器的高速缓冲存储器的层次级存储在可重写层次结构设置寄存器中。每个处理器处理与另一个处理器相对应的高速缓冲存储器，因为高速缓冲存储器具有比对应于每个处理器的高速缓冲存储器更深的层级。结果，每个处理器可以访问所有高速缓冲存储器，因此可以提高高速缓冲存储器利用率的效率，并且可以设置层次级别，使得等待时间对于每个应用来说是最佳的。

8. 发明授权

US08181171B2 Method and apparatus for analyzing large scale program and generation of code from degenerated program dependence graph 有权
标题翻译：用于从退化程序依赖图中分析大规模程序和代码生成的方法和装置
公开(公告)号：US08181171B2
公开(公告)日：2012-05-15
申请号：US12191623
申请日：2008-08-14
申请人： Makiko Ito , Hideo Miyake , Atsuhiro Suga
发明人： Makiko Ito , Hideo Miyake , Atsuhiro Suga
IPC分类号： G06F9/45 , G06F9/44
CPC分类号： G06F11/3604
摘要： A dependent element group which is invertibly contractible is found by using program analysis information including a plurality of dependent elements representing dependent relationships of statement and control, the statement and the control being included in a program. Next, a program dependence graph in which dependent elements are made to be contracted is generated by contracting the found dependent element group. The number of vertices and the number of edges of the program dependence graph are reduced by the contraction of the dependent elements, so that a program dependence graph with a rough granularity can be generated. As a result, a calculation amount (calculation time) necessary for optimization processing such as parallel processing of the program can be reduced. That is, by generating the contracted program dependence graph having invertibility, it is possible to realize the analysis and optimization of large-scale software in a realistic time.
摘要翻译：通过使用包括表示语句和控制的依赖关系的多个依赖元素的程序分析信息，语句和控件被包括在程序中，可以发现可逆收缩的依赖元素组。接下来，通过收合找到的依赖元素组来生成依赖元素被收缩的程序依赖图。通过依赖元素的收缩减少程序依赖图的顶点数和边数，从而可以生成具有粗略粒度的程序依赖图。结果，可以减少诸如程序的并行处理的优化处理所需的计算量（计算时间）。也就是说，通过生成具有可逆性的合同程序依赖图，可以在实际的时间内实现大规模软件的分析和优化。

9. 发明授权

US07581090B2 Interrupt control apparatus and method 有权
标题翻译：中断控制装置及方法
公开(公告)号：US07581090B2
公开(公告)日：2009-08-25
申请号：US10692800
申请日：2003-10-27
申请人： Hideo Miyake , Atsuhiro Suga , Yasuki Nakamura
发明人： Hideo Miyake , Atsuhiro Suga , Yasuki Nakamura
IPC分类号： G06F9/00
CPC分类号： G06F9/4812 , G06F13/24
摘要： When a normal interrupt occurs, data of processor operation before the normal interrupt are held in a normal return address register (452), a normal previous state register (453), and a normal factor register (454). When a break-interrupt occurs, data of processor operation before the break-interrupt is held in another break return address register (455). Hence, a break-interrupt can occur even within an interrupt inhibition period by a normal interrupt. Besides, when a break-interrupt occurs, the break-interrupt state is set in a flag register (456). By referring to the flag register (456) in executing an interrupt return instruction, the operation data before the break-interrupt or before the normal interrupt can accurately be restored.
摘要翻译：当正常中断发生时，在正常中断之前的处理器操作的数据被保存在正常的返回地址寄存器（452），正常的先前状态寄存器（453）和正常因子寄存器（454）中。当发生中断中断时，中断中断前的处理器操作数据保存在另一个中断返回地址寄存器（455）中。因此，即使在正常中断的中断禁止期间，中断也可能发生。此外，当发生中断中断时，中断中断状态被设置在标志寄存器（456）中。通过参考标志寄存器（456）执行中断返回指令，可以准确地恢复中断中断前或正常中断前的操作数据。

10. 发明授权

US07134004B1 Processing device for buffering sequential and target sequences and target address information for multiple branch instructions 失效
标题翻译：用于缓冲顺序和目标序列的处理设备以及多个分支指令的目标地址信息
公开(公告)号：US07134004B1
公开(公告)日：2006-11-07
申请号：US09666853
申请日：2000-09-20
申请人： Shin-ichiro Tago , Taizo Sato , Yoshimasa Takebe , Yasuhiro Yamazaki , Teruhiko Kamigata , Atsuhiro Suga , Hiroshi Okano , Hitoshi Yoda
发明人： Shin-ichiro Tago , Taizo Sato , Yoshimasa Takebe , Yasuhiro Yamazaki , Teruhiko Kamigata , Atsuhiro Suga , Hiroshi Okano , Hitoshi Yoda
IPC分类号： G06F9/00
CPC分类号： G06F9/3804 , G06F9/3806 , G06F9/3846
摘要： An information processing device reads, buffers, decodes and executes instructions from an instruction store portion by pipeline processing includes: an instruction reading request portion which assigns a read address to the instruction store portion, an instruction buffering portion which includes a plurality of instruction buffers which buffer an instruction sequence read from the instruction store portion; an instruction execution unit which decodes and executes instructions buffered by the instruction buffering portion. A branching instruction detection portion detects a branching instruction in the instruction sequence read from the instruction store portion. A branch target address information buffering portion includes a plurality of branch target address information buffers which, when the branching instruction detection portion has detected a branching instruction, buffer the branch target address information for generating the branch target address of the branching instruction.
摘要翻译：信息处理装置通过流水线处理从指令存储部分读取，缓冲，解码和执行指令，包括：向指令存储部分分配读取地址的指令读取请求部分，包括多个指令缓冲器的指令缓冲部分，缓冲从指令存储部分读取的指令序列; 指令执行单元，其对由指令缓冲部分缓冲的指令进行解码和执行。分支指令检测部分检测从指令存储部分读取的指令序列中的分支指令。分支目标地址信息缓冲部分包括多个分支目标地址信息缓冲器，当分支指令检测部分已经检测到分支指令时，缓冲用于生成分支指令的分支目标地址的转移目标地址信息。

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