专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06198128B1 Method of manufacturing a semiconductor device, and semiconductor device 有权
标题翻译：制造半导体器件的方法和半导体器件
公开(公告)号：US06198128B1
公开(公告)日：2001-03-06
申请号：US09390662
申请日：1999-09-07
申请人： Hisao Asakura , Yoshitaka Tadaki , Toshihiro Sekiguchi , Ryo Nagai , Masafumi Miyamoto , Masayuki Nakamura , Shinichi Miyatake , Tsuyuki Suzuki , Masahiro Hyoma
发明人： Hisao Asakura , Yoshitaka Tadaki , Toshihiro Sekiguchi , Ryo Nagai , Masafumi Miyamoto , Masayuki Nakamura , Shinichi Miyatake , Tsuyuki Suzuki , Masahiro Hyoma
IPC分类号： H01L2972
CPC分类号： H01L29/66537 , H01L21/26586 , H01L21/823814
摘要： In a case where an impurity for suppressing the short channel effect of MISFETs is introduced into a semiconductor substrate obliquely to the principal surface thereof, gate electrodes adjacent to each other are arranged so that the impurity to be introduced in directions crossing the gate electrodes may not be introduced into the part of the semiconductor substrate lying between the gate electrodes, and the source region of the MISFETs is arranged in the part between the gate electrodes.
摘要翻译：在用于抑制MISFET的短沟道效应的杂质与其主表面倾斜地引入半导体衬底的情况下，彼此相邻的栅电极被布置成使得沿与栅电极交叉的方向引入的杂质不会被引入位于栅电极之间的半导体衬底的部分中，并且MISFET的源极区域被布置在栅电极之间的部分中。

2. 发明授权

US06287912B1 Method of fabricating semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US06287912B1
公开(公告)日：2001-09-11
申请号：US09389457
申请日：1999-09-03
申请人： Hisao Asakura , Yoshitaka Tadaki , Toshihiro Sekiguchi , Ryo Nagai , Masafumi Miyamoto , Masayuki Nakamura
发明人： Hisao Asakura , Yoshitaka Tadaki , Toshihiro Sekiguchi , Ryo Nagai , Masafumi Miyamoto , Masayuki Nakamura
IPC分类号： H01L218242
CPC分类号： H01L27/10894 , H01L21/823857 , H01L27/10852 , H01L27/10873 , Y10S438/981
摘要： A mask for etching a relatively thin gate insulating film formed in a gate insulating film forming region is formed by patterning a photoresist film, and the mask is used for introducing an impurity for adjusting the threshold voltages of n-channel field-effect transistors and p-channel field-effect transistors having the relatively thin gate insulating film into regions on the semiconductor substrate not covered with the mask.
摘要翻译：通过图案化光致抗蚀剂膜形成用于蚀刻形成在栅极绝缘膜形成区域中的相对薄的栅极绝缘膜的掩模，并且该掩模用于引入用于调节n沟道场效应晶体管的阈值电压的杂质和p - 沟道场效应晶体管，其具有相对较薄的栅极绝缘膜到半导体衬底上未被掩模覆盖的区域。

3. 发明授权

US6077735A Method of manufacturing semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US6077735A
公开(公告)日：2000-06-20
申请号：US708104
申请日：1996-08-28
申请人： Yuji Ezaki , Shinya Nishio , Fumiaki Saitoh , Hideo Nagasawa , Toshiyuki Kaeriyama , Songsu Cho , Hisao Asakura , Jun Murata , Yoshitaka Tadaki , Toshihiro Sekiguchi , Keizo Kawakita
发明人： Yuji Ezaki , Shinya Nishio , Fumiaki Saitoh , Hideo Nagasawa , Toshiyuki Kaeriyama , Songsu Cho , Hisao Asakura , Jun Murata , Yoshitaka Tadaki , Toshihiro Sekiguchi , Keizo Kawakita
IPC分类号： H01L21/316 , H01L21/265 , H01L21/762 , H01L21/8234 , H01L21/8238 , H01L21/8242 , H01L27/092 , H01L27/108
CPC分类号： H01L21/76218 , H01L21/823493 , H01L21/823878
摘要： A method of making semiconductor devices which enables control of the impurity concentration and fine patterning by making removal of residual stress due LOCOS oxidation compatible with the formation of deep wells. A selective oxide layer is formed for separating element regions on a principal plane of a semiconductor substrate, for example, a p.sup.- -type silicon substrate 1. A mask is formed (for example photoresist 47) on the surface including the selective oxide layer and impurities (for example phosphorous) of a conductivity type opposite that of the semiconductor substrate are introduced via an opening in the mask. Then the selective oxide film is annealed by a high-temperature treatment while a deep well (for example n-type deep well 50) is formed by introducing the impurities.
摘要翻译：制造半导体器件的方法，其能够通过去除与深孔形成相关的LOCOS氧化的残留应力来控制杂质浓度和精细图案化。形成用于分离半导体衬底的主平面上的元件区域的选择性氧化物层，例如p型硅衬底1.在包括选择性氧化物层的表面上形成掩模（例如光致抗蚀剂47）通过掩模中的开口引入与半导体衬底的导电类型相反的导电类型的杂质（例如磷）。然后，通过引入杂质形成深阱（例如n型深阱50），通过高温处理退火选择性氧化物膜。

4. 发明授权

US06737318B2 Semiconductor integrated circuit device having switching misfet and capacitor element and method of producing the same, including wiring therefor and method of producing such wiring 失效
标题翻译：具有开关错位和电容器元件的半导体集成电路器件及其制造方法，包括其布线及其制造方法
公开(公告)号：US06737318B2
公开(公告)日：2004-05-18
申请号：US09998654
申请日：2001-12-03
申请人： Jun Murata , Yoshitaka Tadaki , Isamu Asano , Mitsuaki Horiuchi , Jun Sugiura , Hiroko Kaneko , Shinji Shimizu , Atsushi Hiraiwa , Hidetsugu Ogishi , Masakazu Sagawa , Masami Ozawa , Toshihiro Sekiguchi
发明人： Jun Murata , Yoshitaka Tadaki , Isamu Asano , Mitsuaki Horiuchi , Jun Sugiura , Hiroko Kaneko , Shinji Shimizu , Atsushi Hiraiwa , Hidetsugu Ogishi , Masakazu Sagawa , Masami Ozawa , Toshihiro Sekiguchi
IPC分类号： H01L218242
CPC分类号： H01L27/105 , H01L27/10808
摘要： A method of manufacturing a semiconductor integrated circuit device having a switching MISFET and a capacitor element formed over a semiconductor substrate, such as a DRAM, is disclosed. The dielectric film of the capacitor element is formed to be co-extensive with the capacitor electrode layer over it. The upper electrode of the capacitor element is formed to be larger than the lower electrode.
摘要翻译：公开了一种制造半导体集成电路器件的方法，该半导体集成电路器件具有形成在诸如DRAM之类的半导体衬底上的开关MISFET和电容元件。电容器元件的电介质膜形成为与其上的电容器电极层共同扩展。电容器元件的上电极形成为比下电极大。

5. 发明授权

US06638811B2 Method of manufacturing a semiconductor integrated circuit device having a capacitor 有权
标题翻译：具有电容器的半导体集成电路器件的制造方法
公开(公告)号：US06638811B2
公开(公告)日：2003-10-28
申请号：US10157977
申请日：2002-05-31
申请人： Masayoshi Saito , Yoshitaka Nakamura , Hidekazu Goto , Keizo Kawakita , Satoru Yamada , Toshihiro Sekiguchi , Isamu Asano , Yoshitaka Tadaki , Takuya Fukuda , Masayuki Suzuki , Tsuyoshi Tamaru , Naoki Fukuda , Hideo Aoki , Masayoshi Hirasawa
发明人： Masayoshi Saito , Yoshitaka Nakamura , Hidekazu Goto , Keizo Kawakita , Satoru Yamada , Toshihiro Sekiguchi , Isamu Asano , Yoshitaka Tadaki , Takuya Fukuda , Masayuki Suzuki , Tsuyoshi Tamaru , Naoki Fukuda , Hideo Aoki , Masayoshi Hirasawa
IPC分类号： H01L218242
CPC分类号： H01L21/76855 , H01L21/28518 , H01L21/31604 , H01L21/76801 , H01L21/76828 , H01L21/76837 , H01L21/76843 , H01L21/76856 , H01L21/7687 , H01L27/10814 , H01L27/10885 , H01L27/10894 , H01L28/40
摘要： In a DRAM having a capacitor-over-bitline structure in which the capacitive insulating film of an information storing capacitive element C is formed of a high dielectric material such as Ta2O5 (tantalum oxide) film 46, the portions of bit lines BL and first-layer interconnect lines 23 to 26 of a peripheral circuit which are in contact with at least an underlying silicon oxide film 28 are formed of a W film, the bit lines BL and the interconnect lines 23 to 26 being arranged below the information storing capacitive element C, whereby the adhesion at the interface between the bit lines BL and the interconnect lines 23 to 26 and the silicon oxide film is improved in terms of high-temperature heat treatment to be performed when the capacitive insulating film is being formed.
摘要翻译：在具有电容器的位线结构的DRAM中，信息存储电容元件C的电容绝缘膜由诸如Ta 2 O 5（氧化钽）膜46的高电介质材料形成，位线BL和第一 - 与W膜形成的与外部电路至少底层的氧化硅膜28接触的层间布线23〜26，位线BL和布线23〜26配置在信息存储电容元件C的下方从而在形成电容绝缘膜时进行的高温热处理方面提高了位线BL与布线23〜26之间界面处的粘附性和氧化硅膜。

6. 发明授权

US06258649B1 Semiconductor integrated circuit device and method of manufacturing the same 有权
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US06258649B1
公开(公告)日：2001-07-10
申请号：US09389231
申请日：1999-09-03
申请人： Yoshitaka Nakamura , Masayoshi Hirasawa , Isamu Asano , Tsuyoshi Tamaru , Satoru Yamada , Keizo Kawakita , Toshihiro Sekiguchi , Yoshitaka Tadaki , Takuya Fukuda
发明人： Yoshitaka Nakamura , Masayoshi Hirasawa , Isamu Asano , Tsuyoshi Tamaru , Satoru Yamada , Keizo Kawakita , Toshihiro Sekiguchi , Yoshitaka Tadaki , Takuya Fukuda
IPC分类号： H01L218234
CPC分类号： H01L27/10894 , H01L21/28518 , H01L21/31612 , H01L21/76801 , H01L21/76816 , H01L21/76828 , H01L21/76843 , H01L21/76855 , H01L23/53223 , H01L27/10882 , H01L28/40 , H01L2924/0002 , H01L2924/00
摘要： In order to improve connection reliability of a feeding interconnection connected to an electrode of each of the information storage capacitive elements of a DRAM, the formation of a through hole for connecting the information storage capacitive element formed over each memory cell selection MISFET and a feeding interconnection is performed in a process different from that for the formation of a through hole for connecting an interconnection of a second wiring layer in a peripheral circuit, which is formed over the information storage capacitive element and an interconnection corresponding to a first wiring layer.
摘要翻译：为了提高连接到DRAM的每个信息存储电容元件的电极的馈电互连的连接可靠性，形成用于连接在每个存储单元选择MISFET上形成的信息存储电容元件的通孔和馈电互连在与形成用于连接在信息存储电容元件上形成的外围电路中的第二布线层的互连的通孔和形成用于连接对应于第一布线层的互连的通孔中。

7. 发明授权

US5937290A Method of manufacturing semiconductor integrated circuit devices using phase shifting mask 失效
标题翻译：使用相移掩模制造半导体集成电路器件的方法
公开(公告)号：US5937290A
公开(公告)日：1999-08-10
申请号：US862992
申请日：1997-05-27
申请人： Toshihiro Sekiguchi , Yoshitaka Tadaki , Keizo Kawakita , Katsuo Yuhara , Kazuhiko Saito , Shinya Nishio , Michio Tanaka , Michio Nishimura , Toshiyuki Kaeriyama , Songsu Cho
发明人： Toshihiro Sekiguchi , Yoshitaka Tadaki , Keizo Kawakita , Katsuo Yuhara , Kazuhiko Saito , Shinya Nishio , Michio Tanaka , Michio Nishimura , Toshiyuki Kaeriyama , Songsu Cho
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/10852 , Y10S438/942
摘要： In an embodiment of a method of manufacturing semiconductor integrated circuit devices according to the present invention, word lines are provided in a straight form, which serve as gate electrodes of two selecting MOSFETs formed symmetrical about a center portion of an active region surrounded by a LOCOS oxide film on a semiconductor substrate, and bit lines have straight segments and protruding segments. Each protruding segment is formed to protrude from the bit line and is connected through a first contact hole to a first semiconductor region formed at the center portion of the active region. The straight line segments and the protruding segments are formed separately by two separate exposure steps.
摘要翻译：在根据本发明的制造半导体集成电路器件的方法的实施例中，字线被提供成直线形式，其用作两个选择MOSFET的栅电极，所述选择MOSFET形成为由LOCOS包围的有源区域的中心部分对称地形成半导体衬底上的氧化膜，位线具有直段和突出段。每个突出部分形成为从位线突出，并且通过第一接触孔连接到形成在有源区域的中心部分处的第一半导体区域。直线段和突出段通过两个单独的曝光步骤分别形成。

8. 发明授权

US5629898A Dynamic memory device, a memory module, and a method of refreshing a dynamic memory device 失效
标题翻译：动态存储器件，存储器模块和刷新动态存储器件的方法
公开(公告)号：US5629898A
公开(公告)日：1997-05-13
申请号：US607977
申请日：1996-02-29
申请人： Youji Idei , Katsuhiro Shimohigashi , Masakazu Aoki , Hiromasa Noda , Katsuyuki Sato , Hidetoshi Iwai , Makoto Saeki , Jun Murata , Yoshitaka Tadaki , Toshihiro Sekiguchi , Osamu Tsuchiya
发明人： Youji Idei , Katsuhiro Shimohigashi , Masakazu Aoki , Hiromasa Noda , Katsuyuki Sato , Hidetoshi Iwai , Makoto Saeki , Jun Murata , Yoshitaka Tadaki , Toshihiro Sekiguchi , Osamu Tsuchiya
IPC分类号： G11C11/406 , G11C11/407 , G11C7/00
CPC分类号： G11C11/406 , G11C2211/4016 , G11C2211/4061
摘要： A period pulse corresponding to the shortest information retention time of those of dynamic memory cells is counted to form a refresh address to be assigned to a plurality of word lines. A carry signal outputted from the refresh address counter is divided by a divider. For each of said plurality of word lines assigned with the refresh address, one of a short period corresponding to an output pulse of a timer or a long period corresponding to the divided pulse from the divider is stored in a storage circuit as refresh time setting information. A memory cell refresh operation to be performed by the refresh address is made valid or invalid for each word line according to the refresh time setting information stored in the storage circuit and the refresh time setting information itself is made invalid by the output pulse of the divider.
摘要翻译：对与动态存储单元的最短信息保持时间对应的周期脉冲进行计数，以形成分配给多个字线的刷新地址。从刷新地址计数器输出的进位信号由分频器分频。对于分配有刷新地址的所述多个字线中的每一个，对应于定时器的输出脉冲的短周期中的一个或与来自分频器的分频脉冲相对应的长周期中的一个作为刷新时间设置信息被存储在存储电路中。根据存储在存储电路中的刷新时间设定信息，由刷新地址执行的存储器单元刷新动作对每个字线进行有效或无效，并且刷新时间设定信息本身被分频器的输出脉冲无效。

9. 发明授权

US5578849A Semiconductor integrated circuit device including a memory device having memory cells with increased information storage capacitance 失效
标题翻译：半导体集成电路器件包括具有增加的信息存储电容的存储单元的存储器件
公开(公告)号：US5578849A
公开(公告)日：1996-11-26
申请号：US341966
申请日：1994-11-16
申请人： Yoshitaka Tadaki , Jun Murata , Toshihiro Sekiguchi , Hideo Aoki , Keizo Kawakita , Hiroyuki Uchiyama , Michio Nishimura , Michio Tanaka , Yuji Ezaki , Kazuhiko Saitoh , Katsuo Yuhara , Songsu Cho
发明人： Yoshitaka Tadaki , Jun Murata , Toshihiro Sekiguchi , Hideo Aoki , Keizo Kawakita , Hiroyuki Uchiyama , Michio Nishimura , Michio Tanaka , Yuji Ezaki , Kazuhiko Saitoh , Katsuo Yuhara , Songsu Cho
IPC分类号： H01L21/3205 , H01L21/8242 , H01L23/52 , H01L27/10 , H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/10852 , H01L27/10817 , H01L2924/0002
摘要： A memory device has a semiconductor substrate, and memory cells provided at intersections between word line conductors and bit line conductors. Each memory cell has a switching transistor and an information storage capacitor. Adjacent two memory cells for each bit line conductor form a memory cell pair unit structure, in which first semiconductor regions of the transistors of the adjacent two memory cells are united at their boundary into a single region and are connected to one of the bit line conductors via a bit line connection conductor, the gate electrodes of the transistors of the adjacent two memory cells are connected to word line conductors adjacent to each other, respectively, the second semiconductor regions of the transistors of the adjacent two memory cells are connected to the respective information storage capacitors. A series of memory cell pair unit structures formed under one bit line conductor is positionally shifted with respect to a series of memory cell pair unit structures formed under adjacent first and second bit line conductors on opposite sides of the one bit line conductor, respectively, such that a second information storage capacitor of a memory cell pair unit structure formed under the adjacent first bit line conductor and a first information storage capacitor of a memory cell pair unit structure formed under the adjacent second bit line conductor are located adjacent to a bit line connection conductor of a memory cell pair unit structure formed under the one bit line conductor.
摘要翻译：存储器件具有半导体衬底和设置在字线导体和位线导体之间的交叉点处的存储单元。每个存储单元具有开关晶体管和信息存储电容器。每个位线导体的相邻的两个存储单元形成存储单元对单元结构，其中相邻两个存储单元的晶体管的第一半导体区域在其边界处被结合成单个区域并连接到位线导体之一通过位线连接导体，相邻的两个存储单元的晶体管的栅电极分别连接到彼此相邻的字线导体，相邻两个存储单元的晶体管的第二半导体区域连接到相应的两个存储单元的晶体管的第二半导体区域信息存储电容器。形成在一个位线导体下方的一系列存储单元对单元结构分别相对于位于一个位线导体的相对侧上相邻的第一和第二位线导体下方的一系列存储单元对单元结构位移地移位，形成在相邻的第一位线导体下方的存储单元对单元结构的第二信息存储电容器和形成在相邻的第二位线导体下方的存储单元对单元结构的第一信息存储电容器位于与位线连接形成在一个位线导体下的存储单元对单元结构的导体。

10. 发明授权

US5504029A Method of producing semiconductor integrated circuit device having memory cell and peripheral circuit MISFETs 失效
标题翻译：具有存储单元和外围电路MISFET的半导体集成电路器件的制造方法
公开(公告)号：US5504029A
公开(公告)日：1996-04-02
申请号：US254562
申请日：1994-06-06
申请人： Jun Murata , Yoshitaka Tadaki , Isamu Asano , Mitsuaki Horiuchi , Jun Sugiura , Hiroko Kaneko , Shinji Shimizu , Atsushi Hiraiwa , Hidetsugu Ogishi , Masakazu Sagawa , Masami Ozawa , Toshihiro Sekiguchi
发明人： Jun Murata , Yoshitaka Tadaki , Isamu Asano , Mitsuaki Horiuchi , Jun Sugiura , Hiroko Kaneko , Shinji Shimizu , Atsushi Hiraiwa , Hidetsugu Ogishi , Masakazu Sagawa , Masami Ozawa , Toshihiro Sekiguchi
IPC分类号： H01L27/10 , H01L21/8242 , H01L27/105 , H01L27/108 , H01L21/70 , H01L27/00
CPC分类号： H01L27/105 , H01L27/10808
摘要： A semiconductor integrated circuit device having a switching MISFET, and a capacitor element formed over the semiconductor substrate, is disclosed. The impurity concentration of the semiconductor region of the switching MISFET to which the capacitor element is connected is less than the impurity concentration of semiconductor regions of MISFETs of peripheral circuitry. The Y-select signal line overlaps the lower electrode layer of the capacitor element. A potential barrier layer, provided at least under the semiconductor region of the switching MISFET to which the capacitor element is connected, is formed by diffusion of an impurity for a channel stopper region. The dielectric film of the capacitor element is co-extensive with the capacitor electrode layer over it. The capacitor dielectric film is a silicon nitride film having a silicon oxide layer thereon, the silicon oxide layer being formed by oxidizing a surface layer of the silicon nitride under high pressure. An aluminum wiring layer and a protective (and/or barrier) layer are formed by sputtering in the same vacuum sputtering chamber without breaking the vacuum between forming the layers; and a refractory metal, or a refractory metal silicide QSi.sub.x, where Q is a refractory metal and x is between 0 and 2, is used as a protective layer, for an aluminum wiring containing an added element (e.g., Cu) to prevent migration.
摘要翻译：公开了一种具有开关MISFET的半导体集成电路器件和形成在半导体衬底上的电容器元件。电容器元件连接的开关MISFET的半导体区域的杂质浓度小于外围电路的MISFET的半导体区域的杂质浓度。 Y选择信号线与电容器元件的下电极层重叠。至少在与电容器元件连接的开关MISFET的半导体区域下方设置的势垒层通过用于沟道阻挡区域的杂质的扩散而形成。电容器元件的电介质膜与其上的电容器电极层共同扩展。电容器电介质膜是其上具有氧化硅层的氮化硅膜，氧化硅层通过在高压下氧化氮化硅的表面层而形成。通过溅射在相同的真空溅射室中形成铝布线层和保护（和/或阻挡层），而不破坏形成层之间的真空; 和难熔金属或难熔金属硅化物QSix，其中Q是难熔金属，x在0和2之间，用作含有添加元素（例如Cu）以防止迁移的铝布线的保护层。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式