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    • 9. 发明授权
    • Semiconductor integrated circuit device including a memory device having
memory cells with increased information storage capacitance
    • 半导体集成电路器件包括具有增加的信息存储电容的存储单元的存储器件
    • US5578849A
    • 1996-11-26
    • US341966
    • 1994-11-16
    • Yoshitaka TadakiJun MurataToshihiro SekiguchiHideo AokiKeizo KawakitaHiroyuki UchiyamaMichio NishimuraMichio TanakaYuji EzakiKazuhiko SaitohKatsuo YuharaSongsu Cho
    • Yoshitaka TadakiJun MurataToshihiro SekiguchiHideo AokiKeizo KawakitaHiroyuki UchiyamaMichio NishimuraMichio TanakaYuji EzakiKazuhiko SaitohKatsuo YuharaSongsu Cho
    • H01L21/3205H01L21/8242H01L23/52H01L27/10H01L27/108H01L29/76H01L29/94H01L31/119
    • H01L27/10852H01L27/10817H01L2924/0002
    • A memory device has a semiconductor substrate, and memory cells provided at intersections between word line conductors and bit line conductors. Each memory cell has a switching transistor and an information storage capacitor. Adjacent two memory cells for each bit line conductor form a memory cell pair unit structure, in which first semiconductor regions of the transistors of the adjacent two memory cells are united at their boundary into a single region and are connected to one of the bit line conductors via a bit line connection conductor, the gate electrodes of the transistors of the adjacent two memory cells are connected to word line conductors adjacent to each other, respectively, the second semiconductor regions of the transistors of the adjacent two memory cells are connected to the respective information storage capacitors. A series of memory cell pair unit structures formed under one bit line conductor is positionally shifted with respect to a series of memory cell pair unit structures formed under adjacent first and second bit line conductors on opposite sides of the one bit line conductor, respectively, such that a second information storage capacitor of a memory cell pair unit structure formed under the adjacent first bit line conductor and a first information storage capacitor of a memory cell pair unit structure formed under the adjacent second bit line conductor are located adjacent to a bit line connection conductor of a memory cell pair unit structure formed under the one bit line conductor.
    • 存储器件具有半导体衬底和设置在字线导体和位线导体之间的交叉点处的存储单元。 每个存储单元具有开关晶体管和信息存储电容器。 每个位线导体的相邻的两个存储单元形成存储单元对单元结构,其中相邻两个存储单元的晶体管的第一半导体区域在其边界处被结合成单个区域并连接到位线导体之一 通过位线连接导体,相邻的两个存储单元的晶体管的栅电极分别连接到彼此相邻的字线导体,相邻两个存储单元的晶体管的第二半导体区域连接到相应的两个存储单元的晶体管的第二半导体区域 信息存储电容器。 形成在一个位线导体下方的一系列存储单元对单元结构分别相对于位于一个位线导体的相对侧上相邻的第一和第二位线导体下方的一系列存储单元对单元结构位移地移位, 形成在相邻的第一位线导体下方的存储单元对单元结构的第二信息存储电容器和形成在相邻的第二位线导体下方的存储单元对单元结构的第一信息存储电容器位于与位线连接 形成在一个位线导体下的存储单元对单元结构的导体。