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1. 发明授权

US06072207A Process for fabricating layered superlattice materials and making electronic devices including same 失效
标题翻译：用于制造分层超晶格材料并制造包括其的电子器件的方法
公开(公告)号：US06072207A
公开(公告)日：2000-06-06
申请号：US405953
申请日：1995-03-17
申请人： Hiroyuki Yoshimori , Carlos A. Paz De Araujo , Takeshi Ito , Michael C. Scott , Larry D. McMillan
发明人： Hiroyuki Yoshimori , Carlos A. Paz De Araujo , Takeshi Ito , Michael C. Scott , Larry D. McMillan
IPC分类号： H01L21/8247 , B05D1/00 , B05D3/04 , B05D7/24 , C23C16/44 , C23C16/448 , C23C16/455 , C23C16/46 , C23C16/48 , C23C16/52 , C23C18/12 , C23C26/02 , C30B7/00 , H01C7/10 , H01L21/02 , H01L21/314 , H01L21/316 , H01L21/8242 , H01L27/108 , H01L27/115 , H01L29/788 , H01L29/792 , H01L41/24 , H05K3/10 , H01L29/12
CPC分类号： C23C18/1216 , B05D1/00 , B05D1/60 , B05D3/0493 , C23C16/4412 , C23C16/4486 , C23C16/45561 , C23C16/4558 , C23C16/46 , C23C16/482 , C23C16/52 , C23C18/1279 , C23C18/1283 , C23C18/1295 , C23C26/02 , C30B29/68 , C30B7/00 , C30B7/005 , H01C7/1013 , H01L21/314 , H01L21/31691 , H01L27/10805 , H01L27/11502 , H01L28/56 , H01L28/60 , H01L41/318 , H01L28/55 , H01L41/257 , H05K3/105
摘要： A liquid precursor containing a metal is applied to a substrate, RTP baked, and annealed to form a layered superlattice material. Special polyoxyalkylated precursor solutions are designed to optimize polarizability of the corresponding metal oxide materials by adding dopants including stoichiometric excess amounts of bismuth and tantalum. The RTP baking process is especially beneficial in optimizing the polarizability of the resultant metal oxide.
摘要翻译：将含有金属的液体前体施加到基材上，进行RTP烘焙并退火以形成层状超晶格材料。设计特殊的聚氧化烷基化前体溶液通过添加包括化学计量过量的铋和钽的掺杂剂来优化相应的金属氧化物材料的极化率。 RTP烘焙过程对于优化所得金属氧化物的极化率是特别有利的。

2. 发明授权

US5439845A Process for fabricating layered superlattice materials and making electronic devices including same 失效
公开(公告)号：US5439845A
公开(公告)日：1995-08-08
申请号：US350323
申请日：1994-12-05
申请人： Hitoshi Watanabe , Carlos A. Paz De Araujo , Hiroyuki Yoshimori , Michael C. Scott , Takashi Mihara , Joseph D. Cuchiaro , Larry D. McMillan
发明人： Hitoshi Watanabe , Carlos A. Paz De Araujo , Hiroyuki Yoshimori , Michael C. Scott , Takashi Mihara , Joseph D. Cuchiaro , Larry D. McMillan
IPC分类号： B05D1/00 , B05D3/04 , B05D7/24 , C23C16/44 , C23C16/448 , C23C16/455 , C23C16/46 , C23C16/48 , C23C16/52 , C23C18/12 , C23C26/02 , C30B7/00 , H01C7/10 , H01L21/02 , H01L21/314 , H01L21/316 , H01L27/108 , H01L27/115 , H01L41/24 , H05K3/10 , H01L29/15
CPC分类号： B05D1/00 , B05D1/60 , B05D3/0493 , C23C16/4412 , C23C16/4486 , C23C16/45561 , C23C16/4558 , C23C16/46 , C23C16/482 , C23C16/52 , C23C18/1216 , C23C18/1225 , C23C18/1279 , C23C18/1283 , C23C18/1295 , C23C26/02 , C30B29/68 , C30B7/00 , C30B7/005 , H01C7/1013 , H01L21/314 , H01L21/31691 , H01L27/10805 , H01L27/11502 , H01L27/11507 , H01L28/56 , H01L28/60 , H01L41/317 , H01L28/55 , H05K3/105
摘要： A liquid precursor containing a metal is applied to a substrate, RTP baked, and annealed to form a layered superlattice material. Prebaking the substrate and oxygen in the RTP and anneal is essential, except for high bismuth content precursors. Excess bismuth between 110% and 140% of stoichiometry and RTP temperature of 725.degree. C. is optimum. The film is formed in two layers, the first of which uses a stoichiometric precursor and the second of which uses an excess bismuth precursor. The electronic properties are so regularly dependent on process parameters and material composition, and such a wide variety of materials are possible, that electronic devices can be designed by selecting from a continuous record of the values of one or more electronic properties as a continuous function of the process parameters and material composition, and utilizing the selected process and material composition to make a device.

3. 发明授权

US5434102A Process for fabricating layered superlattice materials and making electronic devices including same 失效
标题翻译：用于制造分层超晶格材料并制造包括其的电子器件的方法
公开(公告)号：US5434102A
公开(公告)日：1995-07-18
申请号：US65656
申请日：1993-05-21
申请人： Hitoshi Watanabe , Carlos A. Paz De Araujo , Hiroyuki Yoshimori , Michael C. Scott , Takashi Mihara , Joseph D. Cuchiaro , Larry D. McMillan
发明人： Hitoshi Watanabe , Carlos A. Paz De Araujo , Hiroyuki Yoshimori , Michael C. Scott , Takashi Mihara , Joseph D. Cuchiaro , Larry D. McMillan
IPC分类号： B05D1/00 , B05D3/04 , B05D7/24 , C23C16/44 , C23C16/448 , C23C16/455 , C23C16/46 , C23C16/48 , C23C16/52 , C23C18/12 , C23C26/02 , C30B7/00 , H01C7/10 , H01L21/02 , H01L21/314 , H01L21/316 , H01L27/108 , H01L27/115 , H01L41/24 , H05K3/10 , H01L21/385
CPC分类号： B05D1/00 , B05D1/60 , B05D3/0493 , C23C16/4412 , C23C16/4486 , C23C16/45561 , C23C16/4558 , C23C16/46 , C23C16/482 , C23C16/52 , C23C18/1216 , C23C18/1225 , C23C18/1279 , C23C18/1283 , C23C18/1295 , C23C26/02 , C30B29/68 , C30B7/00 , C30B7/005 , H01C7/1013 , H01L21/314 , H01L21/31691 , H01L27/10805 , H01L27/11502 , H01L27/11507 , H01L28/56 , H01L28/60 , H01L41/317 , H01L28/55 , H05K3/105
摘要： A liquid precursor containing a metal is applied to a substrate, RTP baked, and annealed to form a layered superlattice material. Prebaking the substrate and oxygen in the RTP and anneal is essential, except for high bismuth content precursors. Excess bismuth between 110% and 140% of stoichiometry and RTP temperature of 725.degree. C. is optimum. The film is formed in two layers, the first of which uses a stoichiometric precursor and the second of which uses an excess bismuth precursor. The electronic properties are so regularly dependent on process parameters and material composition, and such a wide variety of materials are possible, that electronic devices can be designed by selecting from a continuous record of the values of one or more electronic properties as a continuous function of the process parameters and material composition, and utilizing the selected process and material composition to make a device.
摘要翻译：将含有金属的液体前体施加到基材上，进行RTP烘焙并退火以形成层状超晶格材料。除了高铋含量前体之外，预处理RTP和退火中的底物和氧是至关重要的。化学计量的110％至140％之间的过量铋和725℃的RTP温度是最佳的。该膜形成为两层，其中第一层使用化学计量的前体，其中第二层使用过量的铋前体。电子性质如此定期地取决于工艺参数和材料组成，并且这种各种各样的材料是可能的，可以通过从一个或多个电子性质的值的连续记录中选择电子装置作为连续功能工艺参数和材料组成，并利用所选择的工艺和材料组成制造设备。

4. 发明授权

US5825057A Process for fabricating layered superlattice materials and making electronic devices including same 失效
公开(公告)号：US5825057A
公开(公告)日：1998-10-20
申请号：US349692
申请日：1994-12-05
申请人： Hitoshi Watanabe , Carlos A. Paz De Araujo , Hiroyuki Yoshimori , Michael C. Scott , Takashi Mihara , Joseph D. Cuchiaro , Larry D. McMillan
发明人： Hitoshi Watanabe , Carlos A. Paz De Araujo , Hiroyuki Yoshimori , Michael C. Scott , Takashi Mihara , Joseph D. Cuchiaro , Larry D. McMillan
IPC分类号： B05D1/00 , B05D3/04 , B05D7/24 , C23C16/44 , C23C16/448 , C23C16/455 , C23C16/46 , C23C16/48 , C23C16/52 , C23C18/12 , C23C26/02 , C30B7/00 , H01C7/10 , H01L21/02 , H01L21/314 , H01L21/316 , H01L27/108 , H01L27/115 , H01L41/24 , H05K3/10 , H01L29/76
CPC分类号： B05D1/00 , B05D1/60 , B05D3/0493 , C23C16/4412 , C23C16/4486 , C23C16/45561 , C23C16/4558 , C23C16/46 , C23C16/482 , C23C16/52 , C23C18/1216 , C23C18/1225 , C23C18/1279 , C23C18/1283 , C23C18/1295 , C23C26/02 , C30B29/68 , C30B7/00 , C30B7/005 , H01C7/1013 , H01L21/314 , H01L21/31691 , H01L27/10805 , H01L27/11502 , H01L27/11507 , H01L28/56 , H01L28/60 , H01L41/317 , H01L28/55 , H05K3/105
摘要： A liquid precursor containing a metal is applied to a substrate, RTP baked, and annealed to form a layered superlattice material. Prebaking the substrate and oxygen in the RTP and anneal is essential, except for high bismuth content precursors. Excess bismuth between 110% and 140% of stoichiometry and RTP temperature of 725.degree. C. is optimum. The film is formed in two layers, the first of which uses a stoichiometric precursor and the second of which uses an excess bismuth precursor. The electronic properties are so regularly dependent on process parameters and material composition, and such a wide variety of materials are possible, that electronic devices can be designed by selecting from a continuous record of the values of one or more electronic properties as a continuous function of the process parameters and material composition, and utilizing the selected process and material composition to make a device.

5. 发明授权

US5523964A Ferroelectric non-volatile memory unit 失效
标题翻译：铁电非易失性存储单元
公开(公告)号：US5523964A
公开(公告)日：1996-06-04
申请号：US224241
申请日：1994-04-07
申请人： Larry D. McMillan , Takashi Mihara , Hiroyuki Yoshimori , John W. Gregory , Carlos A. Paz de Araujo
发明人： Larry D. McMillan , Takashi Mihara , Hiroyuki Yoshimori , John W. Gregory , Carlos A. Paz de Araujo
IPC分类号： G11C14/00 , G11C11/22 , H01L21/8242 , H01L21/8247 , H01L27/10 , H01L27/108 , H01L29/788 , H01L29/792
CPC分类号： G11C11/22 , G11C11/223
摘要： An integrated circuit non-volatile, non-destructive read-out memory unit includes a ferroelectric capacitor having first and second electrodes, a capacitance Cf, and an area Af, and a transistor having a gate, a source and a drain forming a gate capacitor having an area Ag and a gate capacitance Cg, a gate overlap b, and a channel depth a, with the capacitor first electrode connected to the gate of the transistor. The ferroelectric material has a dielectric constant .epsilon.f and the gate insulator has a dielectric constant .epsilon.g. A source of a constant reference voltage is connectable to the first electrode. A bit line connects to the second electrode. In one embodiment the first electrode and gate are the same conductive member. In another embodiment the second electrode and the gate are the same conductive member and the first electrode is formed by extensions of the transistor source and drains underlying the gate, with the ferroelectric material between the source and drain extensions and the gate. The memory unit has the parametric relationships: Cf
摘要翻译：集成电路非易失性非破坏性读出存储单元包括具有第一和第二电极的铁电电容器，电容Cf和区域Af，以及具有形成栅极电容器的栅极，源极和漏极的晶体管具有面积Ag和栅极电容Cg，栅极重叠b和沟道深度a，其中电容器第一电极连接到晶体管的栅极。铁电材料具有介电常数εf，栅极绝缘体具有介电常数εg。恒定参考电压的源可连接到第一电极。位线连接到第二电极。在一个实施例中，第一电极和栅极是相同的导电构件。在另一个实施例中，第二电极和栅极是相同的导电构件，并且第一电极由晶体管源的延伸和栅极下方的漏极形成，铁电材料在源极和漏极延伸部分之间以及栅极之间。存储器单元具有参数关系：Cf <5xCg，Af / = 2a和epsilon g> / = epsilon f / 8。

6. 发明授权

US5508954A Method and apparatus for reduced fatigue in ferroelectric memory 失效
标题翻译：铁电存储器疲劳减少的方法和装置
公开(公告)号：US5508954A
公开(公告)日：1996-04-16
申请号：US395582
申请日：1995-02-27
申请人： Takashi Mihara , Hitoshi Watanabe , Hiroyuki Yoshimori , Carlos A. Paz de Araujo , Larry D. McMillan
发明人： Takashi Mihara , Hitoshi Watanabe , Hiroyuki Yoshimori , Carlos A. Paz de Araujo , Larry D. McMillan
IPC分类号： G11C14/00 , G11C11/22 , G11C16/04 , H01L21/8247 , H01L27/10 , H01L29/788 , H01L29/792 , G11C11/12
CPC分类号： G11C11/22 , G11C11/223 , G11C11/2293
摘要： A method and apparatus for programming ferroelectric memory cells which reduces polarizability fatigue effects of switching polarization of the ferroelectric devices associated with the memory cells such as ferroelectric capacitors and transistors. Alteration of the pulse width duty cycle associated with signals used to switch ferroelectric device polarization is shown to reduce polarizability fatigue of the ferroelectric material thereby increasing the useful life of ferroelectric memory cells. Methods and apparatus for producing a signal pulse duty cycle in the range 2-30% is disclosed and shown to improve the useful life of the ferroelectric material.
摘要翻译：一种用于编程铁电存储器单元的方法和装置，其降低与诸如铁电电容器和晶体管之类的存储单元相关联的铁电体器件的开关极化的极化率疲劳效应。显示与用于切换铁电体器件极化的信号相关联的脉冲宽度占空比的改变，以降低铁电材料的极化率疲劳，从而增加铁电存储器单元的使用寿命。公开并示出了用于产生2-30％范围内的信号脉冲占空比的方法和装置，以改善铁电材料的使用寿命。

7. 发明授权

US5541870A Ferroelectric memory and non-volatile memory cell for same 失效
标题翻译：铁电存储器和非易失性存储器单元相同
公开(公告)号：US5541870A
公开(公告)日：1996-07-30
申请号：US330989
申请日：1994-10-28
申请人： Takashi Mihara , Hitoshi Watanabe , Hiroyuki Yoshimori , Carlos A. Paz de Araujo , Larry D. McMillan
发明人： Takashi Mihara , Hitoshi Watanabe , Hiroyuki Yoshimori , Carlos A. Paz de Araujo , Larry D. McMillan
IPC分类号： G11C17/00 , G11C11/22 , G11C16/04 , H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11502 , G11C11/22
摘要： A non-volatile integrated circuit memory in which the memory cell includes a first transistor gate overlying a first channel region, a ferroelectric material overlying a second channel region, and a second transistor gate overlying a third channel region. The channel regions are connected in series, and preferably are contiguous portions of a single semiconducting channel. The firm channel is connected to a plate voltage that is 20% to 50% of the coercive voltage of the ferroelectric material. A sense amplifier is connected to the third channel region via a bit line. The rise of the bit line after reading a logic "1" state of the cell is prevented from disturbing the ferroelectric material by shutting off the third channel before the sense amplifier rises.
摘要翻译：一种非易失性集成电路存储器，其中存储单元包括覆盖第一沟道区的第一晶体管栅极，覆盖第二沟道区的铁电材料和覆盖第三沟道区的第二晶体管栅极。通道区域串联连接，优选地是单个半导体通道的连续部分。固体通道连接到铁电体的矫顽电压的20％至50％的板电压。读出放大器通过位线连接到第三通道区域。读出逻辑“1”状态之后的位线的上升通过在读出放大器上升之前切断第三通道来防止铁电材料的干扰。

8. 发明授权

US5468684A Integrated circuit with layered superlattice material and method of fabricating same 失效
标题翻译：具有分层超晶格材料的集成电路及其制造方法
公开(公告)号：US5468684A
公开(公告)日：1995-11-21
申请号：US65666
申请日：1993-05-21
申请人： Hiroyuki Yoshimori , Hitoshi Watanabe , Carlos A. Paz De Araujo , Shuzo Hiraide , Takashi Mihara , Larry D. McMillan
发明人： Hiroyuki Yoshimori , Hitoshi Watanabe , Carlos A. Paz De Araujo , Shuzo Hiraide , Takashi Mihara , Larry D. McMillan
IPC分类号： C23C16/02 , C23C16/40 , C23C16/56 , C23C18/12 , C30B7/00 , C30B25/02 , H01C7/10 , H01L21/02 , H01L21/314 , H01L21/316 , H01L27/108 , H01L27/115 , H01L21/465
CPC分类号： C23C16/0218 , B05D1/00 , B05D1/60 , B05D3/0493 , C23C16/40 , C23C16/4412 , C23C16/4486 , C23C16/45561 , C23C16/4558 , C23C16/46 , C23C16/482 , C23C16/52 , C23C16/56 , C23C18/1216 , C23C18/1225 , C23C26/02 , C30B25/02 , C30B29/68 , C30B7/00 , H01C7/1013 , H01L21/314 , H01L21/31691 , H01L27/10805 , H01L27/11502 , H01L28/56 , H01L28/60 , H01L41/317 , H01L28/55 , H01L41/187 , H05K3/105
摘要： A method of fabricating a ferroelectric or layered superlattice DRAM compatible with conventional silicon CMOS technology. A MOSFET is formed on a silicon substrate. A thick layer of BPSG followed by a thin SOG layer overlies the MOSFET. A capacitor is formed by depositing a layer of platinum, annealing, depositing an intermediate layer comprising a ferroelectric or layered superlattice material, annealing, depositing a second layer of platinum, then patterning the capacitor. Another SOG layer is deposited, contact holes to the MOSFET and capacitor are partially opened, the SOG is annealed, the contact holes are completely opened, and a Pt/Ti/PtSi wiring layer is deposited.
摘要翻译：制造与常规硅CMOS技术兼容的铁电或分层超晶格DRAM的方法。在硅衬底上形成MOSFET。厚层的BPSG后面是薄的SOG层覆盖在MOSFET上。通过沉积铂层，退火，沉积包含铁电或层状超晶格材料的中间层，退火，沉积第二层铂，然后构图电容器，形成电容器。沉积另一个SOG层，MOSFET和电容器的接触孔部分打开，SOG退火，接触孔完全打开，并沉积Pt / Ti / PtSi布线层。

9. 发明授权

US5719416A Integrated circuit with layered superlattice material compound 失效
标题翻译：集成电路与层状超晶格材料复合
公开(公告)号：US5719416A
公开(公告)日：1998-02-17
申请号：US276805
申请日：1994-07-18
申请人： Hiroyuki Yoshimori , Hitoshi Watanabe , Carlos A. Paz De Araujo , Shuzo Hiraide , Takashi Mihara , Larry D. McMillan
发明人： Hiroyuki Yoshimori , Hitoshi Watanabe , Carlos A. Paz De Araujo , Shuzo Hiraide , Takashi Mihara , Larry D. McMillan
IPC分类号： C23C18/12 , C30B7/00 , H01L21/02 , H01L21/314 , H01L21/316 , H01L27/108 , H01L27/115
CPC分类号： H01L27/11502 , C23C16/45561 , C30B29/68 , C30B7/00 , H01L21/31691 , H01L27/10805 , H01L28/56 , H01L28/60 , H01L28/55
摘要： A method of fabricating a ferroelectric or layered superlattice DRAM compatible with conventional silicon CMOS technology. A MOSFET is formed on a silicon substrate. A thick layer of BPSG followed by a thin SOG layer overlies the MOSFET. A capacitor is formed by depositing a layer of platinum, annealing, depositing an intermediate layer comprising a ferroelectric or layer superlattice material, annealing, depositing a second layer of platinum, then patterning the capacitor. Another SOG layer is deposited, contact holes to the MOSFET and capacitor are partially opened, the SOG is annealed, the contact holes are completely opened, and a Pt/Ti/PtSi wiring layer is deposited.
摘要翻译：制造与常规硅CMOS技术兼容的铁电或分层超晶格DRAM的方法。在硅衬底上形成MOSFET。厚层的BPSG后面是薄的SOG层覆盖在MOSFET上。通过沉积铂层，退火，沉积包含铁电体或层超晶格材料的中间层，退火，沉积第二层铂，然后构图电容器，形成电容器。沉积另一个SOG层，MOSFET和电容器的接触孔部分打开，SOG退火，接触孔完全打开，并沉积Pt / Ti / PtSi布线层。

10. 发明授权

US5559733A Memory with ferroelectric capacitor connectable to transistor gate 失效
标题翻译：具有可连接到晶体管栅极的铁电电容器的存储器
公开(公告)号：US5559733A
公开(公告)日：1996-09-24
申请号：US482765
申请日：1995-06-07
申请人： Larry D. McMillan , Takashi Mihara , Hiroyuki Yoshimori , John W. Gregory , Carlos A. Paz de Araujo
发明人： Larry D. McMillan , Takashi Mihara , Hiroyuki Yoshimori , John W. Gregory , Carlos A. Paz de Araujo
IPC分类号： G11C14/00 , G11C11/22 , H01L21/8242 , H01L21/8247 , H01L27/10 , H01L27/108 , H01L29/788 , H01L29/792
CPC分类号： G11C11/22 , G11C11/223
摘要： A ferroelectric memory includes a constant voltage source, a capacitor having first and second electrodes, and a transistor having a gate. A switch alternately connects the gate of the transistor to the first electrode and the constant voltage source. In another embodiment, there are two ferroelectric transistors, and the first electrode of each capacitor is connected both to the gate of the transistor and to a voltage source external of the memory.
摘要翻译：铁电存储器包括恒压源，具有第一和第二电极的电容器和具有栅极的晶体管。开关将晶体管的栅极交替地连接到第一电极和恒定电压源。在另一实施例中，存在两个铁电晶体管，并且每个电容器的第一电极都连接到晶体管的栅极和存储器外部的电压源。

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