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    • 5. 发明授权
    • Multiprocessor system
    • 多处理器系统
    • US09317287B2
    • 2016-04-19
    • US14232389
    • 2012-06-06
    • Hiroyuki Morishita
    • Hiroyuki Morishita
    • G06F9/38G06F9/30G06F11/36G06F9/00
    • G06F9/30145G06F9/30185G06F9/3836G06F9/3877G06F11/362
    • To provide a multi-processor system that efficiently debugs operations of one processor and operations of another processor. The multiprocessor system has a first processor and a second processor that executes processing by receiving notification from the first processor. The first processor: sequentially specifies instructions to be executed from an instruction queue; sends a notification based on a processing request instruction to the second processor when an instruction that is specified is the processing request instruction; executes the instruction that is specified when the instruction that is specified is not the processing request instruction; and determines whether or not a debug mode is set. When the first processor determines that the debug mode is set, the first processor stops specifying instructions after specifying the processing request instruction, and, after sending the notification, resumes specifying instructions after detecting that the second processor has completed processing corresponding to the notification.
    • 提供有效调试一个处理器的操作和另一个处理器的操作的多处理器系统。 多处理器系统具有通过从第一处理器接收通知来执行处理的第一处理器和第二处理器。 第一处理器:从指令队列中顺序指定要执行的指令; 当指定的指令是处理请求指令时,基于处理请求指令向第二处理器发送通知; 当指定的指令不是处理请求指令时执行指定的指令; 并确定是否设置了调试模式。 当第一处理器确定调试模式被设置时,第一处理器在指定处理请求指令之后停止指定指令,并且在发送通知之后,在检测到第二处理器已经完成与通知相对应的处理之后恢复指定指令。
    • 6. 发明授权
    • Transposition operation device, integrated circuit for the same, and transposition method
    • 换位操作装置,集成电路相同,换位方式
    • US09201899B2
    • 2015-12-01
    • US13824865
    • 2012-09-11
    • Takashi NishimuraHiroyuki Morishita
    • Takashi NishimuraHiroyuki Morishita
    • G06F17/30G06F9/30
    • G06F17/30244G06F9/30032G06F9/30036G06F9/30109
    • A transposition operation device includes: a register group storing a matrix of data such that elements are readable one at a time; an output data rearrangement unit rearranging elements in each row of the matrix so that elements in a same column of the matrix are in different columns of the matrix after rearrangement; a register access unit writing the matrix after rearrangement to the register group and reading the elements in the same column by using column position information indicating positions in the register group at which the elements in the same column are stored; an input data rearrangement unit rearranging the read elements; an operation unit performing an operation on the rearranged elements; and a transposition control unit generating rearrangement information and the column position information to control rearrangement, and performs transposition at high speed by performing rearrangement at the time of storing/reading data in/from the register group.
    • 移位操作装置包括:存储数据矩阵的寄存器组,使得元素一次可读; 输出数据重排单元重新排列矩阵的每行中的元素,使得矩阵的同一列中的元素在重新排列之后处于矩阵的不同列中; 寄存器访问单元,通过使用指示存储同一列中的元素的寄存器组中的位置的列位置信息,将重排后的矩阵写入寄存器组并读取同一列中的元素; 输入数据重排单元重新排列读取的元件; 对重新排列的元件执行操作的操作单元; 以及转置控制单元,其生成重排信息和列位置信息以控制重排,并且通过在从寄存器组中存储/读取数据时执行重排来高速执行转置。
    • 7. 发明授权
    • Processor capable of reconfiguring a logical circuit
    • 能够重新配置逻辑电路的处理器
    • US07926055B2
    • 2011-04-12
    • US11574359
    • 2006-04-12
    • Hiroyuki MorishitaTakashi HashimotoTokuzo Kiyohara
    • Hiroyuki MorishitaTakashi HashimotoTokuzo Kiyohara
    • G06F9/46
    • G06F15/7867G06F9/30076G06F9/3851G06F9/3867G06F9/3885G06F9/3897
    • The present invention provides a processor that cyclically executes a plurality of threads in accordance with an execution time allocated to each of the threads, comprising a reconfigurable integrated circuit. The processor stores circuit configuration information sets respectively corresponding to the plurality of threads, reconfigures a part of the integrated circuit based on the circuit configuration information sets, and sequentially executes each thread using the integrated circuit that has been reconfigured based on one of the configuration information sets that corresponds to the thread. While executing a given thread, the processor selects a thread to be executed next, and reconfigures a part of the integrated circuit where is not currently used for execution of the given thread, based on a circuit configuration information set corresponding to the selected thread.
    • 本发明提供了一种根据分配给每个线程的执行时间循环地执行多个线程的处理器,包括可重构集成电路。 处理器存储分别对应于多个线程的电路配置信息集合,基于电路配置信息集重配置集成电路的一部分,并且使用基于配置信息之一重新配置的集成电路来顺序地执行每个线程 设置对应于线程。 在执行给定的线程的同时,处理器根据与所选择的线程对应的电路配置信息,选择要执行的线程,并重新配置当前不用于执行给定线程的集成电路的一部分。