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1. 发明授权

US07315934B2 Data processor and program for processing a data matrix 有权
标题翻译：用于处理数据矩阵的数据处理器和程序
公开(公告)号：US07315934B2
公开(公告)日：2008-01-01
申请号：US10377328
申请日：2003-02-28
申请人： Hiroyuki Morishita , Atsushi Ito , Satoshi Takashima , Hideshi Nishida , Kozo Kimura , Tokuzo Kiyohara , Akira Miyoshi , Hiroshi Kadota
发明人： Hiroyuki Morishita , Atsushi Ito , Satoshi Takashima , Hideshi Nishida , Kozo Kimura , Tokuzo Kiyohara , Akira Miyoshi , Hiroshi Kadota
IPC分类号： G06F15/76
CPC分类号： G06F9/3012 , G06F9/30036 , G06F9/3824 , G06F9/3885
摘要： A data processor has sixteen processing elements that each include a register file and an arithmetic logic unit. A network unit connects between the register files of the processing elements and the arithmetic logic units of the processing elements. The network unit has a selector for simultaneously performing a plurality of data transfers which are each made from a register file of one processing element to an operation unit of another processing element. With the provision of this selector that can perform such simultaneous data transfers, the processing efficiency of the processing elements can be maintained even if a change occurs in operand assignments and the like.
摘要翻译：数据处理器具有16个处理元件，每个处理元件包括寄存器文件和算术逻辑单元。网络单元连接处理元件的寄存器文件和处理元件的算术逻辑单元。网络单元具有选择器，用于同时执行多个数据传送，每个数据传输由一个处理元件的寄存器文件制成到另一个处理元件的操作单元。通过提供可以执行这种同时数据传输的该选择器，即使在操作数分配等中发生改变，也可以保持处理元件的处理效率。

2. 发明授权

US06829302B2 Pixel calculating device 有权
标题翻译：像素计算装置
公开(公告)号：US06829302B2
公开(公告)日：2004-12-07
申请号：US10019498
申请日：2001-12-20
申请人： Hiroyuki Morishita , Kosuke Yoshioka , Hideshi Nishida , Makoto Hirai , Ryuji Matsuura , Toshiaki Tsuji , Kozo Kimura , Tokuzo Kiyohara
发明人： Hiroyuki Morishita , Kosuke Yoshioka , Hideshi Nishida , Makoto Hirai , Ryuji Matsuura , Toshiaki Tsuji , Kozo Kimura , Tokuzo Kiyohara
IPC分类号： H04N712
CPC分类号： H04N19/80 , G06T3/4007 , G06T3/4023 , G06T5/20 , G06T2200/28
摘要： A pixel calculating device that performs vertical filtering on pixel data in order to reduce frame data in a vertical direction. The pixel calculating device includes a decoding unit 401 for decoding compressed video data to produce frame data, frame memory 402 for storing the frame data, a filtering unit 403 for reducing the frame data in a vertical direction by the vertical filtering to produce a reduced image, buffer memory 404 for storing the reduced image outputted from filtering unit 403, and a control unit 406 for controlling filtering unit 403 based on a decoding state of the video data by decoding unit 401 and a filtering state of the frame data by filtering unit 403, so that overrun and underrun do not occur in filtering unit 403.
摘要翻译：一种对像素数据进行垂直滤波以便在垂直方向上减少帧数据的像素计算装置。像素计算装置包括用于解码压缩视频数据以产生帧数据的解码单元401，用于存储帧数据的帧存储器402，用于通过垂直滤波减少垂直方向上的帧数据以产生缩小图像的滤波单元403 用于存储从滤波单元403输出的缩小图像的缓冲存储器404，以及基于解码单元401的视频数据的解码状态和滤波单元403的帧数据的滤波状态来控制滤波单元403的控制单元406 ，因此在过滤单元403中不会发生溢出和欠载。

3. 发明授权

US06809777B2 Pixel calculating device 有权
标题翻译：像素计算装置
公开(公告)号：US06809777B2
公开(公告)日：2004-10-26
申请号：US10019419
申请日：2001-12-18
申请人： Hiroyuki Oka , Hideshi Nishida , Kosuke Yoshioka , Tokuzo Kiyohara , Makoto Hirai , Kozo Kimura , Ryuji Matsuura , Hiroyuki Morishita , Toshiaki Tsuji
发明人： Hiroyuki Oka , Hideshi Nishida , Kosuke Yoshioka , Tokuzo Kiyohara , Makoto Hirai , Kozo Kimura , Ryuji Matsuura , Hiroyuki Morishita , Toshiaki Tsuji
IPC分类号： H04N964
CPC分类号： H04N19/80 , G06T1/20 , G06T5/20
摘要： A pixel calculating device for performing vertical filtering that includes 16 pixel processing units 1 to 16 and an input buffer group 22 storing 16 pieces of pixel data and filter coefficients. Each of the pixel processing units performs operations using the pixel data and a filter coefficient supplied from input buffer group 22, and then acquires pixel data from an adjacent pixel processing unit. Further operations are performed by each of the pixel processing units using the acquired pixel data and operation results are accumulated. Filtering is carried out through a repetition of this acquiring and accumulation process, the number of taps being determined by the number of repetitions.
摘要翻译：用于执行垂直滤波的像素计算装置，其包括16个像素处理单元1至16以及存储16个像素数据和滤波器系数的输入缓冲器组22。每个像素处理单元使用从输入缓冲器组22提供的像素数据和滤波器系数来执行操作，然后从邻近的像素处理单元获取像素数据。使用所获取的像素数据由每个像素处理单元执行进一步的操作，并且累积运算结果。通过重复该获取和累积过程来进行过滤，抽头的数量由重复次数确定。

4. 发明授权

US07926055B2 Processor capable of reconfiguring a logical circuit 有权
标题翻译：能够重新配置逻辑电路的处理器
公开(公告)号：US07926055B2
公开(公告)日：2011-04-12
申请号：US11574359
申请日：2006-04-12
申请人： Hiroyuki Morishita , Takashi Hashimoto , Tokuzo Kiyohara
发明人： Hiroyuki Morishita , Takashi Hashimoto , Tokuzo Kiyohara
IPC分类号： G06F9/46
CPC分类号： G06F15/7867 , G06F9/30076 , G06F9/3851 , G06F9/3867 , G06F9/3885 , G06F9/3897
摘要： The present invention provides a processor that cyclically executes a plurality of threads in accordance with an execution time allocated to each of the threads, comprising a reconfigurable integrated circuit. The processor stores circuit configuration information sets respectively corresponding to the plurality of threads, reconfigures a part of the integrated circuit based on the circuit configuration information sets, and sequentially executes each thread using the integrated circuit that has been reconfigured based on one of the configuration information sets that corresponds to the thread. While executing a given thread, the processor selects a thread to be executed next, and reconfigures a part of the integrated circuit where is not currently used for execution of the given thread, based on a circuit configuration information set corresponding to the selected thread.
摘要翻译：本发明提供了一种根据分配给每个线程的执行时间循环地执行多个线程的处理器，包括可重构集成电路。处理器存储分别对应于多个线程的电路配置信息集合，基于电路配置信息集重配置集成电路的一部分，并且使用基于配置信息之一重新配置的集成电路来顺序地执行每个线程设置对应于线程。在执行给定的线程的同时，处理器根据与所选择的线程对应的电路配置信息，选择要执行的线程，并重新配置当前不用于执行给定线程的集成电路的一部分。

5. 发明申请

US20070028055A1 Cache memory and cache memory control method 审中-公开
标题翻译：缓存内存和缓存内存控制方式
公开(公告)号：US20070028055A1
公开(公告)日：2007-02-01
申请号：US10571531
申请日：2004-08-23
申请人： Tetsuya Tanaka , Ryuta Nakanishi , Tokuzo Kiyohara , Hiroyuki Morishita , Keishi Chikamura
发明人： Tetsuya Tanaka , Ryuta Nakanishi , Tokuzo Kiyohara , Hiroyuki Morishita , Keishi Chikamura
IPC分类号： G06F12/00
CPC分类号： G06F12/127 , G06F12/124
摘要： A cache memory of the present invention includes: for each cache entry, way 0 to way 3 which hold use flags U indicating whether or not the use flags U have been accessed; and a control unit which: updates, when a cache entry is hit, a use flag U corresponding to the hit cache entry so that the use flag U indicates that the cache entry has been accessed; and reset, in the case where all other use flags in the same set indicates that the cache entries have been accessed herein, the all other use flags so that the use flags indicate that the cache entries have not been accessed; and select a cache entry to be replaced from among the cache entries corresponding to the use flags indicating that the cache entries have not been accessed.
摘要翻译：本发明的高速缓存存储器包括：对于每个高速缓存条目，方式0到路径3，其保持使用标志U，指示是否已经访问了使用标志U; 以及控制单元，其在高速缓存条目被命中时更新与所述命中高速缓存条目对应的使用标志U，使得所述使用标志U指示所述高速缓存条目已经被访问; 并且在同一集合中的所有其他使用标志指示已经在这里访问了高速缓存条目的情况下，复位所有其他使用标志，使得使用标志指示高速缓存条目未被访问; 并且从与指示高速缓存条目未被访问的使用标志相对应的高速缓存条目中选择要替换的高速缓存条目。

6. 发明授权

US07685351B2 External device access apparatus 有权
标题翻译：外部设备接入设备
公开(公告)号：US07685351B2
公开(公告)日：2010-03-23
申请号：US11916319
申请日：2006-06-06
申请人： Takao Kawakami , Masaitsu Nakajima , Tokuzo Kiyohara , Hiroyuki Morishita , Nobuo Higaki , Yousuke Kudo
发明人： Takao Kawakami , Masaitsu Nakajima , Tokuzo Kiyohara , Hiroyuki Morishita , Nobuo Higaki , Yousuke Kudo
IPC分类号： G06F13/00
CPC分类号： G06F13/385
摘要： In response to a write request from a master to write to an external device, a control unit holds a write address and write data from the master in a write address holding unit and in a write data holding unit, respectively, outputs a reception signal to the master, and writes the write data to the external device specified by the write address. When the master holds the read address in the read address holding unit, the control unit reads data from the external device specified by the read address, and holds the read data in the read data holding unit.
摘要翻译：响应于来自主机对外部设备的写入请求，控制单元分别保存写入地址并从写入地址保存单元和写入数据保持单元中写入数据，将接收信号输出到并将写入数据写入由写入地址指定的外部设备。当主机在读取地址保持单元中保持读取地址时，控制单元从读取地址指定的外部设备读取数据，并将读取的数据保存在读取数据保存单元中。

7. 发明申请

US20090037916A1 PROCESSOR 有权
标题翻译：处理器
公开(公告)号：US20090037916A1
公开(公告)日：2009-02-05
申请号：US11574359
申请日：2006-04-12
申请人： Hiroyuki Morishita , Takashi Hashimoto , Tokuzo Kiyohara
发明人： Hiroyuki Morishita , Takashi Hashimoto , Tokuzo Kiyohara
IPC分类号： G06F9/46
CPC分类号： G06F15/7867 , G06F9/30076 , G06F9/3851 , G06F9/3867 , G06F9/3885 , G06F9/3897
摘要： The present invention provides a processor that cyclically executes a plurality of threads in accordance with an execution time allocated to each of the threads, comprising a reconfigurable integrated circuit. The processor stores circuit configuration information sets respectively corresponding to the plurality of threads, reconfigures a part of the integrated circuit based on the circuit configuration information sets, and sequentially executes each thread using the integrated circuit that has been reconfigured based on one of the configuration information sets that corresponds to the thread. While executing a given thread, the processor selects a thread to be executed next, and reconfigures a part of the integrated circuit where is not currently used for execution of the given thread, based on a circuit configuration information set corresponding to the selected thread.
摘要翻译：本发明提供了一种根据分配给每个线程的执行时间循环地执行多个线程的处理器，包括可重构集成电路。处理器存储分别对应于多个线程的电路配置信息集，基于电路配置信息集重配置集成电路的一部分，并且使用基于配置信息之一重新配置的集成电路来顺序地执行每个线程设置对应于线程。在执行给定的线程的同时，处理器根据与所选择的线程对应的电路配置信息，选择要执行的线程，并重新配置当前不用于执行给定线程的集成电路的一部分。

8. 发明授权

US07395410B2 Processor system with an improved instruction decode control unit that controls data transfer between processor and coprocessor 有权
标题翻译：处理器系统具有改进的指令解码控制单元，用于控制处理器和协处理器之间的数据传输
公开(公告)号：US07395410B2
公开(公告)日：2008-07-01
申请号：US11172601
申请日：2005-06-30
申请人： Masaki Maeda , Hiroyuki Morishita , Takeshi Tanaka , Tokuzo Kiyohara
发明人： Masaki Maeda , Hiroyuki Morishita , Takeshi Tanaka , Tokuzo Kiyohara
IPC分类号： G06F15/16
CPC分类号： G06F9/3877 , G06F9/3885
摘要： A processor system includes a main processor having registers and an instruction decode control unit, and a coprocessor. When the main processor performs an operation in accordance with an instruction, the registers store data to be used for the operation and data obtained by the operation, and the control unit sequentially decodes an instruction, and performs a control based on the instruction. When decoding a coprocessor operation instruction to request the coprocessor to perform an operation, which includes operands designating a type of an operation to be performed by the coprocessor, a first register storing data to be used for the operation, and a second register to store data obtained by the operation, the control unit requests the coprocessor to perform the designated type of operation by using a content in the first register, and causes the second register to store a result of the operation.
摘要翻译：处理器系统包括具有寄存器和指令解码控制单元的主处理器以及协处理器。当主处理器根据指令执行操作时，寄存器存储要用于操作的数据和通过操作获得的数据，并且控制单元顺序地解码指令，并且基于该指令进行控制。当解码协处理器操作指令以请求协处理器执行操作时，其包括指定要由协处理器执行的操作的类型的操作数，存储要用于操作的数据的第一寄存器和用于存储数据的第二寄存器通过该操作获得，控制单元通过使用第一寄存器中的内容来请求协处理器执行指定类型的操作，并且使第二寄存器存储操作的结果。

9. 发明申请

US20060010305A1 Processor system that controls data transfer between processor and coprocessor 有权
标题翻译：控制处理器和协处理器之间数据传输的处理器系统
公开(公告)号：US20060010305A1
公开(公告)日：2006-01-12
申请号：US11172601
申请日：2005-06-30
申请人： Masaki Maeda , Hiroyuki Morishita , Takeshi Tanaka , Tokuzo Kiyohara
发明人： Masaki Maeda , Hiroyuki Morishita , Takeshi Tanaka , Tokuzo Kiyohara
IPC分类号： G06F15/00
CPC分类号： G06F9/3877 , G06F9/3885
摘要： A processor system includes a main processor having registers and an instruction decode control unit, and a coprocessor. When the main processor performs an operation in accordance with an instruction, the registers store data to be used for the operation and data obtained by the operation, and the control unit sequentially decodes an instruction, and performs a control based on the instruction. When decoding a coprocessor operation instruction to request the coprocessor to perform an operation, which includes operands designating a type of an operation to be performed by the coprocessor, a first register storing data to be used for the operation, and a second register to store data obtained by the operation, the control unit requests the coprocessor to perform the designated type of operation by using a content in the first register, and causes the second register to store a result of the operation.
摘要翻译：处理器系统包括具有寄存器和指令解码控制单元的主处理器以及协处理器。当主处理器根据指令执行操作时，寄存器存储要用于操作的数据和通过操作获得的数据，并且控制单元顺序地解码指令，并且基于该指令进行控制。当解码协处理器操作指令以请求协处理器执行操作时，其包括指定要由协处理器执行的操作的类型的操作数，存储要用于操作的数据的第一寄存器和用于存储数据的第二寄存器通过该操作获得，控制单元通过使用第一寄存器中的内容来请求协处理器执行指定类型的操作，并且使第二寄存器存储操作的结果。

10. 发明申请

US20090037779A1 EXTERNAL DEVICE ACCESS APPARATUS 有权
标题翻译：外部设备访问设备
公开(公告)号：US20090037779A1
公开(公告)日：2009-02-05
申请号：US11916319
申请日：2006-06-06
申请人： Takao Kawakami , Masaitsu Nakajima , Tokuzo Kiyohara , Hiroyuki Morishita , Nobuo Higaki , Yousuke Kudo
发明人： Takao Kawakami , Masaitsu Nakajima , Tokuzo Kiyohara , Hiroyuki Morishita , Nobuo Higaki , Yousuke Kudo
IPC分类号： G06F12/00 , G06F11/07
CPC分类号： G06F13/385
摘要： In response to a write request from a master to write to an external device, a control unit holds a write address and write data from the master in a write address holding unit and in a write data holding unit, respectively, outputs a reception signal to the master, and writes the write data to the external device specified by the write address. When the master holds the read address in the read address holding unit, the control unit reads data from the external device specified by the read address, and holds the read data in the read data holding unit.
摘要翻译：响应于来自主机对外部设备的写入请求，控制单元分别保存写入地址并从写入地址保存单元和写入数据保持单元中写入数据，将接收信号输出到并将写入数据写入由写入地址指定的外部设备。当主机在读取地址保持单元中保持读取地址时，控制单元从读取地址指定的外部设备读取数据，并将读取的数据保存在读取数据保存单元中。

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