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1. 发明授权

US07685351B2 External device access apparatus 有权
标题翻译：外部设备接入设备
公开(公告)号：US07685351B2
公开(公告)日：2010-03-23
申请号：US11916319
申请日：2006-06-06
申请人： Takao Kawakami , Masaitsu Nakajima , Tokuzo Kiyohara , Hiroyuki Morishita , Nobuo Higaki , Yousuke Kudo
发明人： Takao Kawakami , Masaitsu Nakajima , Tokuzo Kiyohara , Hiroyuki Morishita , Nobuo Higaki , Yousuke Kudo
IPC分类号： G06F13/00
CPC分类号： G06F13/385
摘要： In response to a write request from a master to write to an external device, a control unit holds a write address and write data from the master in a write address holding unit and in a write data holding unit, respectively, outputs a reception signal to the master, and writes the write data to the external device specified by the write address. When the master holds the read address in the read address holding unit, the control unit reads data from the external device specified by the read address, and holds the read data in the read data holding unit.
摘要翻译：响应于来自主机对外部设备的写入请求，控制单元分别保存写入地址并从写入地址保存单元和写入数据保持单元中写入数据，将接收信号输出到并将写入数据写入由写入地址指定的外部设备。当主机在读取地址保持单元中保持读取地址时，控制单元从读取地址指定的外部设备读取数据，并将读取的数据保存在读取数据保存单元中。

2. 发明申请

US20090037779A1 EXTERNAL DEVICE ACCESS APPARATUS 有权
标题翻译：外部设备访问设备
公开(公告)号：US20090037779A1
公开(公告)日：2009-02-05
申请号：US11916319
申请日：2006-06-06
申请人： Takao Kawakami , Masaitsu Nakajima , Tokuzo Kiyohara , Hiroyuki Morishita , Nobuo Higaki , Yousuke Kudo
发明人： Takao Kawakami , Masaitsu Nakajima , Tokuzo Kiyohara , Hiroyuki Morishita , Nobuo Higaki , Yousuke Kudo
IPC分类号： G06F12/00 , G06F11/07
CPC分类号： G06F13/385
摘要： In response to a write request from a master to write to an external device, a control unit holds a write address and write data from the master in a write address holding unit and in a write data holding unit, respectively, outputs a reception signal to the master, and writes the write data to the external device specified by the write address. When the master holds the read address in the read address holding unit, the control unit reads data from the external device specified by the read address, and holds the read data in the read data holding unit.
摘要翻译：响应于来自主机对外部设备的写入请求，控制单元分别保存写入地址并从写入地址保存单元和写入数据保持单元中写入数据，将接收信号输出到并将写入数据写入由写入地址指定的外部设备。当主机在读取地址保持单元中保持读取地址时，控制单元从读取地址指定的外部设备读取数据，并将读取的数据保存在读取数据保存单元中。

3. 发明申请

US20100174884A1 PROCESSOR HAVING RECONFIGURABLE ARITHMETIC ELEMENT 审中-公开
标题翻译：具有可重构算术元素的处理器
公开(公告)号：US20100174884A1
公开(公告)日：2010-07-08
申请号：US12159271
申请日：2006-11-09
申请人： Hiroyuki Morishita , Takao Yamamoto , Masaitsu Nakajima
发明人： Hiroyuki Morishita , Takao Yamamoto , Masaitsu Nakajima
IPC分类号： G06F9/302 , G06F9/30 , G06F15/80 , G06F9/06
CPC分类号： G06F9/3885 , G06F9/30014 , G06F9/30181 , G06F9/3897
摘要： A processor (101) in which a plurality of arithmetic elements executing instructions are embedded includes: fixed function arithmetic elements (121 to 123) each having a circuit configuration that is not dynamically reconfigurable; a reconfigurable arithmetic element (125) having a circuit configuration that is dynamically reconfigurable; and an arithmetic operation control unit (113) which allocates instructions to the fixed function arithmetic elements (121 to 123) and the reconfigurable arithmetic element (125) and issues the allocated instructions to the respective arithmetic elements.
摘要翻译：其中嵌入执行指令的多个运算元件的处理器（101）包括：每个具有不能动态重新配置的电路配置的固定功能运算元件（121至123）具有可动态重新配置的电路配置的可重构算术元件（125）; 以及向所述固定功能运算元件（121〜123）和所述可重构运算元件（125）分配指令的运算控制单元（113），并且将分配的指令发布给各个运算元件。

4. 发明授权

US08141088B2 Multithreaded processor 有权
标题翻译：多线程处理器
公开(公告)号：US08141088B2
公开(公告)日：2012-03-20
申请号：US11936296
申请日：2007-11-07
申请人： Hiroyuki Morishita , Shinji Ozaki , Takao Yamamoto , Masaitsu Nakajima
发明人： Hiroyuki Morishita , Shinji Ozaki , Takao Yamamoto , Masaitsu Nakajima
IPC分类号： G06F9/46 , G06F9/38
CPC分类号： G06F9/3885 , G06F9/3802 , G06F9/3814 , G06F9/3851
摘要： Provided is a multithreaded processor that can accurately estimate processing time necessary for each thread, and a multithreaded processor that simultaneously executes instruction streams, the multithreaded processor including: a computing unit group that executes instructions; an instruction scheduler that groups the instructions into groups for each of the instruction streams, the instructions being included in the each of instruction streams, and each of the groups being made up of instructions among the instructions to be simultaneously issued to the computing units; an instruction buffer which holds the instructions for each of the groups grouped by the instruction scheduler, the instructions being included in the each of instruction streams; and an issued instruction determining unit that reads the instructions for each of the groups from the instruction buffer in each of execution cycles of the multithreaded processor, and that issues the read instructions to the computing unit group.
摘要翻译：提供了一种可以准确地估计每个线程所需的处理时间的多线程处理器，以及同时执行指令流的多线程处理器，所述多线程处理器包括：执行指令的计算单元组; 指令调度器，其将指令分组为每个指令流，每个指令流中包括指令，并且每个组由指令同时发出到计算单元; 指令缓冲器，其保存由指令调度器分组的每个组的指令，所述指令被包括在每个指令流中; 以及发出指令确定单元，其在多线程处理器的每个执行周期中从指令缓冲器读取每个组的指令，并将读取指令发布到计算单元组。

5. 发明申请

US20110307686A1 Method for Instructing a data processor to process data 有权
标题翻译：指示数据处理器处理数据的方法
公开(公告)号：US20110307686A1
公开(公告)日：2011-12-15
申请号：US13153035
申请日：2011-06-03
申请人： Takeshi KISHIDA , Masaitsu Nakajima
发明人： Takeshi KISHIDA , Masaitsu Nakajima
IPC分类号： G06F9/30 , G06F9/312
CPC分类号： G06F9/30149 , G06F9/3013 , G06F9/30138 , G06F9/30145 , G06F9/30167 , G06F9/30181 , G06F9/30189 , G06F9/3822 , G06F9/384 , G06F9/3853
摘要： A data processor which executes instructions described in first and second instruction formats. The first instruction format defines a register-addressing field of a predetermined size, while the second instruction format defines a register-addressing field of a size larger than that of the register-addressing field defined by the first instruction format. The data processor includes: instruction-type identifier, responsive to an instruction, for identifying the received instruction as being described in the first or second instruction format by the instruction itself; a first register file including a plurality of registers; and a second register file also including a plurality of registers, the number of the registers included in the second register file being larger than that of the registers included in the first register file.
摘要翻译：执行以第一和第二指令格式描述的指令的数据处理器。第一指令格式定义了预定大小的寄存器寻址字段，而第二指令格式定义了大于由第一指令格式定义的寄存器寻址字段的大小的寄存器寻址字段。数据处理器包括：指令类型标识符，响应于指令，用于通过指令本身识别接收到的以第一或第二指令格式描述的指令; 包括多个寄存器的第一寄存器堆; 以及还包括多个寄存器的第二寄存器堆，包括在第二寄存器堆中的寄存器的数目大于包含在第一寄存器堆中的寄存器的寄存器数。

6. 发明授权

US07979676B2 Method for instructing a data processor to process data 有权
标题翻译：指示数据处理器处理数据的方法
公开(公告)号：US07979676B2
公开(公告)日：2011-07-12
申请号：US12632532
申请日：2009-12-07
申请人： Takeshi Kishida , Masaitsu Nakajima
发明人： Takeshi Kishida , Masaitsu Nakajima
IPC分类号： G06F9/30
CPC分类号： G06F9/30149 , G06F9/3013 , G06F9/30138 , G06F9/30145 , G06F9/30167 , G06F9/30181 , G06F9/30189 , G06F9/3822 , G06F9/384 , G06F9/3853
摘要： A data processor which executes instructions described in first and second instruction formats. The first instruction format defines a register-addressing field of a predetermined size, while the second instruction format defines a register-addressing field of a size larger than that of the register-addressing field defined by the first instruction format. The data processor includes: instruction-type identifier, responsive to an instruction, for identifying the received instruction as being described in the first or second instruction format by the instruction itself; a first register file including a plurality of registers; and a second register file also including a plurality of registers, the number of the registers included in the second register file being larger than that of the registers included in the first register file.
摘要翻译：执行以第一和第二指令格式描述的指令的数据处理器。第一指令格式定义了预定大小的寄存器寻址字段，而第二指令格式定义了大于由第一指令格式定义的寄存器寻址字段的大小的寄存器寻址字段。数据处理器包括：指令类型标识符，响应于指令，用于通过指令本身识别接收到的以第一或第二指令格式描述的指令; 包括多个寄存器的第一寄存器堆; 以及还包括多个寄存器的第二寄存器堆，包括在第二寄存器堆中的寄存器的数目大于包含在第一寄存器堆中的寄存器的寄存器数。

7. 发明授权

US07970998B2 Parallel caches operating in exclusive address ranges 有权
标题翻译：在独占地址范围内运行的并行缓存
公开(公告)号：US07970998B2
公开(公告)日：2011-06-28
申请号：US11910831
申请日：2006-03-17
申请人： Takao Yamamoto , Tetsuya Tanaka , Ryuta Nakanishi , Masaitsu Nakajima , Keisuke Kaneko , Hazuki Okabayashi
发明人： Takao Yamamoto , Tetsuya Tanaka , Ryuta Nakanishi , Masaitsu Nakajima , Keisuke Kaneko , Hazuki Okabayashi
IPC分类号： G06F12/08
CPC分类号： G06F12/0875 , G06F12/0848 , G06F12/0888
摘要： A cache memory of the present invention includes a second cache memory that is operated in parallel with a first cache memory, a judgment unit which, when a cache miss occurs in both of the first cache memory and the second cache memory, makes a true or false judgment relating to an attribute of data for which memory access resulted in the cache miss, and a controlling unit which stores memory data in the second cache memory when a judgment of true is made, and stores the memory data in the first cache memory when a judgment of false is made.
摘要翻译：本发明的高速缓存存储器包括与第一高速缓存存储器并行操作的第二高速缓冲存储器，当在第一高速缓冲存储器和第二高速缓冲存储器两者中发生高速缓存未命中时，判断单元都是真的或关于存储器访问导致高速缓存未命中的数据的属性的错误判断，以及当进行判断时将存储器数据存储在第二高速缓冲存储器中的控制单元，并且将存储器数据存储在第一高速缓冲存储器中做出了错误的判断。

8. 发明申请

US20070088896A1 Arithmetic processing unit and method for operating cache 审中-公开
标题翻译：用于操作缓存的算术处理单元和方法
公开(公告)号：US20070088896A1
公开(公告)日：2007-04-19
申请号：US11510670
申请日：2006-08-28
申请人： Masahide Kakeda , Masaitsu Nakajima , Takao Yamamoto , Shinji Ozaki
发明人： Masahide Kakeda , Masaitsu Nakajima , Takao Yamamoto , Shinji Ozaki
IPC分类号： G06F12/08 , G06F13/00
CPC分类号： G06F12/0893 , G06F12/0831
摘要： A cache access transmission means outputs an access address, obtained from a CPU by way of a local cache access address input means, to a shared address bus via a remote cache access address output means. A cache access control means accesses a cache memory by using the access address obtained from the shared address bus by way of a remote cache access address input means. That is, an access address output from a CPU of a first processor is output from the cache access transmission means and received by the cache access control means so as to be used in accessing a cache memory in a second processor.
摘要翻译：高速缓存存取传输装置经由远程高速缓存存取地址输出装置将通过本地高速缓存存取地址输入装置从CPU获得的访问地址输出到共享地址总线。高速缓存访问控制装置通过使用通过远程高速缓存访问地址输入装置从共享地址总线获得的访问地址来访问高速缓冲存储器。也就是说，从高速缓存访问传输装置输出从第一处理器的CPU输出的访问地址，并由高速缓存访问控制装置接收，以便用于访问第二处理器中的高速缓冲存储器。

9. 发明授权

US5946223A Subtraction/shift-type dividing device producing a 2-bit partial quotient in each cycle 失效
标题翻译：在每个周期中产生2位部分商的减法/移位分割装置
公开(公告)号：US5946223A
公开(公告)日：1999-08-31
申请号：US767083
申请日：1996-12-06
申请人： Masaitsu Nakajima
发明人： Masaitsu Nakajima
IPC分类号： G06F7/52 , G06F7/535
CPC分类号： G06F7/535
摘要： A first subtracting means subtracts divisor data from dividend data or partial remainder data. In parallel with the subtraction of the first subtracting means, a comparing means performs a comparison between the highest-3-bit data of the dividend or partial remainder data and that of the divisor data. A first selecting means supplies, after shifting leftward by one bit, the dividend data or partial remainder data, or output data of the first subtracting means to a second subtracting means in accordance with a comparison result of the comparing means. A 2-bit partial quotient is determined based on the comparison result of the comparing means and subtraction results of the first and second subtracting means. As a result, the critical path is simplified and hence the delay time is shortened.
摘要翻译：第一减法装置从除数数据或部分余数数据中减除除数数据。与第一减法装置的减法并行，比较装置执行除数或部分余数数据的最高3位数据与除数数据的最高3位数据之间的比较。第一选择装置根据比较装置的比较结果向左移一比特，将除数数据或部分余数数据或第一减法装置的输出数据提供给第二减法装置。基于比较装置的比较结果和第一和第二减法装置的减法结果确定2位部分商。结果，关键路径被简化，因此延迟时间缩短。

10. 发明授权

US4910668A Address conversion apparatus 失效
标题翻译：地址转换装置
公开(公告)号：US4910668A
公开(公告)日：1990-03-20
申请号：US100561
申请日：1987-09-24
申请人： Tadashi Okamoto , Hiroshi Kadota , Masaitsu Nakajima
发明人： Tadashi Okamoto , Hiroshi Kadota , Masaitsu Nakajima
IPC分类号： G06F12/10 , G06F12/12 , G11C15/04
CPC分类号： G06F12/1036 , G06F12/123
摘要： An address conversion apparatus includes a content addressable memory for storing a plurality of logical addresses, and a random access memory for storing a plurality of physical addresses corresponding to the logical addresses. When an input logical address is received, a search is conducted to find the same logical address stored in the memory. When the same logical address is found, the content addressable memory causes the random access memory to output a corresponding physical address. The content addressable memory includes a plurality of logical address storage units. Each unit has a plurality of data bit cells for storing address data and a process identification number cell for storing a process identification number. Thereby, a plurality of logical addresses which correspond to different processes are stored in the single content addressable memory.
摘要翻译：地址转换装置包括用于存储多个逻辑地址的内容可寻址存储器和用于存储对应于逻辑地址的多个物理地址的随机存取存储器。当接收到输入逻辑地址时，进行搜索以找到存储在存储器中的相同逻辑地址。当找到相同的逻辑地址时，内容可寻址存储器使随机存取存储器输出相应的物理地址。内容可寻址存储器包括多个逻辑地址存储单元。每个单元具有用于存储地址数据的多个数据位单元和用于存储处理标识号的处理标识号单元。因此，与单个内容可寻址存储器中存储对应于不同进程的多个逻辑地址。

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