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1. 发明授权

US06906551B2 Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US06906551B2
公开(公告)日：2005-06-14
申请号：US10154956
申请日：2002-05-28
申请人： Hiroyuki Mizuno , Masataka Minami , Koichiro Ishibashi , Masayuki Miyazaki
发明人： Hiroyuki Mizuno , Masataka Minami , Koichiro Ishibashi , Masayuki Miyazaki
IPC分类号： H01L27/092 , H01L27/105 , H03K3/01
CPC分类号： H01L27/0207 , H01L27/092 , H01L27/105 , H03K3/011 , H03K3/0315 , H03K19/0016
摘要： A semiconductor integrated circuit device comprising a logical circuit including a MIS transistor formed on a semiconductor substrate, a control circuit for controlling a threshold voltage of the MIS transistor forming the logical circuit, an oscillation circuit including a MIS transistor formed on the semiconductor substrate, the oscillation circuit being constructed so that the frequency of an oscillation output thereof can be made variable, and a buffer circuit, in which the control circuit is supplied with a clock signal having a predetermined frequency and the oscillation output of the oscillation circuit so that the control circuit compares the frequency of the oscillation output and the frequency of the clock signal to output a first control signal, the oscillation circuit is controlled by the first control signal so that the frequency of the oscillation output corresponds to the frequency of the clock signal, the control of the frequency of the oscillation output being performed in such a manner that the first control signal controls a threshold voltage of the MIS transistor forming the oscillation circuit, and the buffer circuit is constructed so that it is inputted with the first control signal to output a second control signal corresponding to the first control signal, the second control signal controlling the threshold voltage of the MIS transistor forming the logical circuit.
摘要翻译：一种半导体集成电路器件，包括一个逻辑电路，该逻辑电路包括形成在半导体衬底上的MIS晶体管，用于控制形成逻辑电路的MIS晶体管的阈值电压的控制电路，包括形成在半导体衬底上的MIS晶体管的振荡电路，振荡电路被构造成使得其振荡输出的频率可以变化;以及缓冲电路，其中向控制电路提供具有预定频率的时钟信号和振荡电路的振荡输出，使得控制电路将振荡输出的频率和时钟信号的频率进行比较以输出第一控制信号，振荡电路由第一控制信号控制，使得振荡输出的频率对应于时钟信号的频率，控制振荡输出的频率 d，使得第一控制信号控制形成振荡电路的MIS晶体管的阈值电压，并且缓冲电路被构造成输入第一控制信号以输出与第一控制相对应的第二控制信号信号，所述第二控制信号控制构成所述逻辑电路的所述MIS晶体管的阈值电压。

2. 发明申请

US20070063735A1 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US20070063735A1
公开(公告)日：2007-03-22
申请号：US11526612
申请日：2006-09-26
申请人： Hiroyuki Mizuno , Masataka Minami , Koichiro Ishibashi , Masayuki Miyazaki
发明人： Hiroyuki Mizuno , Masataka Minami , Koichiro Ishibashi , Masayuki Miyazaki
IPC分类号： H03K19/0175
CPC分类号： H01L27/0207 , H01L27/092 , H01L27/105 , H03K3/011 , H03K3/0315 , H03K19/0016
摘要： A semiconductor integrated circuit device which includes a logical circuit containing a MIS transistor on a semiconductor substrate, a control circuit for controlling a threshold voltage of the MIS transistor in the logical circuit, an oscillation circuit containing a MIS transistor on the semiconductor substrate, and a buffer circuit, the control circuit compares the frequency of the oscillation output and frequency of a clock signal to output a first control signal, the first control signal controls a threshold voltage of the MIS transistor of the oscillation circuit, and the buffer circuit is inputted with the first control signal to output a second control signal corresponding to the first control signal, the second control signal controlling the threshold voltage of the MIS transistor of the logical circuit.
摘要翻译：一种半导体集成电路器件，包括在半导体衬底上包含MIS晶体管的逻辑电路，用于控制逻辑电路中的MIS晶体管的阈值电压的控制电路，在半导体衬底上包含MIS晶体管的振荡电路，以及缓冲电路，控制电路比较振荡输出的频率和时钟信号的频率，输出第一控制信号，第一控制信号控制振荡电路的MIS晶体管的阈值电压，缓冲电路输入所述第一控制信号输出对应于所述第一控制信号的第二控制信号，所述第二控制信号控制所述逻辑电路的所述MIS晶体管的阈值电压。

3. 发明授权

US07112999B2 Semiconductor integrated circuit device 失效
公开(公告)号：US07112999B2
公开(公告)日：2006-09-26
申请号：US11124060
申请日：2005-05-09
申请人： Hiroyuki Mizuno , Masataka Minami , Koichiro Ishibashi , Masayuki Miyazaki
发明人： Hiroyuki Mizuno , Masataka Minami , Koichiro Ishibashi , Masayuki Miyazaki
IPC分类号： H03K3/01
CPC分类号： H01L27/0207 , H01L27/092 , H01L27/105 , H03K3/011 , H03K3/0315 , H03K19/0016
摘要： A semiconductor integrated circuit device comprising a logical circuit including a MIS transistor formed on a semiconductor substrate, a control circuit for controlling a threshold voltage of the MIS transistor forming the logical circuit, an oscillation circuit including a MIS transistor formed on the semiconductor substrate, the oscillation circuit being constructed so that the frequency of an oscillation output thereof can be made variable, and a buffer circuit, in which the control circuit is supplied with a clock signal having a predetermined frequency and the oscillation output of the oscillation circuit so that the control circuit compares the frequency of the oscillation output and the frequency of the clock signal to output a first control signal, the oscillation circuit is controlled by the first control signal so that the frequency of the oscillation output corresponds to the frequency of the clock signal, the control of the frequency of the oscillation output being performed in such a manner that the first control signal controls a threshold voltage of the MIS transistor forming the oscillation circuit, and the buffer circuit is constructed so that it is inputted with the first control signal to output a second control signal corresponding to the first control signal, the second control signal controlling the threshold voltage of the MIS transistor forming the logical circuit.

4. 发明授权

US6140686A Semiconductor integrated circuit device 失效
公开(公告)号：US6140686A
公开(公告)日：2000-10-31
申请号：US979947
申请日：1997-11-26
申请人： Hiroyuki Mizuno , Masataka Minami , Koichiro Ishibashi , Masayuki Miyazaki
发明人： Hiroyuki Mizuno , Masataka Minami , Koichiro Ishibashi , Masayuki Miyazaki
IPC分类号： H01L27/092 , H01L27/105 , H01L27/10
CPC分类号： H01L27/0207 , H01L27/092 , H01L27/105 , H03K19/0016 , H03K3/011 , H03K3/0315
摘要： A semiconductor integrated circuit device comprising a logical circuit including a MIS transistor formed on a semiconductor substrate, a control circuit for controlling a threshold voltage of the MIS transistor forming the logical circuit, an oscillation circuit including a MIS transistor formed on the semiconductor substrate, the oscillation circuit being constructed so that the frequency of an oscillation output thereof can be made variable, and a buffer circuit, in which the control circuit is supplied with a clock signal having a predetermined frequency and the oscillation output of the oscillation circuit so that the control circuit compares the frequency of the oscillation output and the frequency of the clock signal to output a first control signal, the oscillation circuit is controlled by the first control signal so that the frequency of the oscillation output corresponds to the frequency of the clock signal, the control of the frequency of the oscillation output being performed in such a manner that the first control signal controls a threshold voltage of the MIS transistor forming the oscillation circuit, and the buffer circuit is constructed so that it is inputted with the first control signal to output a second control signal corresponding to the first control signal, the second control signal controlling the threshold voltage of the MIS transistor forming the logical circuit.

5. 发明申请

US20050195041A1 Semiconductor integrated circuit device 失效
公开(公告)号：US20050195041A1
公开(公告)日：2005-09-08
申请号：US11124060
申请日：2005-05-09
申请人： Hiroyuki Mizuno , Masataka Minami , Koichiro Ishibashi , Masayuki Miyazaki
发明人： Hiroyuki Mizuno , Masataka Minami , Koichiro Ishibashi , Masayuki Miyazaki
IPC分类号： H01L27/092 , H01L27/105 , H03L7/00
CPC分类号： H01L27/0207 , H01L27/092 , H01L27/105 , H03K3/011 , H03K3/0315 , H03K19/0016
摘要： A semiconductor integrated circuit device comprising a logical circuit including a MIS transistor formed on a semiconductor substrate, a control circuit for controlling a threshold voltage of the MIS transistor forming the logical circuit, an oscillation circuit including a MIS transistor formed on the semiconductor substrate, the oscillation circuit being constructed so that the frequency of an oscillation output thereof can be made variable, and a buffer circuit, in which the control circuit is supplied with a clock signal having a predetermined frequency and the oscillation output of the oscillation circuit so that the control circuit compares the frequency of the oscillation output and the frequency of the clock signal to output a first control signal, the oscillation circuit is controlled by the first control signal so that the frequency of the oscillation output corresponds to the frequency of the clock signal, the control of the frequency of the oscillation output being performed in such a manner that the first control signal controls a threshold voltage of the MIS transistor forming the oscillation circuit, and the buffer circuit is constructed so that it is inputted with the first control signal to output a second control signal corresponding to the first control signal, the second control signal controlling the threshold voltage of the MIS transistor forming the logical circuit.

6. 发明授权

US06404232B1 Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US06404232B1
公开(公告)日：2002-06-11
申请号：US09696283
申请日：2000-10-26
申请人： Hiroyuki Mizuno , Masataka Minami , Koichiro Ishibashi
发明人： Hiroyuki Mizuno , Masataka Minami , Koichiro Ishibashi
IPC分类号： H03K301
CPC分类号： H01L27/0207 , H01L27/092 , H01L27/105 , H03K3/011 , H03K3/0315 , H03K19/0016
摘要： A semiconductor integrated circuit device comprising a logical circuit including a MIS transistor formed on a semiconductor substrate, a control circuit for controlling a threshold voltage of the MIS transistor forming the logical circuit, an oscillation circuit including a MIS transistor formed on the semiconductor substrate, the oscillation circuit being constructed so that the frequency of an oscillation output thereof can be made variable, and a buffer circuit, in which the control circuit is supplied with a clock signal having a predetermined frequency and the oscillation output of the oscillation circuit so that the control circuit compares the frequency of the oscillation output and the frequency of the clock signal to output a first control signal, the oscillation circuit is controlled by the first control signal so that the frequency of the oscillation output corresponds to the frequency of the clock signal, the control of the frequency of the oscillation output being performed in such a manner that the first control signal controls a threshold voltage of the MIS transistor forming the oscillation circuit, and the buffer circuit is constructed so that it is inputted with the first control signal to output a second control signal corresponding to the first control signal, the second control signal controlling the threshold voltage of the MIS transistor forming the logical circuit.
摘要翻译：一种半导体集成电路器件，包括一个逻辑电路，该逻辑电路包括形成在半导体衬底上的MIS晶体管，用于控制形成逻辑电路的MIS晶体管的阈值电压的控制电路，包括形成在半导体衬底上的MIS晶体管的振荡电路，振荡电路被构造成使得其振荡输出的频率可以变化;以及缓冲电路，其中向控制电路提供具有预定频率的时钟信号和振荡电路的振荡输出，使得控制电路将振荡输出的频率和时钟信号的频率进行比较以输出第一控制信号，振荡电路由第一控制信号控制，使得振荡输出的频率对应于时钟信号的频率，控制振荡输出的频率 d，使得第一控制信号控制形成振荡电路的MIS晶体管的阈值电压，并且缓冲电路被构造成输入第一控制信号以输出与第一控制相对应的第二控制信号信号，所述第二控制信号控制构成所述逻辑电路的所述MIS晶体管的阈值电压。

7. 发明申请

US20050146961A1 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US20050146961A1
公开(公告)日：2005-07-07
申请号：US11042172
申请日：2005-01-26
申请人： Kenichi Osada , Masataka Minami , Shuji Ikeda , Koichiro Ishibashi
发明人： Kenichi Osada , Masataka Minami , Shuji Ikeda , Koichiro Ishibashi
IPC分类号： H01L27/10 , H01L21/8244 , H01L27/11 , G11C7/02
CPC分类号： H01L27/1104 , G11C11/412 , G11C11/417 , H01L27/11 , H01L29/4916 , H01L29/783 , Y10S257/904
摘要： Prior known static random access memory (SRAM) cells are required that a diffusion layer be bent into a key-like shape in order to make electrical contact with a substrate with a P-type well region formed therein, which would result in a decrease in asymmetry leading to occurrence of a problem as to the difficulty in micro-patterning. To avoid this problem, the P-type well region in which an inverter making up an SRAM cell is formed is subdivided into two portions, which are disposed on the opposite sides of an N-type well region NW1 and are formed so that a diffusion layer forming a transistor has no curvature while causing the layout direction to run in a direction parallel to well boundary lines and bit lines. At intermediate locations of an array, regions for use in supplying power to the substrate are formed in parallel to word lines in such a manner that one regions is provided per group of thirty two memory cell rows or sixty four cell rows.
摘要翻译：现有的已知的静态随机存取存储器（SRAM）单元需要将扩散层弯曲成键状形状，以便与其中形成有P型阱区的衬底进行电接触，这将导致不对称性导致了微图案化困难的问题的发生。为了避免这个问题，构成SRAM单元的逆变器的P型阱区被细分为两部分，它们设置在N型阱区NW 1的相对侧，并形成为形成晶体管的扩散层没有曲率，同时使得布局方向在平行于边界线和位线的方向上运行。在阵列的中间位置处，以与字线平行的方式形成用于向基板供电的区域，以每组三十二个存储单元行或六十四个单元行提供一个区域。

8. 发明授权

US06677649B2 SRAM cells with two P-well structure 有权
标题翻译：具有两个P阱结构的SRAM单元
公开(公告)号：US06677649B2
公开(公告)日：2004-01-13
申请号：US09565535
申请日：2000-05-05
申请人： Kenichi Osada , Masataka Minami , Shuji Ikeda , Koichiro Ishibashi
发明人： Kenichi Osada , Masataka Minami , Shuji Ikeda , Koichiro Ishibashi
IPC分类号： H01L2976
CPC分类号： H01L27/1104 , G11C11/412 , G11C11/417 , H01L27/11 , H01L29/4916 , H01L29/783 , Y10S257/904
摘要： Prior known static random access memory (SRAM) cells are required that a diffusion layer be bent into a key-like shape in order to make electrical contact with a substrate with a P-type well region formed therein, which would result in a decrease in asymmetry leading to occurrence of a problem as to the difficulty in micro-patterning. To avoid this problem, the P-type well region in which an inverter making up an SRAM cell is formed is subdivided into two portions, which are disposed on the opposite sides of an N-type well region NW1 and are formed so that a diffusion layer forming a transistor has no curvature while causing the layout direction to run in a direction parallel to well boundary lines and bit lines. At intermediate locations of an array, regions for use in supplying power to the substrate are formed in parallel to word lines in such a manner that one regions is provided per group of thirty two memory cell rows or sixty four cell rows.
摘要翻译：现有的已知的静态随机存取存储器（SRAM）单元需要将扩散层弯曲成键状形状，以便与其中形成有P型阱区的衬底进行电接触，这将导致不对称性导致了微图案化困难的问题的发生。为了避免这个问题，构成SRAM单元的逆变器的P型阱区被细分成两部分，它们设置在N型阱区NW1的相对侧上，并形成为扩散形成晶体管的层没有曲率，同时使得布局方向在平行于阱边界线和位线的方向上运行。在阵列的中间位置处，以与字线平行的方式形成用于向基板供电的区域，以每组三十二个存储单元行或六十四个单元行提供一个区域。

9. 发明授权

US09286968B2 Semiconductor integrated circuit device including SRAM cell array and a wiring layer for supplying voltage to well regions of SRAM cells provided on a region exterior of SRAM cell array 有权
标题翻译：包括SRAM单元阵列的半导体集成电路器件和用于向SRAM单元阵列的外部区域上提供的SRAM单元的阱区域提供电压的布线层
公开(公告)号：US09286968B2
公开(公告)日：2016-03-15
申请号：US13616435
申请日：2012-09-14
申请人： Kenichi Osada , Masataka Minami , Shuji Ikeda , Koichiro Ishibashi
发明人： Kenichi Osada , Masataka Minami , Shuji Ikeda , Koichiro Ishibashi
IPC分类号： H01L29/76 , H01L27/11 , G11C11/412
CPC分类号： H01L27/1104 , G11C11/412 , G11C11/417 , H01L27/11 , H01L29/4916 , H01L29/783 , Y10S257/904
摘要： Prior known static random access memory (SRAM) cells required that a diffusion layer be bent into a key-like shape in order to make electrical contact with a substrate with a P-type well region formed therein, which would result in a decrease in asymmetry leading to difficulty in micro-patterning. To avoid this problem, the P-type well region in which an inverter making up an SRAM cell is formed is subdivided into two portions, which are disposed on the opposite sides of an N-type well region NW1 and are formed so that a diffusion layer forming a transistor has no curvature while causing the layout direction to run in a direction parallel to well boundary lines and bit lines. At intermediate locations of an array, regions for use in supply power to the substrate are formed in parallel to word lines.
摘要翻译：现有已知的静态随机存取存储器（SRAM）单元需要将扩散层弯曲成键状形状，以便与其中形成有P型阱区的衬底电接触，这将导致不对称性的降低导致微图案化困难。为了避免这个问题，构成SRAM单元的逆变器的P型阱区被细分成两部分，它们设置在N型阱区NW1的相对侧上，并形成为扩散形成晶体管的层没有曲率，同时使得布局方向在平行于阱边界线和位线的方向上运行。在阵列的中间位置处，与基板平行地形成用于向基板供电的区域。

10. 发明申请

US20100301422A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权
标题翻译：半导体集成电路设备
公开(公告)号：US20100301422A1
公开(公告)日：2010-12-02
申请号：US12821329
申请日：2010-06-23
申请人： Kenichi Osada , Masataka Minami , Shuji Ikeda , Koichiro Ishibashi
发明人： Kenichi Osada , Masataka Minami , Shuji Ikeda , Koichiro Ishibashi
IPC分类号： H01L27/11
CPC分类号： H01L27/1104 , G11C11/412 , G11C11/417 , H01L27/11 , H01L29/4916 , H01L29/783 , Y10S257/904
摘要： Prior known static random access memory (SRAM) cells required that a diffusion layer be bent into a key-like shape in order to make electrical contact with a substrate with a P-type well region formed therein, which would result in a decrease in asymmetry leading to occurrence of a problem as to the difficulty in micro-patterning. To avoid this problem, the P-type well region in which an inverter making up an SRAM cell is formed is subdivided into two portions, which are disposed on the opposite sides of an N-type well region NW1 and are formed so that a diffusion layer forming a transistor has no curvature while causing the layout direction to run in a direction parallel to well boundary lines and bit lines. At intermediate locations of an array, regions for use in supply power to the substrate are formed in parallel to word lines in such a manner that one region is provided per group of thirty two memory cell rows or sixty four cell rows.
摘要翻译：现有已知的静态随机存取存储器（SRAM）单元需要将扩散层弯曲成键状形状，以便与其中形成有P型阱区的衬底电接触，这将导致不对称性的降低导致出现微图案化困难的问题。为了避免这个问题，构成SRAM单元的逆变器的P型阱区被细分成两部分，它们设置在N型阱区NW1的相对侧上，并形成为扩散形成晶体管的层没有曲率，同时使得布局方向在平行于阱边界线和位线的方向上运行。在阵列的中间位置处，用于向衬底供电的区域形成为平行于字线，以这样的方式，每组三十二个存储单元行或六十六个单元行提供一个区域。

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