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1. 发明授权

US08133788B2 Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08133788B2
公开(公告)日：2012-03-13
申请号：US12567050
申请日：2009-09-25
申请人： Yasuyuki Sayama , Tetsuya Okada , Makoto Oikawa , Hiroyasu Ishida , Kazunari Kushiyama
发明人： Yasuyuki Sayama , Tetsuya Okada , Makoto Oikawa , Hiroyasu Ishida , Kazunari Kushiyama
IPC分类号： H01L21/336
CPC分类号： H01L29/7802 , H01L29/0878 , H01L29/42372 , H01L29/4238 , H01L29/66712
摘要： An n type impurity region is provided below a gate electrode. By setting a gate length to be less than a depth of a channel region, a side surface of the channel region and a side surface of the n type impurity region adjacent to the channel region form a substantially perpendicular junction surface. Thus, since a depletion layer widens uniformly in a depth direction of a substrate, it is possible to secure a predetermined breakdown voltage. Furthermore, since an interval between the channel regions, above which the gate electrode is disposed, is uniform from its surface to its bottom, it is possible to increase an impurity concentration of the n type impurity region, resulting in an achievement of a low on-resistance.
摘要翻译：在栅电极的下方设置有n型杂质区。通过将栅极长度设置为小于沟道区的深度，沟道区的侧表面和与沟道区相邻的n型杂质区的侧表面形成基本上垂直的接合表面。因此，由于耗尽层在衬底的深度方向上均匀地变宽，因此可以确保预定的击穿电压。此外，由于栅极电极上方的沟道区域之间的间隔从表面到底部均匀，所以可以增加n型杂质区域的杂质浓度，导致实现低的导通 -抵抗性。

2. 发明申请

US20090096030A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20090096030A1
公开(公告)日：2009-04-16
申请号：US12239368
申请日：2008-09-26
申请人： Hiroyasu ISHIDA , Yasuyuki Sayama , Tetsuya Okada
发明人： Hiroyasu ISHIDA , Yasuyuki Sayama , Tetsuya Okada
IPC分类号： H01L27/105
CPC分类号： H01L29/7811 , H01L29/0634 , H01L29/0653 , H01L29/0661 , H01L29/66734 , H01L29/7813 , H01L2924/0002 , H01L2924/00
摘要： Provided is a semiconductor device in which an insulating region surrounding an element region is provided in an end portion of a semiconductor region with a super junction structure. Since a depletion layer in the element region ends in the insulating region, the end portion of the element region is not formed in a curved surface shape. In other words, the depletion layer has no curved surface in which internal electric fields are concentrated. For this reason, there is no need to take a measure to cause the depletion layer to spread in a horizontal direction by proving a terminal region. Since the terminal region is unnecessary, a chip size can be reduced. Alternatively, an area of the element region can be expanded.
摘要翻译：提供一种半导体器件，其中在具有超结结构的半导体区域的端部中设置围绕元件区域的绝缘区域。由于元件区域中的耗尽层在绝缘区域中结束，元件区域的端部不形成为曲面形状。换句话说，耗尽层没有内部电场集中的曲面。因此，通过证明终端区域，不需要采取措施来使耗尽层在水平方向上扩展。由于不需要端子区域，因此可以减小芯片尺寸。或者，可以扩展元件区域的区域。

3. 发明授权

US07777316B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07777316B2
公开(公告)日：2010-08-17
申请号：US12239368
申请日：2008-09-26
申请人： Hiroyasu Ishida , Yasuyuki Sayama , Tetsuya Okada
发明人： Hiroyasu Ishida , Yasuyuki Sayama , Tetsuya Okada
IPC分类号： H01L23/02 , H01L23/34
CPC分类号： H01L29/7811 , H01L29/0634 , H01L29/0653 , H01L29/0661 , H01L29/66734 , H01L29/7813 , H01L2924/0002 , H01L2924/00
摘要： Provided is a semiconductor device in which an insulating region surrounding an element region is provided in an end portion of a semiconductor region with a super junction structure. Since a depletion layer in the element region ends in the insulating region, the end portion of the element region is not formed in a curved surface shape. In other words, the depletion layer has no curved surface in which internal electric fields are concentrated. For this reason, there is no need to take a measure to cause the depletion layer to spread in a horizontal direction by proving a terminal region. Since the terminal region is unnecessary, a chip size can be reduced. Alternatively, an area of the element region can be expanded.
摘要翻译：提供一种半导体器件，其中在具有超结结构的半导体区域的端部中设置围绕元件区域的绝缘区域。由于元件区域中的耗尽层在绝缘区域中结束，元件区域的端部不形成为曲面形状。换句话说，耗尽层没有内部电场集中的曲面。因此，通过证明终端区域，不需要采取措施使耗尽层在水平方向上扩展。由于不需要端子区域，因此可以减小芯片尺寸。或者，可以扩展元件区域的区域。

4. 发明申请

US20100015772A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20100015772A1
公开(公告)日：2010-01-21
申请号：US12567050
申请日：2009-09-25
申请人： Yasuyuki SAYAMA , Tetsuya Okada , Makoto Oikawa , Hiroyasu Ishida , Kazunari Kushiyama
发明人： Yasuyuki SAYAMA , Tetsuya Okada , Makoto Oikawa , Hiroyasu Ishida , Kazunari Kushiyama
IPC分类号： H01L21/336 , H01L21/28
CPC分类号： H01L29/7802 , H01L29/0878 , H01L29/42372 , H01L29/4238 , H01L29/66712
摘要： An n type impurity region is provided below a gate electrode. By setting a gate length to be less than a depth of a channel region, a side surface of the channel region and a side surface of the n type impurity region adjacent to the channel region form a substantially perpendicular junction surface. Thus, since a depletion layer widens uniformly in a depth direction of a substrate, it is possible to secure a predetermined breakdown voltage. Furthermore, since an interval between the channel regions, above which the gate electrode is disposed, is uniform from its surface to its bottom, it is possible to increase an impurity concentration of the n type impurity region, resulting in an achievement of a low on-resistance.
摘要翻译：在栅电极的下方设置有n型杂质区。通过将栅极长度设置为小于沟道区的深度，沟道区的侧表面和与沟道区相邻的n型杂质区的侧表面形成基本上垂直的接合表面。因此，由于耗尽层在衬底的深度方向上均匀地变宽，因此可以确保预定的击穿电压。此外，由于栅极电极上方的沟道区域之间的间隔从表面到底部均匀，所以可以增加n型杂质区域的杂质浓度，导致实现低的导通 -抵抗性。

5. 发明申请

US20070072352A1 Insulated gate field effect transistor and manufacturing method thereof 审中-公开
标题翻译：绝缘栅场效应晶体管及其制造方法
公开(公告)号：US20070072352A1
公开(公告)日：2007-03-29
申请号：US11519208
申请日：2006-09-12
申请人： Kazunari Kushiyama , Tetsuya Okada , Makoto Oikawa , Hiroyasu Ishida , Yasuyuki Sayama
发明人： Kazunari Kushiyama , Tetsuya Okada , Makoto Oikawa , Hiroyasu Ishida , Yasuyuki Sayama
IPC分类号： H01L21/337 , H01L21/8242 , H01L21/336
CPC分类号： H01L29/7802 , H01L29/0878 , H01L29/41766 , H01L29/42372 , H01L29/4238 , H01L29/66712 , H01L29/66727
摘要： A separation hole is provided in the center of the gate electrode. Accordingly, it is possible to suppress a drastic increase in feedback capacitance Crss in the case where drain-source voltage VDS is decreased and the width of the depletion layer is narrowed. Thus, high-frequency switching characteristics are improved. Moreover, n type impurities are implanted from the separation hole to form an n type impurity region between channel regions. Since a resistance in a portion below the gate electrode can be reduced, an on-resistance can be reduced. The n type impurity region can be formed in a self-aligning manner.
摘要翻译：在栅电极的中心设置有分离孔。因此，在漏极 - 源极电压VDS降低并且耗尽层的宽度变窄的情况下，可以抑制反馈电容Crss急剧增加。因此，提高了高频开关特性。此外，从分离孔注入n型杂质，在沟道区域之间形成n型杂质区。由于可以减小栅电极下方的电阻，所以可以降低导通电阻。可以以自对准的方式形成n型杂质区域。

6. 发明申请

US20060220122A1 Semiconductor device and method of manufacturing the same 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060220122A1
公开(公告)日：2006-10-05
申请号：US11373488
申请日：2006-03-13
申请人： Yasuyuki Sayama , Tetsuya Okada , Makoto Oikawa , Hiroyasu Ishida , Kazunari Kushiyama
发明人： Yasuyuki Sayama , Tetsuya Okada , Makoto Oikawa , Hiroyasu Ishida , Kazunari Kushiyama
IPC分类号： H01L29/76
CPC分类号： H01L29/7802 , H01L29/0878 , H01L29/42372 , H01L29/4238 , H01L29/66712
摘要： An n type impurity region is provided below a gate electrode. By setting a gate length to be less than a depth of a channel region, a side surface of the channel region and a side surface of the n type impurity region adjacent to the channel region form a substantially perpendicular junction surface. Thus, since a depletion layer widens uniformly in a depth direction of a substrate, it is possible to secure a predetermined breakdown voltage. Furthermore, since an interval between the channel regions, above which the gate electrode is disposed, is uniform from its surface to its bottom, it is possible to increase an impurity concentration of the n type impurity region, resulting in an achievement of a low on-resistance.
摘要翻译：在栅电极的下方设置有n型杂质区。通过将栅极长度设置为小于沟道区的深度，沟道区的侧表面和与沟道区相邻的n型杂质区的侧表面形成基本上垂直的接合表面。因此，由于耗尽层在衬底的深度方向上均匀地变宽，因此可以确保预定的击穿电压。此外，由于栅极电极上方的沟道区域之间的间隔从表面到底部均匀，所以可以增加n型杂质区域的杂质浓度，导致实现低的导通 -抵抗性。

7. 发明授权

US07492121B2 Smart battery and method for recognizing battery type using the same 有权
标题翻译：智能电池及使用其识别电池类型的方法
公开(公告)号：US07492121B2
公开(公告)日：2009-02-17
申请号：US11216458
申请日：2005-08-30
申请人： Jong Sam Kim , Tetsuya Okada
发明人： Jong Sam Kim , Tetsuya Okada
IPC分类号： H02J7/14
CPC分类号： H02J7/0003 , H02J2007/0098
摘要： A smart battery pack and a method for recognizing the battery type using the same. The smart battery pack includes at least one battery cell coupled to an external set via positive and negative electrode terminals. A timer circuit is coupled to the external set via a data terminal and is adapted to apply a predetermined timer circuit signal for a period of time when a predetermined signal is applied from the external set. A first switch is controlled by the timer circuit and applies electric power from the battery cell, and a register outputs a predetermined register signal causing a smart battery controller to output battery type information to the external set. The smart battery pack has only one data line between the smart battery pack and the external set (and one data terminal on each) facilitating communication between the devices while maintaining a reduced manufacturing cost.
摘要翻译：一种智能电池组以及使用其来识别电池类型的方法。智能电池组包括经由正极和负极端子耦合到外部组的至少一个电池单元。定时器电路通过数据端子耦合到外部组件，并且适用于在从外部组件施加预定信号的时间段内施加预定定时器电路信号。第一开关由定时器电路控制并且从电池单元施加电力，并且寄存器输出预定的寄存器信号，使得智能电池控制器向外部组输出电池类型信息。智能电池组在智能电池组和外部组件之间仅有一条数据线（和每个数据终端之间），有助于器件之间的通信，同时保持降低的制造成本。

8. 发明申请

US20070160052A1 Packet processing apparatus and method 失效
标题翻译：分组处理装置和方法
公开(公告)号：US20070160052A1
公开(公告)日：2007-07-12
申请号：US11649839
申请日：2007-01-05
申请人： Tetsuya Okada
发明人： Tetsuya Okada
IPC分类号： H04L12/56
CPC分类号： H04L45/742 , H04L45/7453 , H04L47/10 , H04L47/30 , H04L49/90 , H04L49/901 , H04L69/22
摘要： A packet processing apparatus includes a packet processing engine and a search engine connected through a bus having a bandwidth which is equal to or greater than a total transmission bandwidth of one or more receiving ports. The packet processing engine is configured to append a device internal header containing a search key to each of the packets, transfer the packets to the search engine through the bus, and receive the packets whose device internal headers are provided with search result information from the search engine through the bus. The search engine includes a packet buffer for temporarily storing the packets, a search processing part for performing search processing on the basis of the search key in the device internal header, and means for transferring the search result information from the search processing part and the packets stored in the packet buffer to the packet processing engine.
摘要翻译：分组处理装置包括通过具有等于或大于一个或多个接收端口的总传输带宽的带宽的总线连接的分组处理引擎和搜索引擎。分组处理引擎被配置为将包含搜索关键字的设备内部头部附加到每个分组，通过总线将分组传送到搜索引擎，并且从搜索接收具有设备内部头部的分组的搜索结果信息发动机通过公共汽车。搜索引擎包括用于临时存储分组的分组缓冲器，用于基于设备内部报头中的搜索关键字执行搜索处理的搜索处理部分，以及用于从搜索处理部分和分组传送搜索结果信息的装置存储在分组缓冲器中的分组处理引擎。

9. 发明申请

US20050184406A1 Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：US20050184406A1
公开(公告)日：2005-08-25
申请号：US11061730
申请日：2005-02-22
申请人： Tetsuya Okada , Hiroaki Saito
发明人： Tetsuya Okada , Hiroaki Saito
IPC分类号： H01L29/872 , H01L29/47 , H01L29/861 , H01L31/062
CPC分类号： H01L29/872 , H01L29/861
摘要： Conventionally, VF and IR characteristics of a Schottky barrier diode are in a tradeoff relation and there is a problem in that an increase in a leak current is unavoidable in order to realize a reduction in VF. To solve the problem, p type semiconductor regions of a pillar shape reaching an n+ type semiconductor substrate are provided in an n− type semiconductor layer. When a reverse voltage is applied, a depletion layer expanding in a substrate horizontal direction from the p type semiconductor regions fills the n− type semiconductor layer. Thus, it is possible to prevent the leak current generated on a Schottky junction interface from leaking to a cathode side. Since an impurity concentration of the n− type semiconductor layer can be increased to a degree at which the depletion layer expanding from the p type semiconductor regions adjacent to each other can be pinched off, it is possible to realize a reduction in VF and it is possible to secure a predetermined breakdown voltage if only the depletion layer is pinched off.
摘要翻译：通常，肖特基势垒二极管的VF和IR特性是权衡关系的，并且存在为了实现VF的降低而不可避免地增加泄漏电流的问题。为了解决这个问题，在n型半导体层中设置了到n +型半导体衬底的柱状的p型半导体区域。当施加反向电压时，从p型半导体区域沿衬底水平方向膨胀的耗尽层填充n型半导体层。因此，可以防止在肖特基结界面上产生的泄漏电流泄漏到阴极侧。由于可以将n型半导体层的杂质浓度提高到从相邻的p型半导体区域扩大的耗尽层被夹除的程度，所以可以实现VF的降低，如果只有耗尽层被夹掉，则可以确保预定的击穿电压。

10. 发明授权

US06187111B1 Vacuum carburizing method 有权
标题翻译：真空渗碳法
公开(公告)号：US06187111B1
公开(公告)日：2001-02-13
申请号：US09261168
申请日：1999-03-03
申请人： Masaomi Waka , Toru Kadono , Satoshi Harai , Tetsuya Okada , Naoaki Imai
发明人： Masaomi Waka , Toru Kadono , Satoshi Harai , Tetsuya Okada , Naoaki Imai
IPC分类号： C23C822
CPC分类号： C23C8/22 , C21D1/773
摘要： An improved vacuum carburizing method is provided which is easy to handle or to maintenance and low equipment costs without using hydrogen gas or acetylenic gas. The improved vacuum carburizing method comprises a carburizing treatment of workpieces made from steel material heated to about 900-1100° C. performed by introducing an ethylenee gas as a carburizing gas at a vacuum of 1-10 kPa in a carburizing furnace chamber.
摘要翻译：提供了一种改进的真空渗碳方法，其在不使用氢气或炔属气体的情况下易于处理或维护和低设备成本。改进的真空渗碳方法包括通过在渗碳炉室中以1-10kPa的真空引入作为渗碳气体的乙烯气体进行加热至约900-1100℃的钢材制成的工件的渗碳处理。

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