专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07902053B2 Method of processing semiconductor wafer 有权
标题翻译：半导体晶片的处理方法
公开(公告)号：US07902053B2
公开(公告)日：2011-03-08
申请号：US12199547
申请日：2008-08-27
申请人： Hiroyasu Ishida , Yasuyuki Sayama
发明人： Hiroyasu Ishida , Yasuyuki Sayama
IPC分类号： H01L21/20
CPC分类号： H01L29/0634 , H01L21/26586
摘要： Formation and etching of an n type epitaxial layer and formation and etching of a p type epitaxial layer are alternately performed on the semiconductor substrate for at least three times to form all semiconductor layers, of the epitaxial layers. Thereby, impurity concentration profiles of the semiconductor layers can be uniform, and pn junctions can be formed vertically to a wafer surface. Furthermore, the semiconductor layers can each be formed with a narrow width, so that impurity concentrations thereof are increased. With this configuration, high breakdown voltage and low resistance can be achieved.
摘要翻译： n型外延层的形成和蚀刻以及p型外延层的形成和蚀刻在半导体衬底上交替进行至少三次以形成外延层的所有半导体层。因此，半导体层的杂质浓度分布可以是均匀的，并且pn结可以垂直于晶片表面形成。此外，半导体层各自可以形成为窄的宽度，使得其杂质浓度增加。利用这种结构，可以实现高击穿电压和低电阻。

2. 发明授权

US07777316B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07777316B2
公开(公告)日：2010-08-17
申请号：US12239368
申请日：2008-09-26
申请人： Hiroyasu Ishida , Yasuyuki Sayama , Tetsuya Okada
发明人： Hiroyasu Ishida , Yasuyuki Sayama , Tetsuya Okada
IPC分类号： H01L23/02 , H01L23/34
CPC分类号： H01L29/7811 , H01L29/0634 , H01L29/0653 , H01L29/0661 , H01L29/66734 , H01L29/7813 , H01L2924/0002 , H01L2924/00
摘要： Provided is a semiconductor device in which an insulating region surrounding an element region is provided in an end portion of a semiconductor region with a super junction structure. Since a depletion layer in the element region ends in the insulating region, the end portion of the element region is not formed in a curved surface shape. In other words, the depletion layer has no curved surface in which internal electric fields are concentrated. For this reason, there is no need to take a measure to cause the depletion layer to spread in a horizontal direction by proving a terminal region. Since the terminal region is unnecessary, a chip size can be reduced. Alternatively, an area of the element region can be expanded.
摘要翻译：提供一种半导体器件，其中在具有超结结构的半导体区域的端部中设置围绕元件区域的绝缘区域。由于元件区域中的耗尽层在绝缘区域中结束，元件区域的端部不形成为曲面形状。换句话说，耗尽层没有内部电场集中的曲面。因此，通过证明终端区域，不需要采取措施使耗尽层在水平方向上扩展。由于不需要端子区域，因此可以减小芯片尺寸。或者，可以扩展元件区域的区域。

3. 发明申请

US20050197127A1 Communication terminal, and communication computer program product 有权
标题翻译：通讯终端，通讯电脑程序产品
公开(公告)号：US20050197127A1
公开(公告)日：2005-09-08
申请号：US10899293
申请日：2004-07-26
申请人： Yukiyoshi Nakasaku , Hiroshi Takano , Hitoshi Nakanishi , Yasuyuki Sayama , Yuichi Tashiro
发明人： Yukiyoshi Nakasaku , Hiroshi Takano , Hitoshi Nakanishi , Yasuyuki Sayama , Yuichi Tashiro
IPC分类号： H04L12/28 , H04B7/26 , H04L12/725 , H04L12/733 , H04L12/807 , H04W4/00 , H04W40/02 , H04W40/12 , H04W74/08 , H04W84/12 , H04W84/18 , H04B17/00 , H04Q7/20
CPC分类号： H04W40/12 , H04B17/318 , H04W24/10 , H04W40/08 , H04W40/18 , H04W48/16 , H04W88/02
摘要： A communication terminal has an acquiring unit configured to acquire information related to a strength of a radio wave received, a selecting unit configured to select a data communication route based on the information acquired by the acquiring unit, and a storage unit configured to store information related to the data communication route selected by the selecting unit. The communication terminal is configured to perform wireless communication based on the information related to the data communication route.
摘要翻译：通信终端具有获取单元，被配置为获取与所接收的无线电波的强度有关的信息;选择单元，被配置为基于由所述获取单元获取的信息来选择数据通信路由;以及存储单元，被配置为存储与所述无线电波相关的信息到由选择单元选择的数据通信路由。通信终端被配置为基于与数据通信路由相关的信息来执行无线通信。

4. 发明授权

US08133788B2 Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08133788B2
公开(公告)日：2012-03-13
申请号：US12567050
申请日：2009-09-25
申请人： Yasuyuki Sayama , Tetsuya Okada , Makoto Oikawa , Hiroyasu Ishida , Kazunari Kushiyama
发明人： Yasuyuki Sayama , Tetsuya Okada , Makoto Oikawa , Hiroyasu Ishida , Kazunari Kushiyama
IPC分类号： H01L21/336
CPC分类号： H01L29/7802 , H01L29/0878 , H01L29/42372 , H01L29/4238 , H01L29/66712
摘要： An n type impurity region is provided below a gate electrode. By setting a gate length to be less than a depth of a channel region, a side surface of the channel region and a side surface of the n type impurity region adjacent to the channel region form a substantially perpendicular junction surface. Thus, since a depletion layer widens uniformly in a depth direction of a substrate, it is possible to secure a predetermined breakdown voltage. Furthermore, since an interval between the channel regions, above which the gate electrode is disposed, is uniform from its surface to its bottom, it is possible to increase an impurity concentration of the n type impurity region, resulting in an achievement of a low on-resistance.
摘要翻译：在栅电极的下方设置有n型杂质区。通过将栅极长度设置为小于沟道区的深度，沟道区的侧表面和与沟道区相邻的n型杂质区的侧表面形成基本上垂直的接合表面。因此，由于耗尽层在衬底的深度方向上均匀地变宽，因此可以确保预定的击穿电压。此外，由于栅极电极上方的沟道区域之间的间隔从表面到底部均匀，所以可以增加n型杂质区域的杂质浓度，导致实现低的导通 -抵抗性。

5. 发明申请

US20090096030A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20090096030A1
公开(公告)日：2009-04-16
申请号：US12239368
申请日：2008-09-26
申请人： Hiroyasu ISHIDA , Yasuyuki Sayama , Tetsuya Okada
发明人： Hiroyasu ISHIDA , Yasuyuki Sayama , Tetsuya Okada
IPC分类号： H01L27/105
CPC分类号： H01L29/7811 , H01L29/0634 , H01L29/0653 , H01L29/0661 , H01L29/66734 , H01L29/7813 , H01L2924/0002 , H01L2924/00
摘要： Provided is a semiconductor device in which an insulating region surrounding an element region is provided in an end portion of a semiconductor region with a super junction structure. Since a depletion layer in the element region ends in the insulating region, the end portion of the element region is not formed in a curved surface shape. In other words, the depletion layer has no curved surface in which internal electric fields are concentrated. For this reason, there is no need to take a measure to cause the depletion layer to spread in a horizontal direction by proving a terminal region. Since the terminal region is unnecessary, a chip size can be reduced. Alternatively, an area of the element region can be expanded.
摘要翻译：提供一种半导体器件，其中在具有超结结构的半导体区域的端部中设置围绕元件区域的绝缘区域。由于元件区域中的耗尽层在绝缘区域中结束，元件区域的端部不形成为曲面形状。换句话说，耗尽层没有内部电场集中的曲面。因此，通过证明终端区域，不需要采取措施来使耗尽层在水平方向上扩展。由于不需要端子区域，因此可以减小芯片尺寸。或者，可以扩展元件区域的区域。

6. 发明申请

US20090085111A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20090085111A1
公开(公告)日：2009-04-02
申请号：US12238128
申请日：2008-09-25
申请人： Yasuyuki SAYAMA
发明人： Yasuyuki SAYAMA
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/0878 , H01L29/1095 , H01L29/42372 , H01L29/4238 , H01L29/66712
摘要： Provided is a semiconductor device and a method of manufacturing a semiconductor device. In the semiconductor device, high-concentration n type impurity regions are formed respectively below gate electrodes. By setting a gate length to be smaller than a depth of channel regions, pn junction interfaces formed of adjacent side faces of the n type impurity regions and the channel regions can be substantially vertical to a top surface of a base. With this configuration, even when reduction in size is achieved in a super junction structure, a distance between the channel regions (i.e. a current path below the gate electrode) is not reduced unnecessarily. Accordingly, an increase in resistance can be prevented. In addition, depletion layers uniformly expand in the n type semiconductor regions, and impurity concentration of the regions can be increased consequently. Accordingly, reduction in resistance can be achieved.
摘要翻译：提供半导体器件和制造半导体器件的方法。在半导体装置中，分别在栅电极的下方形成高浓度的n型杂质区。通过将栅极长度设定为小于沟道区域的深度，由n型杂质区域和沟道区域的相邻侧面形成的pn结界面可以基本上垂直于基底的顶表面。利用这种结构，即使在超结结构中实现尺寸减小，也不会不必要地减少沟道区域之间的距离（即栅电极下方的电流路径）。因此，可以防止电阻的增加。此外，在n型半导体区域中耗尽层均匀地膨胀，从而可以增加区域的杂质浓度。因此，可以实现电阻的降低。

7. 发明授权

US07397771B2 Communication terminal and communication method 有权
标题翻译：通信终端和通信方式
公开(公告)号：US07397771B2
公开(公告)日：2008-07-08
申请号：US11087014
申请日：2005-03-22
申请人： Yukiyoshi Nakasaku , Hiroshi Takano , Hitoshi Nakanishi , Yasuyuki Sayama , Yuichi Tashiro
发明人： Yukiyoshi Nakasaku , Hiroshi Takano , Hitoshi Nakanishi , Yasuyuki Sayama , Yuichi Tashiro
IPC分类号： H04L12/28 , H04B3/36 , H04Q7/00
CPC分类号： H04W40/24 , H04L45/54 , H04W88/02 , H04W88/021 , H04W88/04
摘要： A communication terminal that builds a wireless network includes a control-information transceiver that transmits and receives control information indicating number of times of forwarding required for a communication with the communication terminal, with respect to other communication terminals connected to the wireless network; a routing-information creating unit that creates, based on the control information received, routing information indicating an initial forward-destination terminal to which data is firstly transmitted when the communication terminal is a destination, for each of the other communication terminals; and a data transmitting unit that transmits the data based on the routing information.
摘要翻译：建立无线网络的通信终端包括控制信息收发信机，用于相对于连接到无线网络的其他通信终端发送和接收指示与通信终端通信所需的转发次数的控制信息; 路由信息创建单元，用于对于每个其他通信终端，基于接收的控制信息，创建指示当通信终端为目的地时首先发送数据的初始前向目的地终端的路由信息; 以及基于路由信息发送数据的数据发送单元。

8. 发明申请

US20110159651A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20110159651A1
公开(公告)日：2011-06-30
申请号：US12974819
申请日：2010-12-21
申请人： TOSHIKAZU MATSUI , YASUYUKI SAYAMA , HIROKI ETO , TAKUMI HOSOYA
发明人： TOSHIKAZU MATSUI , YASUYUKI SAYAMA , HIROKI ETO , TAKUMI HOSOYA
IPC分类号： H01L21/336
CPC分类号： H01L29/66734 , H01L21/26586 , H01L29/42376 , H01L29/7397
摘要： The invention provides a method of manufacturing a semiconductor device at low cost in which the gate insulation film having a trench structure is not damaged by arsenic ions when the emitter layer or the like is formed and the insulation breakdown voltage is enhanced. A gate electrode made of polysilicon formed in a trench is thermally oxidized in a high temperature furnace or the like to form a thick polysilicon thermal oxide film on the gate electrode. Impurity ions are then ion-implanted to form an N type semiconductor layer that is to be an emitter layer or the like. At this time, the polysilicon thermal oxide film is formed thicker than the projected range Rp of impurity ions in the silicon oxide film for forming the N type semiconductor layer as the emitter layer or the like by ion implantation. This prevents a gate insulation film between the gate electrode and the N type semiconductor layer from being damaged by the impurity ions.
摘要翻译：本发明提供了一种以低成本制造半导体器件的方法，其中当形成发射极层等时，具有沟槽结构的栅极绝缘膜不被砷离子损坏并且绝缘击穿电压增强。在沟槽中形成的由多晶硅形成的栅电极在高温炉等中被热氧化，以在栅电极上形成厚的多晶硅热氧化膜。然后将杂质离子离子注入以形成作为发射极层等的N型半导体层。此时，通过离子注入，多晶硅热氧化膜形成得比用于形成N型半导体层的氧化硅膜中的杂质离子的投射范围Rp大，作为发射极层等。这防止了栅电极和N型半导体层之间的栅极绝缘膜被杂质离子损坏。

9. 发明申请

US20060220122A1 Semiconductor device and method of manufacturing the same 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060220122A1
公开(公告)日：2006-10-05
申请号：US11373488
申请日：2006-03-13
申请人： Yasuyuki Sayama , Tetsuya Okada , Makoto Oikawa , Hiroyasu Ishida , Kazunari Kushiyama
发明人： Yasuyuki Sayama , Tetsuya Okada , Makoto Oikawa , Hiroyasu Ishida , Kazunari Kushiyama
IPC分类号： H01L29/76
CPC分类号： H01L29/7802 , H01L29/0878 , H01L29/42372 , H01L29/4238 , H01L29/66712
摘要： An n type impurity region is provided below a gate electrode. By setting a gate length to be less than a depth of a channel region, a side surface of the channel region and a side surface of the n type impurity region adjacent to the channel region form a substantially perpendicular junction surface. Thus, since a depletion layer widens uniformly in a depth direction of a substrate, it is possible to secure a predetermined breakdown voltage. Furthermore, since an interval between the channel regions, above which the gate electrode is disposed, is uniform from its surface to its bottom, it is possible to increase an impurity concentration of the n type impurity region, resulting in an achievement of a low on-resistance.
摘要翻译：在栅电极的下方设置有n型杂质区。通过将栅极长度设置为小于沟道区的深度，沟道区的侧表面和与沟道区相邻的n型杂质区的侧表面形成基本上垂直的接合表面。因此，由于耗尽层在衬底的深度方向上均匀地变宽，因此可以确保预定的击穿电压。此外，由于栅极电极上方的沟道区域之间的间隔从表面到底部均匀，所以可以增加n型杂质区域的杂质浓度，导致实现低的导通 -抵抗性。

10. 发明授权

US08217486B2 Semiconductor device and method of processing the same 有权
标题翻译：半导体器件及其加工方法
公开(公告)号：US08217486B2
公开(公告)日：2012-07-10
申请号：US12236348
申请日：2008-09-23
申请人： Hiroyasu Ishida , Yasuyuki Sayama
发明人： Hiroyasu Ishida , Yasuyuki Sayama
IPC分类号： H01L27/00 , H01L21/20
CPC分类号： H01L21/76224 , H01L21/02381 , H01L21/0243 , H01L21/02439 , H01L21/02494 , H01L21/02521 , H01L21/02573 , H01L21/02587 , H01L21/02656 , H01L21/761 , H01L21/764 , H01L21/82 , H01L21/8222
摘要： Provided is a semiconductor wafer. In the semiconductor wafer, formation and etching of an n type epitaxial layer and formation and etching of a p type epitaxial layer are alternately performed for at least three times, so that all semiconductor layers are formed of epitaxial layers on a semiconductor substrate. Thereby, the respective semiconductor layers can be formed to have reduced widths. Thus, if a required breakdown voltage is the same, dopant concentrations of the respective semiconductor layers can be increased and a resistance value of the wafer can be reduced. In addition, a space portion remaining in the end is buried with an insulating layer, so that a defect can be avoided in a junction surface of the epitaxial layers.
摘要翻译：提供半导体晶片。在半导体晶片中，n型外延层的形成和蚀刻以及p型外延层的形成和蚀刻被交替执行至少三次，使得所有半导体层由半导体衬底上的外延层形成。由此，各个半导体层可以形成为具有减小的宽度。因此，如果所需的击穿电压相同，则可以增加各个半导体层的掺杂剂浓度，并且可以降低晶片的电阻值。此外，剩余的空间部分被绝缘层掩埋，使得在外延层的接合表面中可以避免缺陷。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式