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    • 1. 发明授权
      US08090064B2 Single loop frequency and phase detection 有权
    • Single loop frequency and phase detection
    • 单回路频率和相位检测
    • US08090064B2
    • 2012-01-03
    • US12022725
    • 2008-01-30
    • Hirotaka Tamura , Nikola Nedovic , William W. Walker
    • Hirotaka Tamura , Nikola Nedovic , William W. Walker
    • H04L7/00
    • H04L7/0338
    • In one embodiment, a method includes receiving a data signal comprising a plurality of bits. The method further includes generating a clock signal. A plurality of samples is acquired from the data signal at a sampling rate determined by the clock signal and it is determined whether a transition point from a first bit in the plurality of bits to a second bit in the plurality of bits occurs within the plurality of samples. If it is determined that the transition point occurs within the plurality of samples, a state machine comprising a plurality of states transitions from a first state to a second state. If the second state indicates a non-zero amount of phase displacement between the clock signal and the data signal, the clock signal is adjusted to correlate with the data signal.
    • 在一个实施例中，一种方法包括接收包括多个比特的数据信号。 该方法还包括产生时钟信号。 从数据信号以由时钟信号确定的采样率获取多个采样，并且确定在多个位中是否发生多个比特中的多个比特中的第一比特到第二比特的转换点 样品。 如果确定在多个样本内发生转换点，则包括多个状态的状态机从第一状态转变到第二状态。 如果第二状态指示时钟信号和数据信号之间的非零相位移量，则调整时钟信号以与数据信号相关。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 2. 发明申请
      US20080192873A1 Single Loop Frequency and Phase Detection 有权
    • Single Loop Frequency and Phase Detection
    • 单回路频率和相位检测
    • US20080192873A1
    • 2008-08-14
    • US12022725
    • 2008-01-30
    • Hirotaka Tamura , Nikola Nedovic , William W. Walker
    • Hirotaka Tamura , Nikola Nedovic , William W. Walker
    • H04L7/00
    • H04L7/0338
    • In one embodiment, a method includes receiving a data signal comprising a plurality of bits. The method further includes generating a clock signal. A plurality of samples is acquired from the data signal at a sampling rate determined by the clock signal and it is determined whether a transition point from a first bit in the plurality of bits to a second bit in the plurality of bits occurs within the plurality of samples. If it is determined that the transition point occurs within the plurality of samples, a state machine comprising a plurality of states transitions from a first state to a second state. If the second state indicates a non-zero amount of phase displacement between the clock signal and the data signal, the clock signal is adjusted to correlate with the data signal.
    • 在一个实施例中，一种方法包括接收包括多个比特的数据信号。 该方法还包括产生时钟信号。 从数据信号以由时钟信号确定的采样率获取多个采样，并且确定在多个位中是否发生多个比特中的多个比特中的第一比特到第二比特的转换点 样品。 如果确定在多个样本内发生转换点，则包括多个状态的状态机从第一状态转变到第二状态。 如果第二状态指示时钟信号和数据信号之间的非零相位移量，则调整时钟信号以与数据信号相关。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 3. 发明授权
      US08300754B2 Clock and data recovery with a data aligner 有权
    • Clock and data recovery with a data aligner
    • 使用数据对准器进行时钟和数据恢复
    • US08300754B2
    • 2012-10-30
    • US12510199
    • 2009-07-27
    • Nikola Nedovic , Nestor Tzartzanis , William W. Walker , Hirotaka Tamura
    • Nikola Nedovic , Nestor Tzartzanis , William W. Walker , Hirotaka Tamura
    • H04L7/00
    • H04J3/0685 , H03M9/00
    • In one embodiment, a method includes receiving first and second input streams comprising first and second input data bits, respectively. The method includes generating first and second recovered clocks based on the first and second input streams, respectively. The method includes retiming and demultiplexing the first and second input data bits to generate n first recovered streams and n second recovered streams, respectively, each comprising first and second recovered data bits, respectively. The method further includes determining a phase difference between the first and second recovered clocks; aligning the first recovered data bits with the second recovered data bits based at least in part on a value of n and the phase difference; combining the first and second recovered data bits to generate an output stream; and retiming the first and second recovered data bits in the output stream based on either the first or second recovered clock.
    • 在一个实施例中，一种方法包括分别接收包括第一和第二输入数据位的第一和第二输入流。 该方法包括分别基于第一和第二输入流产生第一和第二恢复时钟。 该方法包括对第一和第二输入数据位进行重新定时和解复用以分别产生n个第一恢复流和n个第二恢复流，每个包括第一和第二恢复数据位。 该方法还包括确定第一和第二恢复时钟之间的相位差; 至少部分地基于n的值和相位差将第一恢复数据位与第二恢复数据位对准; 组合第一和第二恢复数据比特以产生输出流; 以及基于所述第一恢复时钟或第二恢复时钟重新计时输出流中的第一和第二恢复数据比特。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 4. 发明申请
      US20100104057A1 Clock and Data Recovery with a Data Aligner 有权
    • Clock and Data Recovery with a Data Aligner
    • 使用数据对齐器进行时钟和数据恢复
    • US20100104057A1
    • 2010-04-29
    • US12510199
    • 2009-07-27
    • Nikola Nedovic , Nestor Tzartzanis , William W. Walker , Hirotaka Tamura
    • Nikola Nedovic , Nestor Tzartzanis , William W. Walker , Hirotaka Tamura
    • H04L7/02
    • H04J3/0685 , H03M9/00
    • In one embodiment, a method includes receiving first and second input streams comprising first and second input data bits, respectively. The method includes generating first and second recovered clocks based on the first and second input streams, respectively. The method includes retiming and demultiplexing the first and second input data bits to generate n first recovered streams and n second recovered streams, respectively, each comprising first and second recovered data bits, respectively. The method further includes determining a phase difference between the first and second recovered clocks; aligning the first recovered data bits with the second recovered data bits based at least in part on a value of n and the phase difference; combining the first and second recovered data bits to generate an output stream; and retiming the first and second recovered data bits in the output stream based on either the first or second recovered clock.
    • 在一个实施例中，一种方法包括分别接收包括第一和第二输入数据位的第一和第二输入流。 该方法包括分别基于第一和第二输入流产生第一和第二恢复时钟。 该方法包括对第一和第二输入数据位进行重新定时和解复用以分别产生n个第一恢复流和n个第二恢复流，每个包括第一和第二恢复数据位。 该方法还包括确定第一和第二恢复时钟之间的相位差; 至少部分地基于n的值和相位差将第一恢复数据位与第二恢复数据位对准; 组合第一和第二恢复数据比特以产生输出流; 以及基于所述第一恢复时钟或第二恢复时钟重新计时输出流中的第一和第二恢复数据比特。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 6. 发明授权
      US08204153B2 Clock recovery circuit and data receiving circuit 有权
    • Clock recovery circuit and data receiving circuit
    • 时钟恢复电路和数据接收电路
    • US08204153B2
    • 2012-06-19
    • US12400360
    • 2009-03-09
    • Hisakatsu Yamaguchi , Hirotaka Tamura
    • Hisakatsu Yamaguchi , Hirotaka Tamura
    • H03K9/00 , H04L27/00
    • H03L7/091 , G11C7/1078 , G11C7/1087 , G11C7/222 , H04L7/0331
    • A clock recovery circuit has a boundary detection circuit detecting a boundary in an input signal in accordance with a first signal, and performs recovery of a clock by controlling the timing of the first signal in accordance with the detected boundary. The clock recovery circuit has a boundary detection timing varying circuit and a variation reducing circuit. The boundary detection timing varying circuit dynamically varies boundary detection timing in the boundary detection circuit by applying a variation to the first signal, and the variation reducing circuit reduces a phase variation occurring in the recovered clock in accordance with the dynamic variation of the boundary detection timing performed by the boundary detection timing varying circuit.
    • 时钟恢复电路具有根据第一信号检测输入信号中的边界的边界检测电路，并且根据检测到的边界通过控制第一信号的定时来执行时钟的恢复。 时钟恢复电路具有边界检测定时改变电路和变化减小电路。 边界检测定时变化电路通过对第一信号施加变化动态地改变边界检测电路中的边界检测定时，并且变化减小电路根据边界检测定时的动态变化减少在恢复的时钟中发生的相位变化 由边界检测定时变化电路执行。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 10. 发明授权
      US07283601B2 Timing signal generating system and receiving circuit for transmitting signals at high speed with less circuitry 有权
    • Timing signal generating system and receiving circuit for transmitting signals at high speed with less circuitry
    • 定时信号发生系统和接收电路，用于以较少的电路高速传输信号
    • US07283601B2
    • 2007-10-16
    • US10077875
    • 2002-02-20
    • Hirotaka Tamura , Masaya Kibune
    • Hirotaka Tamura , Masaya Kibune
    • H03D3/24
    • G06F5/06 , G06F1/04 , H04L7/0012 , H04L7/005
    • A timing signal generating system has a clock signal generating circuit, a synchronizing circuit, a phase code recognizing circuit, and a calibration circuit. The clock signal generating circuit generates at least one first clock signal upon receipt of at least one reference clock signal by controlling an output phase thereof with a digital code signal. The synchronizing circuit hands over signals between a group of circuits operated by the first clock signal and an internal circuit operated by a second clock signal. The phase code recognizing circuit recognizes a phase code when the phases of the first clock signal and of the second clock signal are in a particular relationship. The calibration circuit calibrates a relationship between a value of the recognized phase code and a phase difference between the first and second clock signals. The synchronizing circuit is controlled by using phase code data calibrated by the calibration circuit.
    • 定时信号发生系统具有时钟信号发生电路，同步电路，相位代码识别电路和校准电路。 时钟信号发生电路在接收到至少一个参考时钟信号时，通过用数字代码信号控制其输出相位来产生至少一个第一时钟信号。 同步电路切换由第一时钟信号操作的一组电路与由第二时钟信号操作的内部电路之间的信号。 当第一时钟信号和第二时钟信号的相位处于特定关系时，相位代码识别电路识别相位代码。 校准电路校准识别的相位码的值与第一和第二时钟信号之间的相位差之间的关系。 通过使用由校准电路校准的相位代码数据来控制同步电路。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
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