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1. 发明申请

US20080192873A1 Single Loop Frequency and Phase Detection 有权
标题翻译：单回路频率和相位检测
公开(公告)号：US20080192873A1
公开(公告)日：2008-08-14
申请号：US12022725
申请日：2008-01-30
申请人： Hirotaka Tamura , Nikola Nedovic , William W. Walker
发明人： Hirotaka Tamura , Nikola Nedovic , William W. Walker
IPC分类号： H04L7/00
CPC分类号： H04L7/0338
摘要： In one embodiment, a method includes receiving a data signal comprising a plurality of bits. The method further includes generating a clock signal. A plurality of samples is acquired from the data signal at a sampling rate determined by the clock signal and it is determined whether a transition point from a first bit in the plurality of bits to a second bit in the plurality of bits occurs within the plurality of samples. If it is determined that the transition point occurs within the plurality of samples, a state machine comprising a plurality of states transitions from a first state to a second state. If the second state indicates a non-zero amount of phase displacement between the clock signal and the data signal, the clock signal is adjusted to correlate with the data signal.
摘要翻译：在一个实施例中，一种方法包括接收包括多个比特的数据信号。该方法还包括产生时钟信号。从数据信号以由时钟信号确定的采样率获取多个采样，并且确定在多个位中是否发生多个比特中的多个比特中的第一比特到第二比特的转换点样品。如果确定在多个样本内发生转换点，则包括多个状态的状态机从第一状态转变到第二状态。如果第二状态指示时钟信号和数据信号之间的非零相位移量，则调整时钟信号以与数据信号相关。

2. 发明授权

US08090064B2 Single loop frequency and phase detection 有权
标题翻译：单回路频率和相位检测
公开(公告)号：US08090064B2
公开(公告)日：2012-01-03
申请号：US12022725
申请日：2008-01-30
申请人： Hirotaka Tamura , Nikola Nedovic , William W. Walker
发明人： Hirotaka Tamura , Nikola Nedovic , William W. Walker
IPC分类号： H04L7/00
CPC分类号： H04L7/0338
摘要： In one embodiment, a method includes receiving a data signal comprising a plurality of bits. The method further includes generating a clock signal. A plurality of samples is acquired from the data signal at a sampling rate determined by the clock signal and it is determined whether a transition point from a first bit in the plurality of bits to a second bit in the plurality of bits occurs within the plurality of samples. If it is determined that the transition point occurs within the plurality of samples, a state machine comprising a plurality of states transitions from a first state to a second state. If the second state indicates a non-zero amount of phase displacement between the clock signal and the data signal, the clock signal is adjusted to correlate with the data signal.
摘要翻译：在一个实施例中，一种方法包括接收包括多个比特的数据信号。该方法还包括产生时钟信号。从数据信号以由时钟信号确定的采样率获取多个采样，并且确定在多个位中是否发生多个比特中的多个比特中的第一比特到第二比特的转换点样品。如果确定在多个样本内发生转换点，则包括多个状态的状态机从第一状态转变到第二状态。如果第二状态指示时钟信号和数据信号之间的非零相位移量，则调整时钟信号以与数据信号相关。

3. 发明授权

US08300754B2 Clock and data recovery with a data aligner 有权
标题翻译：使用数据对准器进行时钟和数据恢复
公开(公告)号：US08300754B2
公开(公告)日：2012-10-30
申请号：US12510199
申请日：2009-07-27
申请人： Nikola Nedovic , Nestor Tzartzanis , William W. Walker , Hirotaka Tamura
发明人： Nikola Nedovic , Nestor Tzartzanis , William W. Walker , Hirotaka Tamura
IPC分类号： H04L7/00
CPC分类号： H04J3/0685 , H03M9/00
摘要： In one embodiment, a method includes receiving first and second input streams comprising first and second input data bits, respectively. The method includes generating first and second recovered clocks based on the first and second input streams, respectively. The method includes retiming and demultiplexing the first and second input data bits to generate n first recovered streams and n second recovered streams, respectively, each comprising first and second recovered data bits, respectively. The method further includes determining a phase difference between the first and second recovered clocks; aligning the first recovered data bits with the second recovered data bits based at least in part on a value of n and the phase difference; combining the first and second recovered data bits to generate an output stream; and retiming the first and second recovered data bits in the output stream based on either the first or second recovered clock.
摘要翻译：在一个实施例中，一种方法包括分别接收包括第一和第二输入数据位的第一和第二输入流。该方法包括分别基于第一和第二输入流产生第一和第二恢复时钟。该方法包括对第一和第二输入数据位进行重新定时和解复用以分别产生n个第一恢复流和n个第二恢复流，每个包括第一和第二恢复数据位。该方法还包括确定第一和第二恢复时钟之间的相位差; 至少部分地基于n的值和相位差将第一恢复数据位与第二恢复数据位对准; 组合第一和第二恢复数据比特以产生输出流; 以及基于所述第一恢复时钟或第二恢复时钟重新计时输出流中的第一和第二恢复数据比特。

4. 发明申请

US20100104057A1 Clock and Data Recovery with a Data Aligner 有权
标题翻译：使用数据对齐器进行时钟和数据恢复
公开(公告)号：US20100104057A1
公开(公告)日：2010-04-29
申请号：US12510199
申请日：2009-07-27
申请人： Nikola Nedovic , Nestor Tzartzanis , William W. Walker , Hirotaka Tamura
发明人： Nikola Nedovic , Nestor Tzartzanis , William W. Walker , Hirotaka Tamura
IPC分类号： H04L7/02
CPC分类号： H04J3/0685 , H03M9/00
摘要： In one embodiment, a method includes receiving first and second input streams comprising first and second input data bits, respectively. The method includes generating first and second recovered clocks based on the first and second input streams, respectively. The method includes retiming and demultiplexing the first and second input data bits to generate n first recovered streams and n second recovered streams, respectively, each comprising first and second recovered data bits, respectively. The method further includes determining a phase difference between the first and second recovered clocks; aligning the first recovered data bits with the second recovered data bits based at least in part on a value of n and the phase difference; combining the first and second recovered data bits to generate an output stream; and retiming the first and second recovered data bits in the output stream based on either the first or second recovered clock.
摘要翻译：在一个实施例中，一种方法包括分别接收包括第一和第二输入数据位的第一和第二输入流。该方法包括分别基于第一和第二输入流产生第一和第二恢复时钟。该方法包括对第一和第二输入数据位进行重新定时和解复用以分别产生n个第一恢复流和n个第二恢复流，每个包括第一和第二恢复数据位。该方法还包括确定第一和第二恢复时钟之间的相位差; 至少部分地基于n的值和相位差将第一恢复数据位与第二恢复数据位对准; 组合第一和第二恢复数据比特以产生输出流; 以及基于所述第一恢复时钟或第二恢复时钟重新计时输出流中的第一和第二恢复数据比特。

5. 发明授权

US08138798B2 Symmetric phase detector 失效
标题翻译：对称相位检测器
公开(公告)号：US08138798B2
公开(公告)日：2012-03-20
申请号：US12511340
申请日：2009-07-29
申请人： Nikola Nedovic , H. Anders Kristensson , William W. Walker
发明人： Nikola Nedovic , H. Anders Kristensson , William W. Walker
IPC分类号： G01R25/00 , H03D13/00
CPC分类号： H03D13/008 , H03L7/085 , H03L7/089
摘要： In one embodiment, a circuit includes a first circuit input for receiving a first input signal having a first phase; a second circuit input for receiving a second input signal having a second phase; a circuit output for outputting a circuit output signal; a first mixer cell comprising a first mixer cell input, a second mixer cell input, and a first mixer cell output; and a second mixer cell comprising a third mixer cell input, a fourth mixer cell input, and a second mixer cell output. The first circuit input is connected to the first and second mixer cell inputs, the second circuit input is connected to the second and fourth mixer cell inputs, and the first and second mixer cell outputs are combined to provide the circuit output. The current of the circuit output signal is proportional to a phase offset between the first and second phases.
摘要翻译：在一个实施例中，电路包括用于接收具有第一相位的第一输入信号的第一电路输入端; 用于接收具有第二相位的第二输入信号的第二电路输入; 用于输出电路输出信号的电路输出; 第一混频器单元，包括第一混频器单元输入，第二混频器单元输入和第一混频器单元输出; 以及包括第三混频器单元输入，第四混频器单元输入和第二混频器单元输出的第二混频器单元。第一电路输入连接到第一和第二混频器单元输入，第二电路输入连接到第二和第四混频器单元输入，并且组合第一和第二混频器单元输出以提供电路输出。电路输出信号的电流与第一和第二相之间的相位偏移成比例。

6. 发明授权

US08058914B2 Generating multiple clock phases 有权
标题翻译：生成多个时钟阶段
公开(公告)号：US08058914B2
公开(公告)日：2011-11-15
申请号：US12511352
申请日：2009-07-29
申请人： H. Anders Kristensson , Nestor Tzartzanis , Nikola Nedovic , William W. Walker
发明人： H. Anders Kristensson , Nestor Tzartzanis , Nikola Nedovic , William W. Walker
IPC分类号： H03L7/06
CPC分类号： H03L7/085 , H03L7/099 , H03L7/0998 , H04L7/0025 , H04L7/0337
摘要： In one embodiment, a circuit includes a first circuit input for receiving a first reference signal having a first phase; a second circuit input for receiving a second reference signal having a second phase; a third circuit input for receiving a target phase signal; a circuit output for outputting an output signal; a first multiplying mixer cell (MMC) comprising a first MMC input, a second MMC input, and a first MMC output; a second MMC comprising a third MMC input, a fourth MMC input, and a second MMC output. In an example embodiment, the first circuit input is connected to the first MMC input; the second circuit input is connected to the third MMC input; the third circuit input is connected to the second MMC input and the fourth MMC input; the first MMC output and the second MMC output are combined with each other to provide the circuit output; and the output signal, when present, represents an error signal that is proportional to a phase difference between a phase of the target phase signal and an average of the first and second phases.
摘要翻译：在一个实施例中，电路包括用于接收具有第一相位的第一参考信号的第一电路输入端; 用于接收具有第二相位的第二参考信号的第二电路输入; 用于接收目标相位信号的第三电路输入; 用于输出输出信号的电路输出; 包括第一MMC输入，第二MMC输入和第一MMC输出的第一乘法混频器单元（MMC）; 第二MMC，包括第三MMC输入，第四MMC输入和第二MMC输出。在示例性实施例中，第一电路输入连接到第一MMC输入; 第二个电路输入连接到第三个MMC输入端; 第三电路输入连接到第二MMC输入和第四MMC输入; 第一MMC输出和第二MMC输出相互组合以提供电路输出; 并且当存在时，输出信号表示与目标相位信号的相位与第一和第二相位的平均值之间的相位差成比例的误差信号。

7. 发明授权

US06693459B2 Method and system for improving speed in a flip-flop 有权
标题翻译：用于提高触发器速度的方法和系统
公开(公告)号：US06693459B2
公开(公告)日：2004-02-17
申请号：US10045179
申请日：2002-01-11
申请人： Nikola Nedovic , Vojin G. Oklobd{haeck over (z)}ija , William W. Walker
发明人： Nikola Nedovic , Vojin G. Oklobd{haeck over (z)}ija , William W. Walker
IPC分类号： H03K19096
CPC分类号： H03K3/012 , H03K3/356139
摘要： The present invention provides techniques, including a system and method, for improving speed in a flip-flop, having a pre-charged stage coupled to an evaluation stage. In one exemplary embodiment delay is reduced by using a conditional rather than an unconditional keeper, where the conditional keeper has the function of a keeper only under certain conditions. In some embodiments there is a conditional keeper in either the pre-charged stage or the evaluation stage or both stages. Another embodiment provides for the combining of the evaluation stage with one or more external logic functions.
摘要翻译：本发明提供了一种技术，包括用于提高触发器中的速度的系统和方法，其具有耦合到评估级的预充电级。在一个示例性实施例中，通过使用条件而不是无条件守门员来减少延迟，其中条件保持者仅在某些条件下具有保持者的功能。在一些实施例中，在预充电阶段或评估阶段或两个阶段中存在条件保持器。另一个实施例提供了评估阶段与一个或多个外部逻辑功能的组合。

8. 发明申请

US20120023380A1 ALGORITHMIC MATCHING OF A DESKEW CHANNEL 有权
标题翻译： DESKEW频道的算法匹配
公开(公告)号：US20120023380A1
公开(公告)日：2012-01-26
申请号：US12840985
申请日：2010-07-21
申请人： Samir Parikh , Nikola Nedovic , William W. Walker
发明人： Samir Parikh , Nikola Nedovic , William W. Walker
IPC分类号： G06F11/07
CPC分类号： H04L25/14
摘要： In one embodiment, a method includes receiving input data bits over data channels; receiving deskew channel bits constituting frames that each comprise ones of the input data bits; determining frame boundaries; mapping each of the input data bits in each of the frames to one of the data channels; for each set of the frames, comparing the input data bits in the set with the input data bits in the corresponding input data words; determining relative delays among the data channels and the deskew channel; when non-zero delays are determined, rearranging the input data bits to reduce the delays; and when it is determined that one or more of the data channels have a delay of greater than a predetermined number of data-channel clock periods relative to a particular data channel, delaying input data bits in the particular data channel by an additional number of input data bits.
摘要翻译：在一个实施例中，一种方法包括：通过数据信道接收输入数据位; 接收构成每个包括所述输入数据位中的一个的帧的歪斜通道位; 确定帧边界; 将每个帧中的每个输入数据位映射到数据信道之一; 对于每组帧，将该组中的输入数据位与相应输入数据字中的输入数据位进行比较; 确定数据通道和歪斜通道之间的相对延迟; 当确定非零延迟时，重新排列输入数据位以减少延迟; 并且当确定一个或多个数据信道相对于特定数据信道具有大于预定数量的数据信道时钟周期的延迟时，通过附加数量的输入来延迟特定数据信道中的输入数据位数据位。

9. 发明申请

US20100085086A1 Digital Frequency Detector 审中-公开
标题翻译：数字频率检测器
公开(公告)号：US20100085086A1
公开(公告)日：2010-04-08
申请号：US12510211
申请日：2009-07-27
申请人： Nikola Nedovic , Nestor Tzartzanis , William W. Walker
发明人： Nikola Nedovic , Nestor Tzartzanis , William W. Walker
IPC分类号： H03B19/00
CPC分类号： H03L7/091 , H03L7/099 , H03L7/10 , H03L2207/06 , H04L7/033
摘要： In one embodiment, a method is described that includes receiving a first clock signal and a second clock signal; dividing the first clock signal by a value of n to generate a divided first clock signal; sampling the frequency detector the divided first clock signal with the second clock signal to generate a plurality of samples; generating a first adjustment signal if more than a predetermined number of consecutive samples in a set of consecutive samples have identical logical values; and generating a second adjustment signal if less than the predetermined number of consecutive samples in the set of consecutive samples have identical logical values.
摘要翻译：在一个实施例中，描述了一种包括接收第一时钟信号和第二时钟信号的方法; 将第一时钟信号除以n的值以产生分割的第一时钟信号; 对所述分频的第一时钟信号与所述第二时钟信号对所述频率检测器进行采样以产生多个采样; 如果一组连续样本中多于一个预定数量的连续样本具有相同的逻辑值，则产生第一调整信号; 以及如果小于所述连续样本集合中的预定数量的连续样本具有相同的逻辑值，则产生第二调整信号。

10. 发明授权

US07629817B2 System and apparatus for aperture time improvement 有权
标题翻译：孔径时间改进的系统和装置
公开(公告)号：US07629817B2
公开(公告)日：2009-12-08
申请号：US11960290
申请日：2007-12-19
申请人： Nikola Nedovic , William W. Walker
发明人： Nikola Nedovic , William W. Walker
IPC分类号： G01R19/00
CPC分类号： H03K3/356139 , H03K17/6871
摘要： In particular embodiments, an apparatus includes a first transistor connected at the gate to a first input signal voltage and a second transistor connected at the gate to a second input signal voltage. The apparatus further includes a deactivation element coupled to the transistors, the deactivation element being operable to deactivate the first and second transistors by selectively transmitting a deactivation current to a first terminal of the first transistor and a second terminal of the second transistor thereby raising a voltage on the first and second terminals to a value large enough to deactivate the first and second transistors. In particular embodiments, activating the first or second transistor transmits a signal from the apparatus and deactivating the first and second transistors prevents the signal from being transmitted from the apparatus.
摘要翻译：在具体实施例中，一种装置包括在栅极处连接到第一输入信号电压的第一晶体管和在栅极处连接到第二输入信号电压的第二晶体管。该装置还包括耦合到晶体管的去激活元件，去激活元件可操作以通过选择性地将去激活电流传输到第一晶体管的第一端子和第二晶体管的第二端子而使第一和第二晶体管去激活，从而提高电压在第一和第二端子上达到足够大以使第一和第二晶体管去激活的值。在特定实施例中，激活第一或第二晶体管传输来自装置的信号，并且去激活第一和第二晶体管防止信号从装置传输。

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