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1. 发明授权

US4884120A Semiconductor device and method for making the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US4884120A
公开(公告)日：1989-11-28
申请号：US16787
申请日：1987-02-20
申请人： Hiroshi Mochizuki , Reiji Tamaki , Junichi Arima , Masaaki Ikegami , Eisuke Tanaka , Kenji Saito
发明人： Hiroshi Mochizuki , Reiji Tamaki , Junichi Arima , Masaaki Ikegami , Eisuke Tanaka , Kenji Saito
IPC分类号： H01L23/522 , H01L21/28 , H01L21/316 , H01L21/768 , H01L27/00 , H01L29/49
CPC分类号： H01L21/31683 , H01L21/7684 , H01L21/76877 , H01L21/76888
摘要： An improved interconnection structure and method for forming the interconnection in a semiconductor device having multilayered interconnection structure in which a contact hole for electrically connecting a first layer interconnection to a predetermined region of a semiconductor substrate and a through hole for electrically connecting a second layer interconnection to the first layer interconnection are formed in the regions overlapping with each other in planer layout. In the interconnection structure of the present invention, hillocks effective to compensate for the contact hole step are formed in the first layer interconnection only in the region of the contact hole of the first layer interconnection. In the method for forming the interconnection according to the present invention, a first layer interconnection is formed and a chemical conversion process is selectively performed to form a film which is more rigid than the first layer interconnection film on a predetermined region of the first layer interconnection film, and then a heat process is performed to generate hillocks only at the region of the contact hole of the first layer interconnection film. The second layer interconnection film is formed thereafter.
摘要翻译：一种用于在具有多层互连结构的半导体器件中形成互连的改进的互连结构和方法，其中用于将第一层互连电连接到半导体衬底的预定区域的接触孔和用于将第二层互连电连接到第一层互连形成在以平面布置彼此重叠的区域中。在本发明的互连结构中，仅在第一层互连的接触孔的区域中，在第一层互连中形成有效补偿接触孔台阶的小丘。在根据本发明的形成互连的方法中，形成第一层互连，并且选择性地执行化学转换处理以在第一层互连的预定区域上形成比第一层互连膜更刚性的膜膜，然后进行热处理，仅在第一层互连膜的接触孔的区域产生小丘。此后形成第二层互连膜。

2. 发明授权

US6130481A Semiconductor integrated circuit interconnection structures and method of making the interconnection structures 失效
公开(公告)号：US6130481A
公开(公告)日：2000-10-10
申请号：US959457
申请日：1997-10-28
申请人： Shigeru Harada , Kenji Kishibe , Akira Ihisa , Hiroshi Mochizuki , Eisuke Tanaka
发明人： Shigeru Harada , Kenji Kishibe , Akira Ihisa , Hiroshi Mochizuki , Eisuke Tanaka
IPC分类号： H01L21/768 , H01L23/522 , H01L23/532 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/76801 , H01L21/76804 , H01L21/76814 , H01L21/76828 , H01L21/76832 , H01L21/76834 , H01L21/76837 , H01L23/5226 , H01L23/53223 , H01L2924/0002 , Y10S257/901 , Y10S257/904 , Y10S257/908 , Y10S257/915
摘要： A semiconductor integrated circuit structure includes a semiconductor substrate; an electronic element disposed in the substrate; a first electrically insulating layer disposed on the substrate and the electronic element; a first electrically conducting interconnection layer electrically connected to the electronic element and disposed at least partly on the first electrically insulating layer; a second electrically insulating layer disposed on the first electrically conducting interconnection layer; a second electrically conducting interconnection layer disposed on the second electrically insulating layer; and a through-hole penetrating the second electrically insulating layer to the first electrically conducting interconnection layer, part of the second interconnection layer being disposed within the through-hole and contacting the first electrically conducting interconnection layer wherein the first electrically conducting interconnection layer includes a current barrier including at least one opening in the first electrically conducting interconnection layer proximate the through-hole extending to the first electrically insulating layer and filled with part of the second electrically insulating layer, constraining current flowing between the first and second electrically conducting interconnection layers to flow around the current barrier.A method of making a semiconductor integrated circuit interconnection structure includes forming an active electronic element in a semiconductor substrate; forming a first electrically insulating layer on the electronic element and the semiconductor substrate; forming a first electrically conducting interconnection layer electrically connected to the electronic element, at least partially disposed on the first electrically insulating layer, and including at least one opening extending to the first electrically insulating layer; forming a second electrically insulating layer on the first electrically conducting interconnection layer and filling the opening, thereby forming a barrier to the flow of current in a region of the first electrically conducting interconnection layer; forming a throughhole extending through the second electrically insulating layer to the first electrically conducting interconnection layer proximate the opening; and depositing a second electrically conducting interconnection layer on the second electrically insulating layer and in the through-hole, electrically contacting the first electrically conducting interconnection layer.

3. 发明授权

US5712509A Semiconductor integrated circuit interconnection structures 失效
标题翻译：半导体集成电路互连结构
公开(公告)号：US5712509A
公开(公告)日：1998-01-27
申请号：US873015
申请日：1992-04-24
申请人： Shigeru Harada , Kenji Kishibe , Akira Ohisa , Hiroshi Mochizuki , Eisuke Tanaka
发明人： Shigeru Harada , Kenji Kishibe , Akira Ohisa , Hiroshi Mochizuki , Eisuke Tanaka
IPC分类号： H01L21/768 , H01L23/522 , H01L23/532 , H01L23/48 , H01L23/52
CPC分类号： H01L21/76801 , H01L21/76804 , H01L21/76814 , H01L21/76828 , H01L21/76832 , H01L21/76834 , H01L21/76837 , H01L23/5226 , H01L23/53223 , H01L2924/0002 , Y10S257/901 , Y10S257/904 , Y10S257/908 , Y10S257/915
摘要： A semiconductor integrated circuit structure includes a semiconductor substrate; an electronic element disposed in the substrate; a first electrically insulating layer disposed on the substrate and the electronic element; a first electrically conducting interconnection layer electrically connected to the electronic element and disposed at least partly on the first electrically insulating layer; a second electrically insulating layer disposed on the first electrically conducting interconnection layer; a second electrically conducting interconnection layer disposed on the second electrically insulating layer; and a through-hole penetrating the second electrically insulating layer to the first electrically conducting interconnection layer, part of the second interconnection layer being disposed within the through-hole and contacting the first electrically conducting interconnection layer wherein the first electrically conducting interconnection layer includes a current barrier including at least one opening in the first electrically conducting interconnection layer proximate the through-hole extending to the first electrically insulating layer and filled with part of the second electrically insulating layer, constraining current flowing between the first and second electrically conducting interconnection layers to flow around the current barrier.
摘要翻译：半导体集成电路结构包括半导体衬底; 设置在所述基板中的电子元件; 设置在所述基板和所述电子元件上的第一电绝缘层; 电连接到所述电子元件并且至少部分地设置在所述第一电绝缘层上的第一导电互连层; 设置在所述第一导电互连层上的第二电绝缘层; 设置在所述第二电绝缘层上的第二导电互连层; 以及穿过所述第二电绝缘层到所述第一导电互连层的通孔，所述第二互连层的一部分设置在所述通孔内并与所述第一导电互连层接触，其中所述第一导电互连层包括电流阻挡层，包括靠近通孔延伸到第一电绝缘层的第一导电互连层中的至少一个开口，并填充有第二电绝缘层的一部分，约束在第一和第二导电互连层之间流动的电流流动围绕当前的障碍。

4. 发明授权

US10173441B2 Apparatus for processing media 有权
公开(公告)号：US10173441B2
公开(公告)日：2019-01-08
申请号：US15635806
申请日：2017-06-28
申请人： Naoto Takeshita , Tetsuya Noda , Yasutake Ohshiro , Hiroaki Moroboshi , Hiroshi Mochizuki
发明人： Naoto Takeshita , Tetsuya Noda , Yasutake Ohshiro , Hiroaki Moroboshi , Hiroshi Mochizuki
IPC分类号： B41J11/00
摘要： The present invention is to provide a media processing apparatus for enabling a plurality of discharge sections disposed one side of the apparatus to be disposed parallel inside saved space, the media processing apparatus is provided with a plurality of discharge sections (correct card discharge section and error card discharge section) disposed on one side of an apparatus housing, and a discharge member (card reverse section) that discharges a card C to each discharge section. In such a card processing apparatus, a width dimension (length dimension in the discharge direction of the card) of a discharge stacker of the first card discharge section is wider than a width dimension of the card C, and a width dimension of a frame body of the error card discharge section is narrower than the width dimension of the card C.

5. 发明授权

US08654164B2 Printing device and printing method 有权
标题翻译：印刷装置和印刷方式
公开(公告)号：US08654164B2
公开(公告)日：2014-02-18
申请号：US13497685
申请日：2010-09-24
申请人： Hiroshi Mochizuki , Yuichi Aihara , Tsuyoshi Kubota
发明人： Hiroshi Mochizuki , Yuichi Aihara , Tsuyoshi Kubota
IPC分类号： B41J2/325
CPC分类号： B41J2/325 , B41J2/0057 , B41J17/02
摘要： The present invention provides a printing device which provides high printing quality. The printing device includes: an image forming section which has a thermal head 9 and a platen roller 12; a media conveyance section for conveying an intermediate transfer film F; a ribbon conveyance section for conveying an ink ribbon R; a sensor 10 for detecting a first mark formed on the film F; and a control section for controlling the image forming section, the media conveyance section, and the ribbon conveyance section in accordance with output information from the sensor 10. The control section presses the head 9 into contact with the roller 12 when the first mark is not detected, which is when the first mark is further upstream than the position of the sensor 10, while the film F and the ribbon R are being conveyed, and selectively heats a heating element formed in the head 9 when the film F is positioned in the printing start position, which is a state in which the first mark is detected when the first mark is further downstream than the position of the sensor 10.
摘要翻译：本发明提供一种提供高打印质量的打印装置。打印装置包括：具有热敏头9和压纸辊12的图像形成部分; 用于输送中间转印膜F的介质输送部; 用于输送墨带R的色带传送部; 用于检测形成在胶片F上的第一标记的传感器10; 以及根据来自传感器10的输出信息来控制图像形成部分，介质传送部分和色带传送部分的控制部分。当第一标记不是时，控制部分将头部9按压与辊12接触当胶片F和色带R被输送时，当第一标记比传感器10的位置更上游时，检测到该位置，并且当胶片F位于该位置时，选择性地加热形成在头部9中的加热元件打印开始位置，其是当第一标记比传感器10的位置更下游时检测到第一标记的状态。

6. 发明申请

US20080312544A1 Sphygmomanometer 有权
标题翻译：血压计
公开(公告)号：US20080312544A1
公开(公告)日：2008-12-18
申请号：US11662207
申请日：2005-09-12
申请人： Hiroshi Mochizuki
发明人： Hiroshi Mochizuki
IPC分类号： A61B5/0225
CPC分类号： A61B5/02225 , A61B5/02116 , A61B5/022 , A61B5/02233
摘要： The objective of the present invention is to provide a sphygmomanometer that is easy to use. The sphygmomanometer according to the present invention measures blood pressure in accordance with an oscillation in an artery wall, resulting from an arterial pulse correspondent with a change in cuff pressure. It comprises a cuff that is connected to the sphygmomanometer main body by a tube, a display unit for displaying the results of blood pressure measurements, and an air supply unit for supplying air to, and thus pressurizing, the cuff, which is detachable from the sphygmomanometer main body. The air supply unit is screwed into the sphygmomanometer main body with a screw assembly, and the screwed-in state is preserved by a caulking ring. The air supply unit also comprises a filter for keeping dust from entering the sphygmomanometer main body.
摘要翻译：本发明的目的是提供一种易于使用的血压计。根据本发明的血压计根据与袖带压力的变化相对应的动脉脉搏导致的动脉壁的振动来测量血压。其包括通过管连接到血压计主体的袖带，用于显示血压测量结果的显示单元，以及用于向袖带提供空气并因此加压袖带的空气供应单元，该袖带可从血压计主体。空气供给单元用螺钉组件拧入血压计主体，并且螺纹固定状态由填缝环保持。空气供给单元还包括用于防止灰尘进入血压计主体的过滤器。

7. 发明授权

US07354403B2 Cuff apparatus and sphygmomanometer comprising the same 失效
标题翻译：袖带装置和包括其的血压计
公开(公告)号：US07354403B2
公开(公告)日：2008-04-08
申请号：US10764507
申请日：2004-01-27
申请人： Hiroshi Mochizuki
发明人： Hiroshi Mochizuki
IPC分类号： A61B5/02
CPC分类号： A61B5/02208 , A61B5/02141 , A61B5/02233
摘要： A plurality of cushions are provided in the airbag of a cuff apparatus, spaced apart from one another and thus maintaining the airbag in an inflated state before compressed air is introduced into the airbag. This shortens the time required to supply the compressed air and minimizes the resistance to the body part being inserted into the cuff apparatus. Therefore, the body part can smoothly enter the cuff apparatus and the flow of blood can be sufficiently suppressed.
摘要翻译：在袖带装置的气囊中设置有多个垫子，彼此间隔开，并且在压缩空气被引入到气囊中之前将气囊保持在膨胀状态。这缩短了供应压缩空气所需的时间，并且使对插入袖带装置的身体部分的抵抗力最小化。因此，能够顺利地进入袖带装置，能够充分抑制血液流动。

8. 发明授权

US06750093B2 Semiconductor integrated circuit and method for manufacturing the same 失效
标题翻译：半导体集成电路及其制造方法
公开(公告)号：US06750093B2
公开(公告)日：2004-06-15
申请号：US10310954
申请日：2002-12-06
申请人： Hiroyuki Kanaya , Osamu Hidaka , Kumi Okuwada , Hiroshi Mochizuki
发明人： Hiroyuki Kanaya , Osamu Hidaka , Kumi Okuwada , Hiroshi Mochizuki
IPC分类号： H01L218242
CPC分类号： H01L27/11502 , H01L27/11507
摘要： A semiconductor integrated circuit has a ferroelectric capacitor. The ferroelectric capacitor includes a first insulation film formed above a semiconductor substrate, a first electrode which is buried in a fist hole formed in the first insulation film and whose surface is flattened, a second insulation film formed above the first insulation film and having a second hole above the first electrode, a ferroelectric film formed in the second hole, and a second electrode formed in the second hole and above the ferroelectric film and flattened so as to be flush with a surface of the second insulation film.
摘要翻译：半导体集成电路具有铁电电容器。铁电电容器包括形成在半导体衬底上的第一绝缘膜，第一电极，其被埋在形成在第一绝缘膜中并且其表面平坦化的第一孔中;第二绝缘膜，形成在第一绝缘膜上方，并具有第二绝缘膜在第二孔中形成的铁电膜，形成在第二孔中并在铁电体膜上方的第二电极，并且与第二绝缘膜的表面齐平。

9. 发明授权

US06190957B1 Method of forming a ferroelectric device 失效
标题翻译：形成铁电体器件的方法
公开(公告)号：US06190957B1
公开(公告)日：2001-02-20
申请号：US09324501
申请日：1999-06-02
申请人： Hiroshi Mochizuki , Kumi Okuwada , Hiroyuki Kanaya , Osamu Hidaka , Susumu Shuto , Iwao Kunishima
发明人： Hiroshi Mochizuki , Kumi Okuwada , Hiroyuki Kanaya , Osamu Hidaka , Susumu Shuto , Iwao Kunishima
IPC分类号： H01L218242
CPC分类号： H01L27/11507 , H01L21/76895 , H01L27/10852 , H01L27/11502 , H01L28/55
摘要： A method of manufacturing a semiconductor apparatus comprises the steps of forming, on a surface of a semiconductor substrate, an MIS transistor including a drain region and a source region each formed of an impurity diffusion region, forming an insulation film on the semiconductor substrate after the MIS transistor has been formed, selectively forming contact holes in the insulation film, embedding, into the contact hole, a capacitor contact plug having a lower end which is in contact with one of the drain region and the source region of the MIS transistor, forming a ferroelectric capacitor having a lower electrode, a ferroelectric film and an upper electrode on the insulation film after the capacitor contact plug has been formed, and forming an electric wire for establishing a connection between the upper electrode of the ferroelectric capacitor and an upper surface of the capacitor contact plug.
摘要翻译：一种制造半导体器件的方法包括以下步骤：在半导体衬底的表面上形成包括漏区和源区的MIS晶体管，所述漏极区和源区各自由杂质扩散区形成，在所述半导体衬底之后形成绝缘膜 MIS晶体管已经形成，在绝缘膜中选择性地形成接触孔，将接触孔埋入电容器接触插塞中，该电容器接触插塞的下端与MIS晶体管的漏极区域和源极区域中的一个接触，形成在形成电容器接触插塞之后，在绝缘膜上形成具有下电极，铁电体膜和上电极的铁电电容器，并且形成用于建立铁电电容器的上电极和上电极之间的连接的电线电容器接触插头。

10. 外观设计

USD356377S Electronic sphygmomanometer 失效
公开(公告)号：USD356377S
公开(公告)日：1995-03-14
申请号：US17308
申请日：1994-01-10
申请人： Jun Tsubota , Hiroshi Mochizuki
设计人： Jun Tsubota , Hiroshi Mochizuki

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