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1. 发明申请

US20090230510A1 SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20090230510A1
公开(公告)日：2009-09-17
申请号：US12400553
申请日：2009-03-09
申请人： Hiroshi Miki , Tomoko Sekiguchi , Naomi Inada , Mitsuhiro Horikawa
发明人： Hiroshi Miki , Tomoko Sekiguchi , Naomi Inada , Mitsuhiro Horikawa
IPC分类号： H01L29/92 , H01L21/02 , H01L21/31 , H01L27/108
CPC分类号： H01L21/02186 , C23C16/40 , C23C16/45531 , H01L21/02175 , H01L21/02194 , H01L21/0228 , H01L21/3141 , H01L27/10817 , H01L27/10852 , H01L28/91
摘要： A rutile phase can be formed even in the case of a thin film by adding nickel or cobalt to titanium dioxide in the range of 0.5 to 10 atm %, and the use of this element-added titanium dioxide film in a capacitor dielectric film results in an increase in capacitance per unit area of a DRAM memory cell and enables a high-integration DRAM to be realized at low cost.
摘要翻译：即使在0.5〜10atm％的二氧化钛中添加镍或钴，也可以形成金红石相，在电容器用电介质膜中使用该元素添加二氧化钛膜 DRAM存储单元的每单位面积的电容增加，能够以低成本实现高集成度的DRAM。

2. 发明授权

US07247890B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07247890B2
公开(公告)日：2007-07-24
申请号：US10931119
申请日：2004-09-01
申请人： Tomoko Sekiguchi , Shinichiro Kimura , Renichi Yamada , Kikuo Watanabe , Hiroshi Miki , Kenichi Takeda
发明人： Tomoko Sekiguchi , Shinichiro Kimura , Renichi Yamada , Kikuo Watanabe , Hiroshi Miki , Kenichi Takeda
IPC分类号： H01L31/0328 , H01L29/80
CPC分类号： H01L29/66659 , H01L27/10855 , H01L27/10873 , H01L27/10894 , H01L29/1079 , H01L29/6656 , H01L29/7835
摘要： Disclosed is herein a semiconductor device having a DRAM with less scattering of threshold voltage of MISFET in a memory cell and having good charge retainability of a capacitor, and a manufacturing method of the semiconductor device. An anti-oxidation film is formed to the side wall of a gate electrode before light oxidation thereby suppressing the oxidation of the side wall for the gate electrode and decreasing scattering of the thickness of the film formed to the sidewall in an asymmetric diffusion region structure in which the impurity concentration of an n-type semiconductor region and a p-type semiconductor region on the side of the data line is made relatively higher than the impurity concentration in the n-type semiconductor region and p-type semiconductor region on the side of the capacitor, respectively.
摘要翻译：这里公开了具有在存储单元中具有MISFET阈值电压的较小散射并具有良好的电容保持性的DRAM的半导体器件，以及半导体器件的制造方法。在光氧化之前，在栅电极的侧壁上形成抗氧化膜，从而抑制栅电极的侧壁的氧化，并且在不对称扩散区域结构中减少形成在侧壁上的膜的厚度的散射使数据线一侧的n型半导体区域和p型半导体区域的杂质浓度比n型半导体区域和p型半导体区域的杂质浓度相对高于电容器。

3. 发明申请

US20050098813A1 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20050098813A1
公开(公告)日：2005-05-12
申请号：US10931119
申请日：2004-09-01
申请人： Tomoko Sekiguchi , Shinichiro Kimura , Renichi Yamada , Kikuo Watanabe , Hiroshi Miki , Kenichi Takeda
发明人： Tomoko Sekiguchi , Shinichiro Kimura , Renichi Yamada , Kikuo Watanabe , Hiroshi Miki , Kenichi Takeda
IPC分类号： H01L27/092 , H01L21/336 , H01L21/8238 , H01L21/8242 , H01L27/108 , H01L29/10 , H01L29/78
CPC分类号： H01L29/66659 , H01L27/10855 , H01L27/10873 , H01L27/10894 , H01L29/1079 , H01L29/6656 , H01L29/7835
摘要： Disclosed is herein a semiconductor device having a DRAM with less scattering of threshold voltage of MISFET in a memory cell and having good charge retainability of a capacitor, and a manufacturing method of the semiconductor device. An anti-oxidation film is formed to the side wall of a gate electrode before light oxidation thereby suppressing the oxidation of the side wall for the gate electrode and decreasing scattering of the thickness of the film formed to the sidewall in an asymmetric diffusion region structure in which the impurity concentration of an n-type semiconductor region and a p-type semiconductor region on the side of the data line is made relatively higher than the impurity concentration in the n-type semiconductor region and p-type semiconductor region on the side of the capacitor, respectively.
摘要翻译：这里公开了具有在存储单元中具有MISFET阈值电压的较小散射并具有良好的电容保持性的DRAM的半导体器件，以及半导体器件的制造方法。在光氧化之前，在栅电极的侧壁上形成抗氧化膜，从而抑制栅电极的侧壁的氧化，并且在不对称扩散区域结构中减少形成在侧壁上的膜的厚度的散射使数据线一侧的n型半导体区域和p型半导体区域的杂质浓度比n型半导体区域和p型半导体区域的杂质浓度相对高于电容器。

4. 发明授权

US07364965B2 Semiconductor device and method of fabrication 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US07364965B2
公开(公告)日：2008-04-29
申请号：US10986497
申请日：2004-11-12
申请人： Osamu Tonomura , Hiroshi Miki , Yuichi Matsui , Tomoko Sekiguchi , Kikuo Watanabe
发明人： Osamu Tonomura , Hiroshi Miki , Yuichi Matsui , Tomoko Sekiguchi , Kikuo Watanabe
IPC分类号： H01L21/8242
CPC分类号： H01L21/02178 , H01L21/02181 , H01L21/02197 , H01L21/0228 , H01L21/02282 , H01L21/02337 , H01L21/02356 , H01L21/3141 , H01L21/3162 , H01L21/31645 , H01L27/1085 , H01L27/10855 , H01L28/65
摘要： A semiconductor device having a DRAM has a capacitor in which a dielectric film and an upper electrode are laminated on a lower electrode comprising a polysilicone, in which a natural oxide film oxidized by oxygen in the atmosphere grows to at least 1.5 nm on the surface of a lower electrode of the capacitor. Further, in forming the dielectric film, the dioxide film further grows in the case of using an oxidative raw material. This brings forth a reduction in capacitance, and an increase of a leakage current is caused.Therefore, after a dielectric film having a reduction property has been formed, the reduction property is promoted by a heat treatment to thereby reduce a dioxide film and realize making the dioxide film on the lower electrode surface thinner.
摘要翻译：具有DRAM的半导体器件具有电容器，其中电介质膜和上电极层压在包含聚硅氧烷的下电极上，其中在大气中的氧气氧化的天然氧化物膜在其表面上生长至少至少1.5nm 电容器的下电极。此外，在形成电介质膜时，在使用氧化性原料的情况下，二氧化硅膜进一步生长。这导致电容的减小，并且引起漏电流的增加。因此，在形成具有还原性的电介质膜之后，通过热处理促进还原性能，从而减少二氧化膜，实现使下电极表面上的二氧化物膜更薄。

5. 发明申请

US20050142742A1 Semiconductor device and method of fabrication 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20050142742A1
公开(公告)日：2005-06-30
申请号：US10986497
申请日：2004-11-12
申请人： Osamu Tonomura , Hiroshi Miki , Yuichi Matsui , Tomoko Sekiguchi , Kikuo Watanabe
发明人： Osamu Tonomura , Hiroshi Miki , Yuichi Matsui , Tomoko Sekiguchi , Kikuo Watanabe
IPC分类号： H01L27/108 , H01L21/02 , H01L21/336 , H01L21/8242 , H01L21/8246 , H01L27/105
CPC分类号： H01L21/02178 , H01L21/02181 , H01L21/02197 , H01L21/0228 , H01L21/02282 , H01L21/02337 , H01L21/02356 , H01L21/3141 , H01L21/3162 , H01L21/31645 , H01L27/1085 , H01L27/10855 , H01L28/65
摘要： A semiconductor device having a DRAM has a capacitor in which a dielectric film and an upper electrode are laminated on a lower electrode comprising a polysilicone, in which a natural oxide film oxidized by oxygen in the atmosphere grows to at least 1.5 nm on the surface of a lower electrode of the capacitor. Further, in forming the dielectric film, the dioxide film further grows in the case of using an oxidative raw material. This brings forth a reduction in capacitance, and an increase of a leakage current is caused. Therefore, after a dielectric film having a reduction property has been formed, the reduction property is promoted by a heat treatment to thereby reduce a dioxide film and realize making the dioxide film on the lower electrode surface thinner.
摘要翻译：具有DRAM的半导体器件具有电容器，其中电介质膜和上电极层压在包含聚硅氧烷的下电极上，其中在大气中的氧气氧化的天然氧化物膜在其表面上生长至少至少1.5nm 电容器的下电极。此外，在形成电介质膜时，在使用氧化性原料的情况下，二氧化硅膜进一步生长。这导致电容的减小，并且引起漏电流的增加。因此，在形成具有还原性的电介质膜之后，通过热处理促进还原性能，从而减少二氧化膜，实现使下电极表面上的二氧化物膜更薄。

6. 发明申请

US20120097533A1 DOUBLE-LAYER SHUTTER SPUTTERING APPARATUS 有权
标题翻译：双层快门飞溅设备
公开(公告)号：US20120097533A1
公开(公告)日：2012-04-26
申请号：US13316927
申请日：2011-12-12
申请人： Shuji NOMURA , Ayumu Miyoshi , Hiroshi Miki
发明人： Shuji NOMURA , Ayumu Miyoshi , Hiroshi Miki
IPC分类号： C23C14/34
CPC分类号： C23C14/3464
摘要： A sputtering apparatus including a target holder configured to hold at least two targets; a substrate holder configured to hold a substrate; a first shutter plate arranged between the target holder and the substrate holder, the first shutter plate having at least two holes and being capable of rotating around an axis; a second shutter plate arranged between the first shutter plate and the substrate holder, the second shutter plate having at least two holes and being capable of rotating around the axis; wherein the first and second shutter plates are rotated such that paths are simultaneously created between the at least two targets and the substrate through the at least two holes of the rotated first shutter plate and the at least two holes of the rotated second shutter plate, and a film is formed on the substrate by co-sputtering of the at least two targets.
摘要翻译：一种溅射装置，包括被配置为保持至少两个靶的目标支架; 衬底保持器，其构造成保持衬底; 布置在所述目标保持器和所述基板保持器之间的第一挡板，所述第一挡板具有至少两个孔并且能够绕轴线旋转; 布置在所述第一活门板和所述衬底支架之间的第二活门板，所述第二活门板具有至少两个孔并能绕所述轴线旋转; 其中所述第一和第二快门板旋转，使得通过旋转的第一快门板的至少两个孔和旋转的第二快门板的至少两个孔同时在至少两个目标和基板之间产生通路，以及通过共溅射至少两个靶，在衬底上形成膜。

7. 发明申请

US20070228427A1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US20070228427A1
公开(公告)日：2007-10-04
申请号：US11723683
申请日：2007-03-21
申请人： Yuichi Matsui , Hiroshi Miki
发明人： Yuichi Matsui , Hiroshi Miki
IPC分类号： H01L29/76
CPC分类号： H01L27/10852 , H01L21/02175 , H01L21/022 , H01L21/02271 , H01L21/31641 , H01L21/31645 , H01L27/10814 , H01L27/10894 , H01L28/91
摘要： HfO2 films and ZrO2 films are currently being developed for use as capacitor dielectric films in 85 nm technology node DRAM. However, these films will be difficult to use in 65 nm technology node or later DRAM, since they have a relative dielectric constant of only 20-25. The dielectric constant of such films may be increased by stabilizing their cubic phase. However, this results in an increase in the leakage current along the crystal grain boundaries, which makes it difficult to use these films as capacitor dielectric films. To overcome this problem, the present invention dopes a base material of HfO2 or ZrO2 with an oxide of an element having a large ion radius, such as Y or La, to increase the oxygen coordination number of the base material and thereby increase its relative dielectric constant to 30 or higher even when the base material is in its amorphous state. Thus, the present invention provides dielectric films that can be used to form DRAM capacitors that meet the 65 nm technology node or later.
摘要翻译：目前正在开发用于85nm技术节点DRAM中的电容器电介质膜的HfO 2膜和ZrO 2膜。然而，这些膜将难以在65nm技术节点或之后的DRAM中使用，因为它们的相对介电常数只有20-25。这些膜的介电常数可以通过稳定它们的立方相来增加。然而，这导致沿着晶粒边界的漏电流的增加，这使得难以将这些膜用作电容器电介质膜。为了克服这个问题，本发明将HfO 2 2或ZrO 2 2的基材与具有大离子半径的元素的氧化物如Y或La掺杂，以增加基材的氧配位数，从而即使当基材处于非晶状态时，其相对介电常数也提高到30以上。因此，本发明提供可用于形成满足65nm技术节点或更高版本的DRAM电容器的电介质膜。

8. 发明授权

US07034355B2 Nonvolatile semiconductor storage and its manufacturing method 有权
标题翻译：非易失性半导体存储及其制造方法
公开(公告)号：US07034355B2
公开(公告)日：2006-04-25
申请号：US10496000
申请日：2002-12-02
申请人： Hiroshi Miki
发明人： Hiroshi Miki
IPC分类号： H01L29/76
CPC分类号： H01L21/28211 , H01L27/105 , H01L27/115 , H01L27/11526 , H01L27/11546 , H01L29/511
摘要： To achieve a higher operating speed, higher reliability, and lower power consumption by reducing the thickness of an inter-poly silicon insulator film between a floating gate and a control gate of a flash memory, a silicon dioxide film, a silicon nitride film, tantalum pentoxide, and a silicon dioxide film are formed in a multilayer structure to serve as the inter-poly insulator film between a floating gate and a control gate. With this configuration, tantalum pentoxide formed on the silicon nitride film has a dielectric constant of 50 or more, which is higher than that of the silicon dioxide film, and the thickness of the inter-poly silicon insulator film can be reduced.
摘要翻译：为了通过减小浮动栅极和闪速存储器的控制栅极之间的多晶硅绝缘膜的厚度来实现更高的操作速度，更高的可靠性和更低的功率消耗，二氧化硅膜，氮化硅膜，钽五氧化物和二氧化硅膜形成为多层结构，以用作浮置栅极和控制栅极之间的多晶硅绝缘膜。利用这种构造，形成在氮化硅膜上的五氧化二钽的介电常数为50以上，高于二氧化硅膜的介电常数，能够降低多晶硅绝缘膜的厚度。

9. 发明授权

US06822276B1 Memory structure with a ferroelectric capacitor 失效
标题翻译：具有铁电电容的存储器结构
公开(公告)号：US06822276B1
公开(公告)日：2004-11-23
申请号：US09391250
申请日：1999-09-07
申请人： Kazuyoshi Torii , Hiroshi Miki , Yoshihisa Fujisaki
发明人： Kazuyoshi Torii , Hiroshi Miki , Yoshihisa Fujisaki
IPC分类号： H01L27108
CPC分类号： H01L28/56 , H01L21/28568 , H01L27/10852 , H01L27/10855 , H01L28/55 , H01L28/75
摘要： It is an object of the present invention to provide a fine memory cell structure preventing a reaction between an interlayer insulating film and a ferroelectric film and suitable for high integration. According to the invention, there is provided a structure in which a reaction barrier film 43 is interposed between a ferroelectric film 71 and an interlayer insulating film 32 and side walls of a diffusion barrier film 51 are not brought into direct contact with the ferroelectric film 71. Thereby, the reaction between the interlayer insulating film 32 and the ferroelectric film 71 can be restrained and exfoliation of the ferroelectric film 71 can be prevented.
摘要翻译：本发明的目的是提供一种防止层间绝缘膜和铁电体膜之间的反应并且适合于高集成度的精细存储单元结构。根据本发明，提供一种结构，其中反应阻挡膜43介于铁电膜71和层间绝缘膜32之间，并且扩散阻挡膜51的侧壁不与铁电体膜71直接接触由此，能够抑制层间绝缘膜32与强电介质膜71的反应，能够防止铁电体膜71的剥离。

10. 发明授权

US06800889B2 Semiconductor device and fabrication method thereof 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US06800889B2
公开(公告)日：2004-10-05
申请号：US10073240
申请日：2002-02-13
申请人： Shinichiro Takatani , Hiroshi Miki , Keiko Kushida , Yoshihisa Fujisaki , Kazuyoshi Torii
发明人： Shinichiro Takatani , Hiroshi Miki , Keiko Kushida , Yoshihisa Fujisaki , Kazuyoshi Torii
IPC分类号： H01L2976
CPC分类号： H01L28/55 , H01L28/60
摘要： A semiconductor device includes a capacitor having a lower electrode (102), a high-dielectric-constant or ferroelectric thin film (103), and an upper electrode (104) which are subsequently stacked. An impurity having an action of suppressing the catalytic activity of a metal or a conductive oxide constituting the electrode is added to the upper electrode (104). The addition of the impurity is effective to prevent inconveniences such as a reduction in capacitance, an insulation failure, and the peeling of the electrode due to hydrogen heat-treatment performed after formation of the upper electrode (104), and to improve the long-term reliability.
摘要翻译：半导体器件包括随后堆叠的具有下电极（102），高介电常数或铁电薄膜（103）和上电极（104）的电容器。具有抑制构成电极的金属或导电氧化物的催化活性的作用的杂质被添加到上电极（104）。杂质的添加对于防止在形成上电极（104）之后进行的氢热处理等电容的减少，绝缘失效以及电极的剥离等不良情况是有效的，长期可靠性。

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