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1. 发明申请

US20090230430A1 Field effect transistor 失效
标题翻译：场效应晶体管
公开(公告)号：US20090230430A1
公开(公告)日：2009-09-17
申请号：US11921857
申请日：2006-06-12
申请人： Hironobu Miyamoto , Yuji Ando , Yasuhiro Okamoto , Tatsuo Nakayama , Takashi Inoue , Kazuki Ota , Aklo Wakejima , Kensuke Kasahara , Yasuhiro Murase , Kohji Matsunaga , Katsumi Yamanoguchi , Hidenori Shimawaki
发明人： Hironobu Miyamoto , Yuji Ando , Yasuhiro Okamoto , Tatsuo Nakayama , Takashi Inoue , Kazuki Ota , Aklo Wakejima , Kensuke Kasahara , Yasuhiro Murase , Kohji Matsunaga , Katsumi Yamanoguchi , Hidenori Shimawaki
IPC分类号： H01L29/78
CPC分类号： H01L29/404 , H01L29/7783 , H01L29/7787 , H01L29/802 , H01L29/812
摘要： A field effect transistor includes a layer structure made of compound semiconductor (111) provided on a semiconductor substrate (110) made of GaAs or InP, as an operation layer, and employs a first field plate electrode (116) and a second field plate electrode (118). The second field plate electrode includes a shielding part (119) located in the region between the first field plate electrode and a drain electrode (114), and serves to shield the first field plate electrode from the drain electrode. When, in the cross sectional view in the gate length direction, the length in the gate length direction of an overlap region, in which the second field plate electrode overlaps the upper part of a structure composed of the first field plate electrode and a gate electrode (113), is designated as Lol, and the gate length is Lg, the relation expressed as 0≦Lol/Lg≦1 holds.
摘要翻译：场效应晶体管包括由设置在由GaAs或InP制成的半导体衬底（110）上的化合物半导体（111）作为操作层的层结构，并且采用第一场极板电极（116）和第二场极板电极（118）。第二场板电极包括位于第一场极板电极和漏电极（114）之间的区域中的屏蔽部分（119），用于屏蔽第一场极板电极与漏极电极。当在栅极长度方向的截面图中，重叠区域的栅极长度方向上的长度，其中第二场极板电极与由第一场极板电极和栅电极构成的结构的上部重叠（113）表示为Lol，栅极长度为Lg，表示为0 <= Lol / Lg <= 1的关系成立。

2. 发明授权

US07863648B2 Field effect transistor 有权
标题翻译：场效应晶体管
公开(公告)号：US07863648B2
公开(公告)日：2011-01-04
申请号：US11921854
申请日：2006-06-12
申请人： Hironobu Miyamoto , Yuji Ando , Yasuhiro Okamoto , Tatsuo Nakayama , Takashi Inoue , Kazuki Ota , Akio Wakejima , Kensuke Kasahara , Yasuhiro Murase , Kohji Matsunaga , Katsumi Yamanoguchi , Hidenori Shimawaki
发明人： Hironobu Miyamoto , Yuji Ando , Yasuhiro Okamoto , Tatsuo Nakayama , Takashi Inoue , Kazuki Ota , Akio Wakejima , Kensuke Kasahara , Yasuhiro Murase , Kohji Matsunaga , Katsumi Yamanoguchi , Hidenori Shimawaki
IPC分类号： H01L29/812 , H01L21/338
CPC分类号： H01L29/7787 , H01L29/2003 , H01L29/402 , H01L29/404 , H01L29/802 , H01L29/812
摘要： A field effect transistor (100) exhibiting good performance at high voltage operation and high frequency includes a first field plate electrode (116) and a second field plate electrode (118). The second field plate electrode includes a shielding part (119) located in the region between the first field plate electrode and a drain electrode (114), and serves to shield the first field plate electrode from the drain electrode. When in the cross sectional view in the gate length direction, the length in the gate length direction of an overlap region where the second field plate electrode (118) overlap the upper part of a structure including the first field plate electrode and a gate electrode (113) is designated as Lol, and the gate length is Lg, the relation expressed as 0 ≦Lol/Lg≦1 holds.
摘要翻译：在高电压运行和高频下表现出良好性能的场效应晶体管（100）包括第一场极板电极（116）和第二场板电极（118）。第二场板电极包括位于第一场极板电极和漏电极（114）之间的区域中的屏蔽部分（119），用于屏蔽第一场极板电极与漏极电极。当在栅极长度方向的横截面视图中，第二场板电极（118）与包括第一场极板电极和栅电极的结构的上部重叠的重叠区域的栅极长度方向上的长度（ 113表示为Lol，栅极长度为Lg，表示为0＆nlE; Lol / Lg＆nlE; 1的关系成立。

3. 发明授权

US07800131B2 Field effect transistor 失效
标题翻译：场效应晶体管
公开(公告)号：US07800131B2
公开(公告)日：2010-09-21
申请号：US11921857
申请日：2006-06-12
申请人： Hironobu Miyamoto , Yuji Ando , Yasuhiro Okamoto , Tatsuo Nakayama , Takashi Inoue , Kazuki Ota , Akio Wakejima , Kensuke Kasahara , Yasuhiro Murase , Kohji Matsunaga , Katsumi Yamanoguchi , Hidenori Shimawaki
发明人： Hironobu Miyamoto , Yuji Ando , Yasuhiro Okamoto , Tatsuo Nakayama , Takashi Inoue , Kazuki Ota , Akio Wakejima , Kensuke Kasahara , Yasuhiro Murase , Kohji Matsunaga , Katsumi Yamanoguchi , Hidenori Shimawaki
IPC分类号： H01L29/812 , H01L21/338
CPC分类号： H01L29/404 , H01L29/7783 , H01L29/7787 , H01L29/802 , H01L29/812
摘要： A field effect transistor includes a layer structure made of compound semiconductor (111) provided on a semiconductor substrate (110) made of GaAs or InP, as an operation layer, and employs a first field plate electrode (116) and a second field plate electrode (118). The second field plate electrode includes a shielding part (119) located in the region between the first field plate electrode and a drain electrode (114), and serves to shield the first field plate electrode from the drain electrode. When, in the cross sectional view in the gate length direction, the length in the gate length direction of an overlap region, in which the second field plate electrode overlaps the upper part of a structure composed of the first field plate electrode and a gate electrode (113), is designated as Lol, and the gate length is Lg, the relation expressed as 0≦Lol/Lg≦1 holds.
摘要翻译：场效应晶体管包括由设置在由GaAs或InP制成的半导体衬底（110）上的化合物半导体（111）作为操作层的层结构，并且采用第一场极板电极（116）和第二场极板电极（118）。第二场板电极包括位于第一场极板电极和漏电极（114）之间的区域中的屏蔽部分（119），用于屏蔽第一场极板电极与漏极电极。当在栅极长度方向的截面图中，重叠区域的栅极长度方向上的长度，其中第二场极板电极与由第一场极板电极和栅电极构成的结构的上部重叠（113）表示为Lol，栅极长度为Lg，表示为0＆nlE; Lol / Lg＆nlE; 1的关系成立。

4. 发明申请

US20090230429A1 Field effect transistor 有权
标题翻译：场效应晶体管
公开(公告)号：US20090230429A1
公开(公告)日：2009-09-17
申请号：US11921854
申请日：2006-06-12
申请人： Hironobu Miyamoto , Yuji Ando , Yasuhiro Okamoto , Tasuo Nakayama , Takashi Inoue , Kazuki Ota , Akio Wakejima , Kensuke Kasahara , Yasuhiro Murase , Kohji Matsunaga , Katsumi Yamanoguchi , Hidenori Shimawaki
发明人： Hironobu Miyamoto , Yuji Ando , Yasuhiro Okamoto , Tasuo Nakayama , Takashi Inoue , Kazuki Ota , Akio Wakejima , Kensuke Kasahara , Yasuhiro Murase , Kohji Matsunaga , Katsumi Yamanoguchi , Hidenori Shimawaki
IPC分类号： H01L29/80
CPC分类号： H01L29/7787 , H01L29/2003 , H01L29/402 , H01L29/404 , H01L29/802 , H01L29/812
摘要： A field effect transistor (100) exhibiting good performance at high voltage operation and high frequency includes a first field plate electrode (116) and a second field plate electrode (118). The second field plate electrode includes a shielding part (119) located in the region between the first field plate electrode and a drain electrode (114), and serves to shield the first field plate electrode from the drain electrode. When in the cross sectional view in the gate length direction, the length in the gate length direction of an overlap region where the second field plate electrode (118) overlap the upper part of a structure including the first field plate electrode and a gate electrode (113) is designated as Lol, and the gate length is Lg, the relation expressed as 0≦Lol/Lg≦1 holds.
摘要翻译：在高电压运行和高频下表现出良好性能的场效应晶体管（100）包括第一场极板电极（116）和第二场板电极（118）。第二场板电极包括位于第一场极板电极和漏电极（114）之间的区域中的屏蔽部分（119），用于屏蔽第一场极板电极与漏极电极。当在栅极长度方向的横截面视图中，第二场板电极（118）与包括第一场极板电极和栅电极的结构的上部重叠的重叠区域的栅极长度方向上的长度（ 113）被指定为Lol，栅极长度为Lg，表示为0 <= Lol / Lg <= 1的关系成立。

5. 发明授权

US06441391B1 Semiconductor device having drain and gate electrodes formed to lie along few degrees of direction in relation to the substrate 有权
标题翻译：具有漏极和栅电极的半导体器件形成为相对于衬底沿着几个方向的位置
公开(公告)号：US06441391B1
公开(公告)日：2002-08-27
申请号：US09940374
申请日：2001-08-29
申请人： Yasuo Ohno , Nobuyuki Hayama , Kensuke Kasahara , Tatsuo Nakayama , Hironobu Miyamoto , Yuji Takahashi , Yuji Ando , Kohji Matsunaga , Masaaki Kuzuhara
发明人： Yasuo Ohno , Nobuyuki Hayama , Kensuke Kasahara , Tatsuo Nakayama , Hironobu Miyamoto , Yuji Takahashi , Yuji Ando , Kohji Matsunaga , Masaaki Kuzuhara
IPC分类号： H01L2906
CPC分类号： H01L29/812 , H01L29/045 , H01L29/2003
摘要： An object of the present invention is to improve, in a group III nitride semiconductor device, the productivity, heat radiation characteristic and performance in the element high speed operation; upon a sapphire substrate in which an A plane (an (11-20) plane) is set to be the basal plane, an epitaxial growth layer of a group III nitride semiconductor is formed and, thereon, a gate electrode 16, a source electrode 15 and a drain electrode 17 are formed; these electrodes are disposed in such a way that a direction along which they are laid makes an angle within 20° with respect to a C axis of sapphire.
摘要翻译：本发明的目的是在III族氮化物半导体器件中提高元件高速运转中的生产率，散热特性和性能; 在其中A平面（（11-20）面）设置为基面的蓝宝石衬底上，形成III族氮化物半导体的外延生长层，并且在其上形成栅电极16，源电极 15和漏电极17; 这些电极被设置成使得它们被放置的方向相对于蓝宝石的C轴成20°以内的角度。

6. 发明授权

US06765241B2 Group III nitride semiconductor device of field effect transistor type having reduced parasitic capacitances 失效
标题翻译：具有降低的寄生电容的场效应晶体管类型的III族氮化物半导体器件
公开(公告)号：US06765241B2
公开(公告)日：2004-07-20
申请号：US10362883
申请日：2003-02-27
申请人： Yasuo Ohno , Nobuyuki Hayama , Kensuke Kasahara , Tatsuo Nakayama , Hironobu Miyamoto , Yuji Takahashi , Yuji Ando , Kohji Matsunaga , Masaaki Kuzuhara
发明人： Yasuo Ohno , Nobuyuki Hayama , Kensuke Kasahara , Tatsuo Nakayama , Hironobu Miyamoto , Yuji Takahashi , Yuji Ando , Kohji Matsunaga , Masaaki Kuzuhara
IPC分类号： H01L29812
CPC分类号： H01L29/8126 , H01L21/0242 , H01L21/02458 , H01L21/0254 , H01L29/045 , H01L29/2003
摘要： A group III nitride semiconductor device of field effect transistor type having improved productivity, reduced parasitic capacitances adapted for excellent device performance in high-speed operation as well as good heat diffusion characteristics. The device includes an epitaxial growth layer of a group III nitride semiconductor with a buffer layer laid under it, formed on an A plane (an (11-20) plane) of a sapphire. Thereon a gate electrode, a source electrode, a drain electrode, and pad electrodes are formed, and a ground conductor layer is formed on the back face of the sapphire substrate. A thickness of said sapphire substrate tsub satisfies the following Equation (1). t sub ≦ 10 ⁢ ϵ sub ⁢ S pad ϵ epi ⁢ S gate ⁢ t act where Spad is an area of the pad electrode; Sgate is an area of the gate electrode; &egr;sub is a relative permittivity of the sapphire substrate in the direction of the thickness; &egr;epi is a relative permittivity of the group III nitride semiconductor layer in the direction of the thickness; tsub is a thickness of the sapphire substrate; and tact is an effective thickness of the group III nitride semiconductor layer.
摘要翻译：具有提高生产率的场效应晶体管类型的III族氮化物半导体器件，适于在高速操作中优异的器件性能以及良好的热扩散特性的减小的寄生电容。该器件包括形成在蓝宝石的A平面（（11-20）面）上的具有缓冲层的III族氮化物半导体的外延生长层。在其上形成栅电极，源电极，漏电极和焊盘电极，并且在蓝宝石衬底的背面上形成接地导体层。所述蓝宝石衬底tsub的厚度满足以下等式（1）。其中，Spad是焊盘电极的面积; Sgate是栅电极的面积; epsilonsub是蓝宝石衬底在厚度方向上的相对介电常数;εilon 是III族氮化物半导体层在厚度方向上的相对介电常数; tsub是蓝宝石衬底的厚度; andtact是III族氮化物半导体层的有效厚度。

7. 发明授权

US07071526B2 Semiconductor device having Schottky junction electrode 失效
标题翻译：具有肖特基结电极的半导体器件
公开(公告)号：US07071526B2
公开(公告)日：2006-07-04
申请号：US10518602
申请日：2003-06-17
申请人： Yuji Ando , Hironobu Miyamoto , Yasuhiro Okamoto , Kensuke Kasahara , Tatsuo Nakayama , Masaaki Kuzuhara
发明人： Yuji Ando , Hironobu Miyamoto , Yasuhiro Okamoto , Kensuke Kasahara , Tatsuo Nakayama , Masaaki Kuzuhara
IPC分类号： H01L27/095 , H01L29/47
CPC分类号： H01L29/7787 , H01L29/2003 , H01L29/475 , H01L29/7781 , H01L29/812
摘要： A GaN semiconductor device with improved heat resistance of the Schottky junction electrode and excellent power performance and reliability is provided. In this semiconductor device having a Schottky gate electrode 17 which is in contact with an AlGaN electron supplying layer 14, a gate electrode 17 comprises a laminated structure wherein a first metal layer 171 formed of any of Ni, Pt and Pd, a second metal layer 172 formed of any of Mo, Pt, W, Ti, Ta, MoSi, PtSi, WSi, TiSi, TaSi, MoN, WN, TiN and TaN, and a third metal layer formed of any of Au, Cu, Al and Pt. Since the second metal layer comprises a metal material having a high melting point, it works as a barrier to the interdiffusion between the first metal layer and the third metal layer, and the deterioration of the gate characteristics caused by high temperature operation is suppressed. Since the first metal layer contacting the AlGaN electron supplying layer 14 has a high work function, the Schottky barrier is high, and superior Schottky contact is obtained.
摘要翻译：提供了具有肖特基接合电极的耐热性改善并且具有优异的功率性能和可靠性的GaN半导体器件。在具有与AlGaN电子供给层14接触的肖特基栅电极17的该半导体器件中，栅电极17包括层叠结构，其中由Ni，Pt和Pd中的任一种形成的第一金属层171，第二金属层由Mo，Pt，W，Ti，Ta，MoSi，PtSi，WSi，TiSi，TaSi，MoN，WN，TiN和TaN中的任一种形成的第一金属层，以及由Au，Cu，Al和Pt中的任一种形成的第三金属层。由于第二金属层包括具有高熔点的金属材料，所以它作为第一金属层和第三金属层之间的相互扩散的障碍，并且抑制了由高温操作引起的栅极特性的劣化。由于与AlGaN电子供给层14接触的第一金属层具有高功函数，所以肖特基势垒高，得到优异的肖特基接触。

8. 发明申请

US20060054929A1 Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：US20060054929A1
公开(公告)日：2006-03-16
申请号：US10515886
申请日：2004-11-29
申请人： Tatsuo Nakayama , Yuji Ando , Hironobu Miyamoto , Kensuke Kasahara , Yasuhiro Okamoto , Masaaki Kuzuhara
发明人： Tatsuo Nakayama , Yuji Ando , Hironobu Miyamoto , Kensuke Kasahara , Yasuhiro Okamoto , Masaaki Kuzuhara
IPC分类号： H01L31/109
CPC分类号： H01L29/7783 , H01L29/2003
摘要： A semiconductor device includes, on a substrate (101), a buffer layer (102), and an channel layer (104), consisting essentially of semiconductor of a wultzite compound of group III-V, having a (0001) plane as a principal plane. The channel layer is subjected to compressive strain. A carrier supplying layer (103) is interposed between the channel layer (104) and the buffer layer (102). The carrier supplying layer (103) consists essentially of semiconductor of a wultzite compound of group III-V as a main component. N-type impurities are doped into the entire or part of the carrier supplying layer (103).
摘要翻译：半导体器件在衬底（101）上包括缓冲层（102）和沟道层（104），该沟道层（104）主要由具有（0001）面作为主体的III-V族的无丝绒化合物的半导体组成飞机通道层经受压应变。载体供给层（103）插入在沟道层（104）和缓冲层（102）之间。载体供给层（103）主要由作为主要成分的III-V族的无水锰矿化合物的半导体构成。 N型杂质被掺杂到载体供给层（103）的整个或部分中。

9. 发明申请

US20050151255A1 Semiconductor device having schottky junction electrode 失效
标题翻译：具有肖特基结电极的半导体器件
公开(公告)号：US20050151255A1
公开(公告)日：2005-07-14
申请号：US10518602
申请日：2003-06-17
申请人： Yuji Ando , Hironobu Miyamoto , Yasuhiro Okamoto , Kensuke Kasahara , Tatsuo Nakayama , Masaaki Kuzuhara
发明人： Yuji Ando , Hironobu Miyamoto , Yasuhiro Okamoto , Kensuke Kasahara , Tatsuo Nakayama , Masaaki Kuzuhara
IPC分类号： H01L29/872 , H01L21/338 , H01L29/20 , H01L29/423 , H01L29/47 , H01L29/778 , H01L29/812 , H01L31/0328
CPC分类号： H01L29/7787 , H01L29/2003 , H01L29/475 , H01L29/7781 , H01L29/812
摘要： A GaN semiconductor device with improved heat resistance of the Schottky junction electrode and excellent power performance and reliability is provided. In this semiconductor device having a Schottky gate electrode 17 which is in contact with an AlGaN electron supplying layer 14, a gate electrode 17 comprises a laminated structure wherein a first metal layer 171 formed of any of Ni, Pt and Pd, a second metal layer 172 formed of any of Mo, Pt, W, Ti, Ta, MoSi, PtSi, WSi, TiSi, TaSi, MoN, WN, TiN and TaN, and a third metal layer formed of any of Au, Cu, Al and Pt. Since the second metal layer comprises a metal material having a high melting point, it works as a barrier to the interdiffusion between the first metal layer and the third metal layer, and the deterioration of the gate characteristics caused by high temperature operation is suppressed. Since the first metal layer contacting the AlGaN electron supplying layer 14 has a high work function, the Schottky barrier is high, and superior Schottky contact is obtained.
摘要翻译：提供了具有肖特基接合电极的耐热性改善并且具有优异的功率性能和可靠性的GaN半导体器件。在具有与AlGaN电子供给层14接触的肖特基栅电极17的该半导体器件中，栅电极17包括层叠结构，其中由Ni，Pt和Pd中的任一种形成的第一金属层171，第二金属层由Mo，Pt，W，Ti，Ta，MoSi，PtSi，WSi，TiSi，TaSi，MoN，WN，TiN和TaN中的任一种形成的第一金属层，以及由Au，Cu，Al和Pt中的任一种形成的第三金属层。由于第二金属层包括具有高熔点的金属材料，所以它作为第一金属层和第三金属层之间的相互扩散的障碍，并且抑制了由高温操作引起的栅极特性的劣化。由于与AlGaN电子供给层14接触的第一金属层具有高功函数，所以肖特基势垒高，得到优异的肖特基接触。

10. 发明授权

US06492669B2 Semiconductor device with schottky electrode having high schottky barrier 有权
标题翻译：肖特基电极具有高肖特基势垒的半导体器件
公开(公告)号：US06492669B2
公开(公告)日：2002-12-10
申请号：US09892567
申请日：2001-06-28
申请人： Tatsuo Nakayama , Yuji Ando , Hironobu Miyamoto , Kazuaki Kunihiro , Yuji Takahashi , Kensuke Kasahara , Nobuyuki Hayama , Yasuo Ohno , Kouji Matsunaga , Masaaki Kuzuhara
发明人： Tatsuo Nakayama , Yuji Ando , Hironobu Miyamoto , Kazuaki Kunihiro , Yuji Takahashi , Kensuke Kasahara , Nobuyuki Hayama , Yasuo Ohno , Kouji Matsunaga , Masaaki Kuzuhara
IPC分类号： H01L2980
CPC分类号： H01L29/66462 , H01L21/28587 , H01L29/2003 , H01L29/475 , H01L29/7783
摘要： A carrier travel layer is formed on the substrate of a semiconductor device with a buffer layer interposed, and a spacer layer and carrier supply layer are then formed on this carrier travel layer. On the carrier supply layer are provided a source electrode and a drain electrode, and a gate electrode is provided on an interposed Schottky layer. The carrier supply layer is composed of AlGaN and has tensile strain. The Schottky layer is composed of InGaN and has compressive strain. A negative piezoelectric charge is induced on the carrier supply layer side of the Schottky layer, and a positive piezoelectric charge is induced on the opposite side of the Schottky layer, whereby a sufficient Schottky barrier height is obtained and leakage current is suppressed.
摘要翻译：在具有缓冲层的半导体器件的基板上形成载流子行进层，然后在该载体行进层上形成间隔层和载体供给层。在载体供给层上设置有源电极和漏电极，在插入的肖特基层上设置有栅电极。载体供应层由AlGaN组成并具有拉伸应变。肖特基层由InGaN组成并具有压应变。在肖特基层的载流子供给层侧感应出负的压电电荷，在肖特基层的相反侧产生正的压电电荷，由此获得足够的肖特基势垒高度，并且抑制泄漏电流。

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