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1. 发明授权

US5388230A Parallel processor having multi-processing units either connected or bypassed in either series or parallel by the use of bus switching 失效
标题翻译：具有多处理单元的并行处理器通过使用总线切换以串联或并联方式连接或旁路
公开(公告)号：US5388230A
公开(公告)日：1995-02-07
申请号：US104945
申请日：1993-08-12
申请人： Hiromichi Yamada , Koyo Katsura
发明人： Hiromichi Yamada , Koyo Katsura
IPC分类号： G06F13/40 , G06F15/173 , G06F15/80 , G06T1/20 , G06F13/00
CPC分类号： G06F13/4022 , G06F15/17343
摘要： A parallel process which includes a plurality of processing units connected to each other via input/output ports. Each of the plurality of processing units includes a memory for storing a program and data, a local bus for inputting/outputting the program and data to and from the memory having an address signal line, a data signal line, and a control signal line, a CPU for reading the program from the memory via the local bus, reading data needed to execute the program from the memory via the local bus, and storing data which has been updated due to the execution of the program in the memory via the local bus, and a plurality of input/output ports for connecting the local bus to a plurality of outside buses. The input/output ports are used by the CPU to input/output data to and from an outside memory connected to an outside bus or by an outside CPU, connected to an outside bus, to input/output data to and from the memory. At least one bypass switch is provided for controllably connecting two of the outside buses to permit data transference between the outside CPU and the outside memory thereby bypassing the CPU and the memory. Also provided is a main CPU for setting program and data in the processing units and recovering data from the processing units.
摘要翻译：并行处理，其包括经由输入/输出端口彼此连接的多个处理单元。多个处理单元中的每一个包括用于存储程序和数据的存储器，用于向具有地址信号线，数据信号线和控制信号线的存储器输入/输出程序和数据的本地总线，经由本地总线从存储器读取程序的CPU，经由本地总线读取从存储器执行程序所需的数据，以及经由本地总线将由于执行程序而被更新的数据存储在存储器中的CPU 以及用于将本地总线连接到多个外部总线的多个输入/输出端口。输入/输出端口被CPU用于向连接到外部总线的外部存储器或连接到外部总线的外部CPU输入/输出数据，以从存储器输入/输出数据。提供至少一个旁路开关用于可控地连接两个外部总线以允许外部CPU和外部存储器之间的数据传输，从而绕过CPU和存储器。还提供了用于在处理单元中设置程序和数据并从处理单元恢复数据的主CPU。

2. 发明授权

US08639905B2 Microcontroller and electronic control unit 有权
标题翻译：微控制器和电子控制单元
公开(公告)号：US08639905B2
公开(公告)日：2014-01-28
申请号：US13614313
申请日：2012-09-13
申请人： Hiromichi Yamada , Yuichi Ishiguro , Nobuyasu Kanekawa
发明人： Hiromichi Yamada , Yuichi Ishiguro , Nobuyasu Kanekawa
IPC分类号： G06F12/02
CPC分类号： G06F11/1641 , G06F11/1683
摘要： A microcontroller in which respective CPUs execute different applications so as to improve processing performance, and the respective CPUs execute an application that requires safety and mutually compare the results thereof so as to enhance the reliability of write data is provided. The microcontroller has a plurality of processing systems made up of a first CPU, a second CPU, a first memory and a second memory, and for the instruction processing about specific processing set in advance, the write to peripheral modules which are not multiplexed is executed twice, and the write data of the first time and the second time are mutually collated.
摘要翻译：其中相应CPU执行不同应用以提高处理性能的微控制器，并且相应的CPU执行需要安全性并相互比较其结果的应用，以提供写入数据的可靠性。微控制器具有由第一CPU，第二CPU，第一存储器和第二存储器构成的多个处理系统，并且对于关于预先设定的特定处理的指令处理，执行未复用的对外围模块的写入两次，并且第一次和第二次的写入数据被相互整理。

3. 发明授权

US07260657B2 Serial data transferring apparatus 有权
标题翻译：串行数据传输设备
公开(公告)号：US07260657B2
公开(公告)日：2007-08-21
申请号：US10491285
申请日：2001-10-02
申请人： Masahiro Matsumoto , Fumio Murabayashi , Hiromichi Yamada , Keiji Hanzawa , Hiroyasu Sukesako
发明人： Masahiro Matsumoto , Fumio Murabayashi , Hiromichi Yamada , Keiji Hanzawa , Hiroyasu Sukesako
IPC分类号： G06F3/00 , G06F5/00
CPC分类号： H04L7/10 , H04J3/24 , H04J7/00 , H04L7/046 , H04L7/06
摘要： A master unit sends a start signal to a slave unit. When receiving the start signal from the master unit, the slave unit sends, to the master unit, a synchronization field that is a data train (pulse signal) indicative of a transfer clock with which the slave unit is able to perform transferring and receiving operations. The master unit sends, to the slave unit, command data in accordance with the transfer clock indicated by the synchronization field sent from the slave unit. In response to the command data sent from the master unit, the slave unit sends, to the master unit, response data in accordance with the transfer clock indicated by the synchronization field. Thus, in a communication system employing a serial data transferring apparatus of the present invention, the master unit establishes the synchronization for the data transfer, while the slave unit is free from a burden of establishing the synchronization for the data transfer. A serial data transferring apparatus is realized which can simplify the structure of the slave unit, cut the total cost, and reduce noise.
摘要翻译：主单元向从单元发送启动信号。当从主单元接收到起始信号时，从单元向主单元发送同步字段，该同步字段是指示从单元能够执行传送和接收操作的传送时钟的数据串（脉冲信号）。主单元根据从从单元发送的同步字段指示的传送时钟向从属单元发送命令数据。响应于从主单元发送的命令数据，从单元根据由同步字段指示的传送时钟向主单元发送响应数据。因此，在采用本发明的串行数据传送装置的通信系统中，主单元建立用于数据传送的同步，而从单元没有建立用于数据传送的同步的负担。实现了串行数据传送装置，其可以简化从单元的结构，降低总成本并降低噪声。

4. 发明申请

US20070180317A1 ERROR CORRECTION METHOD 有权
标题翻译：错误校正方法
公开(公告)号：US20070180317A1
公开(公告)日：2007-08-02
申请号：US11623441
申请日：2007-01-16
申请人： Teppei HIROTSU , Hiromichi Yamada , Teruaki Sakata , Kesami Hagiwara
发明人： Teppei HIROTSU , Hiromichi Yamada , Teruaki Sakata , Kesami Hagiwara
IPC分类号： G06F11/00
CPC分类号： G06F11/1407
摘要： This method is an error correction method such that, when an error is detected in a CPU with pipeline struct, a content of a register file is restored by a delayed register file which holds an execute completion state of an [Instruction N] correctly executed before this error, and a rollback control that re-executes an instruction from the [Instruction N+1] which is the next instruction of the [Instruction N] is performed. The method collects a parity check result of arbitrary Flip-Flops existing inside the CPU, and detects an error. As a result, the content of the register file is restored into the instruction execute completion state preceding to the instruction range likely to malfunction by the error, and the instruction can be roll backed from the beginning of the instruction range likely having malfunctioned by the error.
摘要翻译：该方法是一种错误校正方法，使得当在具有流水线结构的CPU中检测到错误时，通过延迟的寄存器文件来恢复寄存器文件的内容，该延迟寄存器文件保持在之前正确执行的[指令N]的执行完成状态该错误和执行作为[指令N]的下一条指令的[指令N + 1]的指令的回滚控制。该方法收集CPU内存在的任意Flip-Flops的奇偶校验结果，并检测出错误。结果，寄存器文件的内容被恢复到可能由错误导致故障的指令范围之前的指令执行完成状态，并且可以从可能由错误发生故障的指令范围的开始滚转指令。

5. 发明申请

US20060096305A1 Fluid flowmeter and engine control system using the same 审中-公开
标题翻译：流体流量计和发动机控制系统使用相同
公开(公告)号：US20060096305A1
公开(公告)日：2006-05-11
申请号：US11206733
申请日：2005-08-19
申请人： Keiji Hanzawa , Masahiro Matsumoto , Hiromichi Yamada , Hiroshi Nakano , Hiroyasu Sukesako
发明人： Keiji Hanzawa , Masahiro Matsumoto , Hiromichi Yamada , Hiroshi Nakano , Hiroyasu Sukesako
IPC分类号： F25B39/04
CPC分类号： G01F1/6845 , G01F1/696 , G01F1/6986 , G01F1/699
摘要： An air temperature sensor sensing an air temperature, supplied with a pulse signal as a driving signal from a pulse signal source, senses an air temperature based on the pulse signal. While the air temperature sensor is self-heated during an electrical current supplying time period by the pulse signal, it is cooled during an electrical current halting time period. Accordingly, the self-heating of the air temperature sensor by the driving signal is suppressed, and a thermal effect on air flow rate sensing elements disposed in an air flow downstream side of the air temperature sensor is also reduced.
摘要翻译：感测从脉冲信号源提供脉冲信号作为驱动信号的空气温度的空气温度传感器基于脉冲信号感测空气温度。当通过脉冲信号在空气温度传感器在电流供应时间段内自加热时，在电流停止时间段期间，其被冷却。因此，通过驱动信号来抑制空气温度传感器的自身加热，并且对于设置在空气温度传感器的空气流下游侧的空气流量感测元件的热效应也降低。

6. 发明授权

US06915413B2 Micro-controller for reading out compressed instruction code and program memory for compressing instruction code and storing therein 失效
公开(公告)号：US06915413B2
公开(公告)日：2005-07-05
申请号：US10101480
申请日：2002-03-20
申请人： Hiromichi Yamada , Dai Fujii , Yasuhiro Nakatsuka , Takashi Hotta , Kotaro Shimamura , Tatsuki Inuduka , Takanaga Yamazaki
发明人： Hiromichi Yamada , Dai Fujii , Yasuhiro Nakatsuka , Takashi Hotta , Kotaro Shimamura , Tatsuki Inuduka , Takanaga Yamazaki
IPC分类号： G06F9/30 , G06F9/318 , G06F9/32 , G06F7/36 , G06F9/45 , G06F17/30
CPC分类号： G06F9/30178 , Y10S707/99942
摘要： A micro-controller includes a dictionary memory for storing instruction codes which appear in a program, and a compressed code memory for storing compressed codes each converted from each of the instruction codes included in the program. Each compressed code has a word length sufficiently long to identify all instruction codes included in the program. Each compressed code has a value indicative of an address in the dictionary memory at which an associated instruction code is stored. The micro-controller is responsive to an instruction code read request which specifies an address of a compressed code to read the compressed code stored in the specified address in the compressed code memory, and to subsequently read an instruction code stored in an address indicated by the compressed code in the dictionary memory.

7. 发明申请

US20050040978A1 A/D converter and a microcontroller including the same 有权
标题翻译： A / D转换器和包含它的微控制器
公开(公告)号：US20050040978A1
公开(公告)日：2005-02-24
申请号：US10912542
申请日：2004-08-06
申请人： Yuichiro Morita , Kohei Sakurai , Nobuyasu Kanekawa , Masatoshi Hoshino , Hiromichi Yamada , Kotaro Shimamura , Satoshi Tanaka , Naoki Yada
发明人： Yuichiro Morita , Kohei Sakurai , Nobuyasu Kanekawa , Masatoshi Hoshino , Hiromichi Yamada , Kotaro Shimamura , Satoshi Tanaka , Naoki Yada
IPC分类号： H03M1/00 , H03M1/12
CPC分类号： H03M1/1225
摘要： In an A/D converter and a microcontroller including the same, the number of selection patterns of analog input channels is increased for each A/D conversion and the A/D conversion is conducted using an A/D converter having only fundamental functions without imposing load onto a CPU. The A/D converter or a DMA transfer device includes an A/D conversion table including one or more entries. Each entry includes enable bits for setting whether or not an A/D conversion is executed for the respective analog input channels and a plurality of count number bits for setting a number of executions of the A/D conversion.
摘要翻译：在A / D转换器和包含该A / D转换器的微控制器中，对于每个A / D转换，模拟输入通道的选择模式的数量增加，并且使用仅具有基本功能的A / D转换器进行A / D转换，而不施加加载到CPU上 A / D转换器或DMA传输装置包括包括一个或多个条目的A / D转换表。每个条目包括用于设置是否对各个模拟输入通道执行A / D转换的使能位以及用于设置A / D转换执行次数的多个计数号位。

8. 发明授权

US06657459B2 Gate circuit and semiconductor circuit to process low amplitude signals, memory, processor and information processing system manufactured by use of them 失效
公开(公告)号：US06657459B2
公开(公告)日：2003-12-02
申请号：US10143762
申请日：2002-05-14
申请人： Yoji Nishio , Kosaku Hirose , Hideo Hara , Katsunori Koike , Kayoko Nemoto , Tatsumi Yamauchi , Fumio Murabayashi , Hiromichi Yamada
发明人： Yoji Nishio , Kosaku Hirose , Hideo Hara , Katsunori Koike , Kayoko Nemoto , Tatsumi Yamauchi , Fumio Murabayashi , Hiromichi Yamada
IPC分类号： H03K19096
CPC分类号： H03K3/3565 , H03K19/018521
摘要： A semiconductor integrated circuit device, responsive to an input signal having a low amplitude and short transition time, operates with low power consumption and prevents the flow of breakthrough current. In an example circuit thereof, the input signal is transmitted through an NMOS pass transistor to the gate of a first NMOS transistor and is applied, through a second NMOS transistor, to the gate of a first PMOS transistor, the first PMOS transistor performing complementary operation with the first NMOS transistor through the second NMOS transistor; the gate of the first PMOS transistor is connected to the power supply potential through the second PMOS transistor; the gate of the second NMOS transistor is connected to the power supply potential; and the gate of the second PMOS transistor is controlled by the signal at a common drain connection of the first NMOS and first PMOS transistors.

9. 发明授权

US06477319B1 Image recording apparatus which sends charasteristic/correction signals whenever new look-up table are selected or a pre-selected number of pages have been printed 失效
标题翻译：每当选择新的查找表或者已经打印了预先选择的页数时，发送特征/校正信号的图像记录装置
公开(公告)号：US06477319B1
公开(公告)日：2002-11-05
申请号：US09375489
申请日：1999-08-17
申请人： Michio Ito , Masaharu Ohkubo , Hiroshi Sasame , Hiromichi Yamada , Masaki Ojima , Kaoru Seto , Hiroshi Mano , Atsushi Kashihara , Takashi Kawana
发明人： Michio Ito , Masaharu Ohkubo , Hiroshi Sasame , Hiromichi Yamada , Masaki Ojima , Kaoru Seto , Hiroshi Mano , Atsushi Kashihara , Takashi Kawana
IPC分类号： H04N5225
CPC分类号： H04N1/295 , H04N1/2315 , H04N1/4005 , H04N1/4056 , H04N1/407 , H04N2201/0082 , H04N2201/33314
摘要： An image recording apparatus for recording image data from an external apparatus is provided, which receives the image data as an image signal from the external apparatus, records the received image signal, and outputs a characteristic signal regarding a recording characteristic of the recording apparatus to the external apparatus.
摘要翻译：提供一种用于从外部装置记录图像数据的图像记录装置，其接收来自外部装置的图像数据的图像数据，记录接收到的图像信号，并将关于记录装置的记录特性的特征信号输出到外部设备

10. 发明授权

US6047149A Image forming apparatus having a rotatable first developing member, and a fixed second developing member having a housing partially covering the first developing member 失效
标题翻译：具有可旋转的第一显影部件的图像形成装置和具有部分地覆盖第一显影部件的壳体的固定的第二显影部件
公开(公告)号：US6047149A
公开(公告)日：2000-04-04
申请号：US348221
申请日：1994-11-28
申请人： Katsuhiko Nishimura , Kimio Nakahata , Masuo Yamazaki , Masami Takeda , Hiromichi Yamada , Tatsuya Nakamura , Tohru Saitou , Tohru Kosaka , Takashi Shibuya , Yasuo Yoda , Masahide Hirai
发明人： Katsuhiko Nishimura , Kimio Nakahata , Masuo Yamazaki , Masami Takeda , Hiromichi Yamada , Tatsuya Nakamura , Tohru Saitou , Tohru Kosaka , Takashi Shibuya , Yasuo Yoda , Masahide Hirai
IPC分类号： G03G15/00 , G03G15/01 , G03G21/00 , G03G21/16
CPC分类号： G03G15/0126 , G03G2215/0174
摘要： An image forming apparatus including a rotatable developing member having a plurality of developing devices for developing an image bearing member at a first developing station, and a second single developing device arranged upstream of the rotatable developing member for developing the image bearing member exclusively at a second developing station different from the first developing station. The second developing device has a cover portion covering the rotatable developing member, and a portion of the cover portion is disposed at a position spaced apart from a rotation axis of the rotatable developing member by a predetermined length in a horizontal direction away from the image bearing member. The rotatable developing member rotates in an opposite direction with respect to the direction of rotation of the image bearing member to prevent toner from scattering toward the optical system.
摘要翻译：一种图像形成装置，包括具有多个用于在第一显影站显影图像承载部件的显影装置的可旋转显影部件和设置在可转动显影部件上游的第二单一显影装置，用于仅在第二显影步骤发展站不同于第一个发展站。第二显影装置具有覆盖可旋转显影构件的盖部分，并且盖部分的一部分设置在远离可转动显影构件的旋转轴线的距离图像承载的水平方向上预定长度的位置会员。可旋转的显影构件相对于图像承载构件的旋转方向沿相反的方向旋转，以防止调色剂向光学系统散射。

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