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1. 发明授权

US07825480B2 Power semiconductor device and manufacturing method of the same 有权
标题翻译：功率半导体器件及其制造方法相同
公开(公告)号：US07825480B2
公开(公告)日：2010-11-02
申请号：US12132610
申请日：2008-06-04
申请人： Hiroki Arai , Nobuyuki Shirai , Tsuyoshi Kachi
发明人： Hiroki Arai , Nobuyuki Shirai , Tsuyoshi Kachi
IPC分类号： H01L27/088
CPC分类号： H01L29/7811 , H01L29/0615 , H01L29/0619 , H01L29/0638 , H01L29/0696 , H01L29/402 , H01L29/41766 , H01L29/4238 , H01L29/66727 , H01L29/66734 , H01L29/7813
摘要： The characteristics of a semiconductor device including a trench-gate power MISFET are improved. The semiconductor device includes a substrate having an active region where the power MISFET is provided and an outer circumferential region which is located circumferentially outside the active region and where a breakdown resistant structure is provided, a pattern formed of a conductive film provided over the substrate in the outer circumferential region with an insulating film interposed therebetween, another pattern isolated from the pattern, and a gate electrode terminal electrically coupled to the gate electrodes of the power MISFET and provided in a layer over the conductive film. The conductive film of the pattern is electrically coupled to the gate electrode terminal, while the conductive film of another pattern is electrically decoupled from the gate electrode terminal.
摘要翻译：提高了包括沟槽栅极功率MISFET的半导体器件的特性。半导体器件包括具有设置有功率MISFET的有源区域的基板和位于有源区域的周向外侧并且设有耐击穿结构的外周区域，由设置在基板上的导电膜形成的图案具有介于其间的绝缘膜的外周区域，与图案隔离的另一图案，以及电连接到功率MISFET的栅电极并设置在导电膜上的层中的栅电极端子。图案的导电膜电耦合到栅电极端子，而另一图案的导电膜与栅电极端子电耦合。

2. 发明授权

US08546223B2 Semiconductor device and manufacturing method of the same 有权
标题翻译：半导体器件及其制造方法相同
公开(公告)号：US08546223B2
公开(公告)日：2013-10-01
申请号：US12889343
申请日：2010-09-23
申请人： Hiroki Arai , Nobuyuki Shirai , Tsuyoshi Kachi
发明人： Hiroki Arai , Nobuyuki Shirai , Tsuyoshi Kachi
IPC分类号： H01L21/336
CPC分类号： H01L29/7811 , H01L29/0615 , H01L29/0619 , H01L29/0638 , H01L29/0696 , H01L29/402 , H01L29/41766 , H01L29/4238 , H01L29/66727 , H01L29/66734 , H01L29/7813
摘要： The characteristics of a semiconductor device including a trench-gate power MISFET are improved. The semiconductor device includes a substrate having an active region where the power MISFET is provided and an outer circumferential region which is located circumferentially outside the active region and where a breakdown resistant structure is provided, a pattern formed of a conductive film provided over the substrate in the outer circumferential region with an insulating film interposed therebetween, another pattern isolated from the pattern, and a gate electrode terminal electrically coupled to the gate electrodes of the power MISFET and provided in a layer over the conductive film. The conductive film of the pattern is electrically coupled to the gate electrode terminal, while the conductive film of another pattern is electrically decoupled from the gate electrode terminal.
摘要翻译：提高了包括沟槽栅极功率MISFET的半导体器件的特性。半导体器件包括具有设置有功率MISFET的有源区域的基板和位于有源区域的周向外侧并且设有耐击穿结构的外周区域，由设置在基板上的导电膜形成的图案具有介于其间的绝缘膜的外周区域，与图案隔离的另一图案，以及电连接到功率MISFET的栅电极并设置在导电膜上的层中的栅电极端子。图案的导电膜电耦合到栅电极端子，而另一图案的导电膜与栅电极端子电耦合。

3. 发明申请

US20090008708A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20090008708A1
公开(公告)日：2009-01-08
申请号：US12132610
申请日：2008-06-04
申请人： Hiroki Arai , Nobuyuki Shirai , Tsuyoshi Kachi
发明人： Hiroki Arai , Nobuyuki Shirai , Tsuyoshi Kachi
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7811 , H01L29/0615 , H01L29/0619 , H01L29/0638 , H01L29/0696 , H01L29/402 , H01L29/41766 , H01L29/4238 , H01L29/66727 , H01L29/66734 , H01L29/7813
摘要： The characteristics of a semiconductor device including a trench-gate power MISFET are improved. The semiconductor device includes a substrate having an active region where the power MISFET is provided and an outer circumferential region which is located circumferentially outside the active region and where a breakdown resistant structure is provided, a pattern formed of a conductive film provided over the substrate in the outer circumferential region with an insulating film interposed therebetween, another pattern isolated from the pattern, and a gate electrode terminal electrically coupled to the gate electrodes of the power MISFET and provided in a layer over the conductive film. The conductive film of the pattern is electrically coupled to the gate electrode terminal, while the conductive film of another pattern is electrically decoupled from the gate electrode terminal.
摘要翻译：提高了包括沟槽栅极功率MISFET的半导体器件的特性。半导体器件包括具有设置有功率MISFET的有源区域的基板和位于有源区域的周向外侧并且设有耐击穿结构的外周区域，由设置在基板上的导电膜形成的图案具有介于其间的绝缘膜的外周区域，与图案隔离的另一图案，以及电连接到功率MISFET的栅电极并设置在导电膜上的层中的栅电极端子。图案的导电膜电耦合到栅电极端子，而另一图案的导电膜与栅电极端子电耦合。

4. 发明授权

US09104609B2 Information processing apparatus, system time synchronization method and computer readable medium 有权
标题翻译：信息处理装置，系统时间同步方法和计算机可读介质
公开(公告)号：US09104609B2
公开(公告)日：2015-08-11
申请号：US13846090
申请日：2013-03-18
申请人： Hiroki Arai
发明人： Hiroki Arai
IPC分类号： G06F11/00 , G06F11/14 , G06F1/14 , G06F11/20
CPC分类号： G06F11/1402 , G06F1/14 , G06F11/2038
摘要： The time in the chipset of backup resources is synchronized easily at the system time.An information processing apparatus including: an operational chipset which includes a first Real Time Clock (RTC); a backup chipset which includes a second RTC: a third RTC which times system time; a difference time calculation unit which calculates a difference time between a system time periodically notified of from the first RTC of the operational chipset and the system time which the third RTC times; a holding unit which holds the difference time; a calculation unit which calculates a temporary system time which is set to the second RTC of the backup chipset to which a chipset switching operated, based on the system time of the third RTC and the difference time at the time of the chipset switching; and a configuration unit which sets the temporary system time to the second RTC of the backup chipset.
摘要翻译：备份资源芯片组的时间在系统时间很容易同步。一种信息处理设备，包括：操作芯片组，其包括第一实时时钟（RTC）; 包括第二RTC的备用芯片组：第三个RTC，系统时间; 差分时间计算单元，计算从操作芯片组的第一RTC周期性地通知的系统时间与第三RTC时间的系统时间之间的差时间; 保持差时间的保持单元; 计算单元，其基于第三RTC的系统时间和芯片组切换时的差时间，计算设置为进行芯片组切换操作的备用芯片组的第二RTC的临时系统时间; 以及将临时系统时间设置为备用芯片组的第二RTC的配置单元。

5. 发明申请

US20130035440A1 POLYARYLENE SULFIDE RESIN COMPOSITION 审中-公开
标题翻译：聚亚烷基硫酸酯树脂组合物
公开(公告)号：US20130035440A1
公开(公告)日：2013-02-07
申请号：US13641839
申请日：2011-04-07
申请人： Raita Nishikawa , Hiroki Arai , Katsuhei Ohnishi
发明人： Raita Nishikawa , Hiroki Arai , Katsuhei Ohnishi
IPC分类号： C08L81/04 , C08K7/14 , B29C45/00
CPC分类号： C08L81/02 , B29C45/0001 , B29K2081/00 , C08K7/14 , C08L77/12
摘要： To provide a polyarylene sulfide resin composition which contains decreased amount of chlorine, which has a high fluidity and generates small flashes at the time of molding, which has an excellent heat resistance, which can resist heat-processing under the condition of a high temperature, which has moldability at a low mold temperature, a molded article of which has an extremely small change in surface hue before and after reflow. The resin composition is obtained by blending: 100 parts by weight of a polyarylene sulfide resin (A) containing 500 to 2,000 ppm of chlorine and having 10 to 200 Pa·s of melt viscosity, 10 to 100 parts by weight of a liquid crystalline polyester amide resin (B), and 5 to 250 parts by weight of glass fiber (C) containing 100 ppm or less of nitrogen, and having a total chlorine content of 950 ppm or less,
摘要翻译：本发明提供一种聚酰亚胺硫化物树脂组合物，该组合物在高温下能够耐热处理，具有流动性高，成型时产生小的闪光，具有优异的耐热性，其在低模具温度下具有成型性，其成型制品在回流之前和之后具有非常小的表面色调变化。树脂组合物通过以下方法获得：将100重量份含有500-2000ppm氯和10-200Pa·s熔体粘度的聚芳硫醚树脂（A），10至100重量份的液晶聚酯酰胺树脂（B）和5〜250重量份含有100ppm以下的氮，总氯含量为950ppm以下的玻璃纤维（C）

6. 发明申请

US20050022737A1 Semiconductor-processing apparatus provided with susceptor and placing block 有权
标题翻译：设有基座和放置块的半导体处理设备
公开(公告)号：US20050022737A1
公开(公告)日：2005-02-03
申请号：US10897061
申请日：2004-07-22
申请人： Akira Shimizu , Hideaki Fukuda , Hiroki Arai , Baiei Kawano , Takayuki Yamagishi
发明人： Akira Shimizu , Hideaki Fukuda , Hiroki Arai , Baiei Kawano , Takayuki Yamagishi
IPC分类号： H01L21/683 , C23C16/00 , C23C16/458 , H01L21/205 , H01L21/677 , H01L21/68
CPC分类号： C23C16/4585
摘要： A semiconductor-processing apparatus comprises a susceptor and removable placing blocks detachably placed at a periphery of the susceptor for transferring a substrate. Retractable supporting members are provided for detaching/attaching the placing blocks from/to the susceptor.
摘要翻译：半导体处理装置包括基座和可拆卸地放置在基座周边的可拆卸放置块，用于传送基板。提供可伸缩的支撑构件用于将放置块从基座分离/附接到基座。

7. 发明申请

US20090286928A1 CARBON NANOTUBE GRAFTED WITH LOW-MOLECULAR WEIGHT POLYANILINE AND DISPERSION THEREOF 审中-公开
标题翻译：碳纳米管用低分子量聚苯胺和其分散体
公开(公告)号：US20090286928A1
公开(公告)日：2009-11-19
申请号：US12270687
申请日：2008-11-13
申请人： Tatsuhiro TAKAHASHI , Noriyuki Kuramoto , Koichiro Yonetake , Osamu Haba , Hiroshi Awano , Hiroki Arai , Teruya Goto , Yushi Yamaguchi , Naoya Nishimura , Masahiro Hida , Masaaki Ozawa , Mitsunobu Matsumura
发明人： Tatsuhiro TAKAHASHI , Noriyuki Kuramoto , Koichiro Yonetake , Osamu Haba , Hiroshi Awano , Hiroki Arai , Teruya Goto , Yushi Yamaguchi , Naoya Nishimura , Masahiro Hida , Masaaki Ozawa , Mitsunobu Matsumura
IPC分类号： C08L77/06 , C08G69/26
CPC分类号： C08G73/0266 , B82Y30/00 , B82Y40/00 , C08K7/24
摘要： Chemically modified carbon nanotubes composed of carbon nanotubes (such as multiwall carbon nanotubes) having carboxyl groups on the surface thereof and polymeric aniline (such as 3- to 300-meric aniline) bonding thereto through the amide linkage. The chemically modified carbon nanotubes exhibit good affinity with organic solvents and readily disperse into organic solvents.
摘要翻译：由其表面具有羧基的碳纳米管（例如多壁碳纳米管）和通过酰胺键与其结合的聚合苯胺（例如3-至300-聚对苯胺）构成的化学改性的碳纳米管。化学改性的碳纳米管与有机溶剂呈现良好的亲和性，易分散于有机溶剂中。

8. 发明申请

US20090022980A1 Reinforcing bar material coated with high adhesion anticorrosion film and method of producing the same 审中-公开
标题翻译：涂覆有高附着力防腐蚀膜的钢筋材料及其制造方法
公开(公告)号：US20090022980A1
公开(公告)日：2009-01-22
申请号：US11826470
申请日：2007-07-16
申请人： Teruhiko Sugimoto , Rikuta Murakami , Mitsuru Takeuchi , Yasuhiro Arai , Hiroki Arai , Kaoru Arai , Yasuharu Kida
发明人： Teruhiko Sugimoto , Rikuta Murakami , Mitsuru Takeuchi , Yasuhiro Arai , Hiroki Arai , Kaoru Arai , Yasuharu Kida
IPC分类号： B32B5/16 , B05D1/36
CPC分类号： B05D7/14 , B05D1/02 , B05D5/00 , B05D5/02 , B05D7/54 , B05D2602/00 , E04C5/015 , E04C5/03 , Y10T428/254
摘要： The present invention provides a reinforcing bar material coated with a high adhesion anticorrosion film that enables to increase adhesion strength to concrete, which comprises forming two layers of anticorrosion films on a surface of a reinforcing bar material by means of spraying an epoxy powder coating material under a temperature condition where performance of the epoxy resin can be retained, so as to solve a pin hole problem that inevitably occurs in an anticorrosion film, and also to exhibit firm projections in a state coated with the epoxy resin on the second layer of anticorrosion film.The present invention comprises heating a reinforcing bar material, spraying and melt-adhering an epoxy powder coating material onto the reinforcing bar material while a temperature on a surface of the reinforcing bar material is between 200 and 250° C. so as to form a first anticorrosion film, and also, under this temperature condition, spraying and melt-adhering an epoxy powder coating material with acrylic resin beads having a particle diameter 2.5 to 3 times that of the epoxy resin powder mixed in on a surface of the first anticorrosion film in a molten state so as to form a second anticorrosion film, followed by cooling the reinforcing bar material coated with the first and second anticorrosion films to prepare the reinforcing bar material coated with a high adhesion anticorrosion film having countless projections formed by the second anticorrosion film.
摘要翻译：本发明提供一种涂覆有高粘合性防腐蚀膜的钢筋材料，其能够增加对混凝土的粘合强度，其包括在钢筋材料的表面上通过喷涂环氧粉末涂料来形成两层防腐蚀膜可以保持环氧树脂的性能的温度条件，以解决在防腐蚀膜中不可避免地发生的针孔问题，并且在涂覆有环氧树脂的状态下在第二层防腐膜上显示出牢固的突起。本发明包括加热钢筋材料，将环氧粉末涂料喷涂和熔融粘附到钢筋材料上，同时钢筋材料表面的温度在200-250℃之间，以形成第一并且在该温度条件下，将环氧粉末涂料与在第一防腐蚀膜的表面上混合的环氧树脂粉末的粒径为2.5〜3倍的丙烯酸树脂珠喷雾和熔融粘合熔融状态以形成第二防腐蚀膜，然后冷却涂覆有第一和第二防腐蚀膜的钢筋材料，以制备涂覆有具有由第二防腐蚀膜形成的无数突起的高粘附性防腐蚀膜的钢筋材料。

9. 发明申请

US20070033299A1 Information processing device, and CPU, method of startup and program product of information processing device 审中-公开
标题翻译：信息处理设备，CPU，信息处理设备的启动和程序产品的方法
公开(公告)号：US20070033299A1
公开(公告)日：2007-02-08
申请号：US11495733
申请日：2006-07-31
申请人： Hiroki Arai
发明人： Hiroki Arai
IPC分类号： G06F3/00 , G06F13/00
CPC分类号： H04N1/32561 , G06F9/4405 , G06F15/177 , H04N1/00954 , H04N1/0096 , H04N1/32587 , H04N1/32593
摘要： In the information processing device of the invention, the region to be scanned is divided and assigned into as many parts as there are CPUs installed in the information processing device, each CPU scans hardware resources under its control respectively, and the main CPU integrates the scanning result at the end. According to the invention, the time necessary to scan the hardware resource can be reduced, and the startup time of the information processing device can also be reduced.
摘要翻译：在本发明的信息处理装置中，要扫描的区域被划分成与安装在信息处理装置中的CPU一样多的部分，每个CPU分别扫描其控制的硬件资源，并且主CPU将扫描结果结束了。根据本发明，可以减少扫描硬件资源所需的时间，并且还可以减少信息处理装置的启动时间。

10. 发明授权

US06586163B1 Method of forming fine pattern 有权
标题翻译：形成精细图案的方法
公开(公告)号：US06586163B1
公开(公告)日：2003-07-01
申请号：US09587359
申请日：2000-06-02
申请人： Ichiro Okabe , Hiroki Arai
发明人： Ichiro Okabe , Hiroki Arai
IPC分类号： G03F700
CPC分类号： G03F7/091 , G03F7/0045 , G03F7/16
摘要： There is described a method of forming a fine pattern aimed at depositing a silicon-nitride-based anti-reflection film which is stable even at high temperature and involves small internal stress. The method is also intended to preventing occurrence of a footing pattern (a rounded corner) in a boundary surface between a photoresist and a substrate at the time of formation of a chemically-amplified positive resist pattern on the anti-reflection film. The method includes the steps of forming a silicon-nitride-based film directly on a substrate or on a substrate by way of another layer; and forming a photoresist directly on the silicon-nitride-based film or on the silicon-nitride-based film by way of another layer. The silicon-nitride-based film is deposited while the temperature at which the substrate is to be situated is set so as to fall within the range of 400 to 700° C., through use of a plasma CVD system. The method further includes a step of depositing a silicon-oxide-based film immediately below the photoresist. The silicon-oxide-based film is deposited while the temperature at which the substrate is to be situated is set so as to fall within the range of 400 to 700° C., through use of a plasma CVD system.
摘要翻译：描述了一种形成精细图案的方法，其目的在于沉积即使在高温下也是稳定且涉及小的内应力的氮化硅基抗反射膜。该方法还旨在防止在防反射膜上形成化学放大的正抗蚀剂图案时光致抗蚀剂和基板之间的边界表面中的基脚图案（圆角）的发生。该方法包括以下步骤：通过另一层直接在衬底或衬底上形成氮化硅基膜; 以及通过另一层在氮化硅基膜或氮化硅基膜上直接形成光致抗蚀剂。通过使用等离子体CVD系统，将基板的位置的温度设定为400〜700℃的范围，来沉积氮化硅基膜。该方法还包括在光致抗蚀剂正下方沉积氧化硅基膜的步骤。通过使用等离子体CVD系统，将基板的位置的温度设定为400〜700℃的范围内，沉积硅氧化物系膜。

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