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1. 发明授权

US06826081B2 Nonvolatile semiconductor memory device, nonvolatile semiconductor memory device-integrated system, and defective block detecting method 有权
公开(公告)号：US06826081B2
公开(公告)日：2004-11-30
申请号：US10638418
申请日：2003-08-12
申请人： Hirokazu Nagashima , Shoichi Kawamura
发明人： Hirokazu Nagashima , Shoichi Kawamura
IPC分类号： G11C1606
CPC分类号： G11C29/26 , G11C16/04
摘要： In a block which is a target of detection of flag data, a page buffer 100 reads data of memory cells 42 of each memory cell by block unit, and latches the data. A detection circuit 28 performs detection of the flag data for each block based on output of the page buffers 100 of one block.

2. 发明授权

US08040730B2 Nonvolatile memory device 失效
标题翻译：非易失性存储器件
公开(公告)号：US08040730B2
公开(公告)日：2011-10-18
申请号：US12625723
申请日：2009-11-25
申请人： Masahito Takehara , Shoichi Kawamura
发明人： Masahito Takehara , Shoichi Kawamura
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/3454 , G11C2211/5621
摘要： A nonvolatile semiconductor memory device includes a memory cell array and a control circuit configured to control reading and programming operations for reading data from and inputting data to the memory cell array, respectively. The control circuit includes first and second units. The first unit is configured to count a number of bits having logic 0 or a number of bits having logic 1, to set a logic where the counted number is greater than n/2 as an initial state to regenerate programming data, and to perform a programming operation based on the regenerated data, when simultaneously programming the programming data of n bits input for a designated address. The second unit is configured to program a recognition bit for recognizing which of the logic 0 and the logic 1 the initial state of the memory cell of the designated address is in, when the programming operation is performed.
摘要翻译：非易失性半导体存储器件包括存储单元阵列和控制电路，该控制电路被配置为分别控制从存储单元阵列读取数据和向存储单元阵列输入数据的读取和编程操作。控制电路包括第一和第二单元。第一单元被配置为对具有逻辑0或具有逻辑1的位数的位数进行计数，以将计数数大于n / 2的逻辑设置为初始状态，以重新生成编程数据，并且执行当对指定地址进行n位输入的编程数据同时编程时，基于再生数据进行编程操作。第二单元被配置为在执行编程操作时对识别位进行编程以识别逻辑0和逻辑1中的哪一个指定地址的存储单元的初始状态。

3. 发明申请

US20100135081A1 NONVOLATILE MEMORY DEVICE 失效
标题翻译：非易失性存储器件
公开(公告)号：US20100135081A1
公开(公告)日：2010-06-03
申请号：US12625723
申请日：2009-11-25
申请人： Shoichi Kawamura , Masahito Takehara
发明人： Shoichi Kawamura , Masahito Takehara
IPC分类号： G11C7/00 , G11C16/10 , G11C16/26
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/3454 , G11C2211/5621
摘要： A nonvolatile semiconductor memory device includes a memory cell array and a control circuit configured to control reading and programming operations for reading data from and inputting data to the memory cell array, respectively. The control circuit includes first and second units. The first unit is configured to count a number of bits having logic 0 or a number of bits having logic 1, to set a logic where the counted number is greater than n/2 as an initial state to regenerate programming data, and to perform a programming operation based on the regenerated data, when simultaneously programming the programming data of n bits input for a designated address. The second unit is configured to program a recognition bit for recognizing which of the logic 0 and the logic 1 the initial state of the memory cell of the designated address is in, when the programming operation is performed.
摘要翻译：非易失性半导体存储器件包括存储单元阵列和控制电路，该控制电路被配置为分别控制从存储单元阵列读取数据和向存储单元阵列输入数据的读取和编程操作。控制电路包括第一和第二单元。第一单元被配置为对具有逻辑0或具有逻辑1的位数的位数进行计数，以将计数数大于n / 2的逻辑设置为初始状态，以重新生成编程数据，并且执行当对指定地址进行n位输入的编程数据同时编程时，基于再生数据进行编程操作。第二单元被配置为在执行编程操作时对识别位进行编程以识别逻辑0和逻辑1中的哪一个指定地址的存储单元的初始状态。

4. 发明授权

US08605512B2 Nonvolatile semiconductor memory device and method of operating a nonvolatile memory device 有权
标题翻译：非易失性半导体存储器件以及非易失性存储器件的操作方法
公开(公告)号：US08605512B2
公开(公告)日：2013-12-10
申请号：US13329372
申请日：2011-12-19
申请人： Shoichi Kawamura , Tomohisa Miyamoto
发明人： Shoichi Kawamura , Tomohisa Miyamoto
IPC分类号： G11C11/40
CPC分类号： G11C16/3413 , G11C16/0483 , G11C16/08 , G11C16/3463 , G11C2216/14
摘要： A nonvolatile memory device includes a memory cell array including a plurality of bitlines, a plurality of wordlines, and a plurality of memory cells. The memory device further includes a plurality of page buffers coupled to the respective bitlines of the memory cell array, each page buffer including a latch configured to store data to be written into and read from a memory cell coupled to a respective bitline of the memory cell array. The memory device further includes a control circuit configured to execute an over-program verify operation which includes detecting an over-programmed memory cell among the plurality of memory cells with reference to pass/fail data stored in the respective latches of the plurality of page buffers, and decreasing a threshold voltage of a detected over-programmed memory cell while maintaining a threshold voltage of memory cells which have not been detected as being over-programmed.
摘要翻译：非易失性存储器件包括包括多个位线，多个字线和多个存储器单元的存储单元阵列。存储器装置还包括耦合到存储器单元阵列的相应位线的多个页缓冲器，每个页缓冲器包括锁存器，其被配置为存储要写入到耦合到存储器单元的相应位线的存储器单元中并从其读取的数据数组。该存储装置还包括控制电路，该控制电路被配置为执行过程编程验证操作，该操作包括参考存储在多个页缓冲器的相应锁存器中的通过/失败数据来检测多个存储器单元中的过度编程的存储器单元并且在保持未被检测为过度编程的存储器单元的阈值电压的同时降低检测到的过度编程的存储单元的阈值电压。

5. 发明授权

US08264891B2 Erase method and non-volatile semiconductor memory 有权
标题翻译：擦除方法和非易失性半导体存储器
公开(公告)号：US08264891B2
公开(公告)日：2012-09-11
申请号：US12535903
申请日：2009-08-05
申请人： Shoichi Kawamura
发明人： Shoichi Kawamura
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/344 , G11C16/14 , G11C16/16
摘要： An erase method for a non-volatile memory device having a defined erase unit divided into first and second inner erase units includes; applying an erase voltage to at least one of the first and second inner erase units in accordance with respective states of corresponding first and second fail flags, after applying the erase voltage to the at least one of the first and second inner erase units, performing an erase verification on the at least one of the first and second inner erase units, and updating the at least one of the first and second fail flags in accordance with erase verification results.
摘要翻译：具有划分为第一和第二内部擦除单元的限定的擦除单元的非易失性存储器件的擦除方法包括：在将擦除电压施加到第一和第二内部擦除单元中的至少一个之后，根据相应的第一和第二故障标志的相应状态，向第一和第二内部擦除单元中的至少一个施加擦除电压，在第一和第二内部擦除单元中的至少一个擦除验证，以及根据擦除验证结果更新第一和第二失败标志中的至少一个。

6. 发明授权

US06738288B2 Semiconductor memory 有权
标题翻译：半导体存储器
公开(公告)号：US06738288B2
公开(公告)日：2004-05-18
申请号：US10459427
申请日：2003-06-12
申请人： Shoichi Kawamura , Masaru Yano
发明人： Shoichi Kawamura , Masaru Yano
IPC分类号： G11C1600
CPC分类号： G11C16/105 , G11C8/12 , G11C16/10 , G11C16/102 , G11C2216/14
摘要： A nonvolatile semiconductor memory with a plurality of banks in which copy back is performed between banks. An input circuit accepts input of a copy back command which requests a data transfer in the memory. When the copy back command is input from the input circuit, a judgment circuit judges whether a source and a destination are in the same bank. If the judgment circuit judges that the source and the destination are in the same bank, a first transfer circuit transfers data in the same bank. If the judgment circuit judges that the source and the destination are in different banks, a second transfer circuit transfers data between the two different banks.
摘要翻译：具有多个银行的非易失性半导体存储器，其中在存储体之间执行复制。输入电路接受请求数据在存储器中传输的复制命令的输入。当从输入电路输入复制命令时，判断电路判断源和目的地是否在同一个存储体中。如果判断电路判定源和目的地在同一个存储体中，则第一传送电路在同一个存储体中传送数据。如果判断电路判定源和目的地在不同的存储体中，则第二传送电路在两个不同的存储体之间传送数据。

7. 发明授权

US06288944B1 NAND type nonvolatile memory with improved erase-verify operations 有权
标题翻译： NAND型非易失性存储器，具有改进的擦除验证操作
公开(公告)号：US06288944B1
公开(公告)日：2001-09-11
申请号：US09577373
申请日：2000-05-23
申请人： Shoichi Kawamura
发明人： Shoichi Kawamura
IPC分类号： G11C1606
CPC分类号： G11C16/3445 , G11C16/26 , G11C16/344
摘要： The invention provides a NAND type nonvolatile memory comprising: a sense circuit 100 having a constant current supply source P7 connected to a bit line to which memory cells are connected and a sense transistor N8 for sensing potential at the connection point thereof; a first reference potential ARVss on the opposite side from the bit line of the memory cells; and a second reference potential PBVss to which the source of the sense transistor is connected, wherein during Erase-verify operations the first reference potential ARVss and the second reference potential PBVss are controlled to predetermined positive potential. By controlling the first reference potential ARVss to positive potential, the control gate level of a memory cell can be equivalently brought to Erase-verify level (which is negative), and by further controlling the second reference potential PBVss of the sense transistor N8 to positive potential as well, the equivalent threshold voltage of the sense transistor N8 can be increased, or the equivalent trip level of the sense inverter increased, thereby solving the conventional problems associated with Erase-verify operations.
摘要翻译：本发明提供了一种NAND型非易失性存储器，包括：感测电路100，其具有连接到与存储单元连接的位线的恒定电流源P7和用于感测其连接点处的电位的读出晶体管N8; 与存储器单元的位线相对的第一参考电位ARVss; 以及连接感测晶体管的源极的第二参考电位PBVss，其中在擦除验证操作期间，将第一参考电位ARVss和第二参考电位PBVss控制到预定的正电位。通过将第一参考电位ARVS控制为正电位，可以将存储单元的控制栅极电平等效地设置为擦除验证电平（其为负），并且通过进一步将读出晶体管N8的第二参考电位PBVss控制为正电位也可以提高感测晶体管N8的等效阈值电压，或者增加感测反相器的等效跳闸电平，从而解决与擦除验证操作相关的常规问题。

8. 发明授权

US06266271B1 Nonvolatile semiconductor memory for preventing unauthorized copying 有权
标题翻译：用于防止未授权复制的非易失性半导体存储器
公开(公告)号：US06266271B1
公开(公告)日：2001-07-24
申请号：US09572318
申请日：2000-05-18
申请人： Shoichi Kawamura
发明人： Shoichi Kawamura
IPC分类号： G11C1134
CPC分类号： G11C16/22
摘要： The present invention is a nonvolatile semiconductor memory having, in addition to a main storage region for storing ordinary data, a hidden storage region for storing a special code for preventing unauthorized copying, and this hidden storage region is in a read enabled state at the time of a write protected state, and is in a read prohibited state at a time when there is no write protected state. Therefore, a hidden storage region can be read out only after a semiconductor memory vendor stores a special code in a hidden storage region, and sets the hidden storage region to a write protected state. And the method for changing to this write protected state is a secret to everyone other than the vendor. As a result thereof, even if a semiconductor memory, for which a special code is not stored in a hidden storage region, is illegally obtained on the black market, since hidden storage region readout is still prohibited, illegally copied data cannot be used, consequently preventing unauthorized copying.
摘要翻译：本发明是一种非易失性半导体存储器，除了用于存储普通数据的主存储区域之外，还具有用于存储用于防止未授权复制的特殊代码的隐藏存储区域，并且该隐藏存储区域当时处于读取使能状态的写保护状态，并且在没有写保护状态的时候处于读禁止状态。因此，只有在半导体存储器供应商将特殊代码存储在隐藏存储区域中之后，才能够读出隐藏存储区域，并将隐藏存储区域设置为写保护状态。而转换为写保护状态的方法对供应商以外的每个人来说都是一个秘密。其结果是，即使在黑市上非法获得特殊代码不存储在隐藏存储区域中的半导体存储器，由于隐藏的存储区域读出仍被禁止，因此不能使用非法复制的数据防止未经授权的复制。

9. 发明授权

US07872917B2 Non-volatile semiconductor memory device and memory system including the same 有权
标题翻译：非易失性半导体存储器件和包括其的存储器系统
公开(公告)号：US07872917B2
公开(公告)日：2011-01-18
申请号：US12335956
申请日：2008-12-16
申请人： Shoichi Kawamura
发明人： Shoichi Kawamura
IPC分类号： G11C16/06 , G11C16/04
CPC分类号： G11C8/14 , G11C16/16
摘要： Provided is a non-volatile semiconductor device. The non-volatile semiconductor memory devices including: first and second word line groups disposed in parallel; dummy word lines disposed between the first and second word line groups; a first bit line group intersecting the first word line group; and a second bit line group intersecting the second word line group, wherein the first and second word line groups, the first and second bit line groups, and the dummy word lines are disposed on a same well.
摘要翻译：提供了一种非易失性半导体器件。所述非易失性半导体存储器件包括：平行设置的第一和第二字线组; 设置在第一和第二字线组之间的虚拟字线; 与第一字线组相交的第一位线组; 以及与第二字线组相交的第二位线组，其中第一和第二字线组，第一和第二位线组以及虚拟字线被布置在同一个孔中。

10. 发明申请

US20070139990A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20070139990A1
公开(公告)日：2007-06-21
申请号：US11612173
申请日：2006-12-18
申请人： Kazunari Kido , Shoichi Kawamura
发明人： Kazunari Kido , Shoichi Kawamura
IPC分类号： G11C15/00
CPC分类号： G11C16/26 , G11C16/24
摘要： A nonvolatile semiconductor memory device has a high read output and is not affected by a noise of adjacent bit lines. The memory device is capable of performing high speed read operations. Each bit of a memory as formed by a plurality of memory cells. The memory cells each have the same structure as the structure of a memory cell of the main memory. During a read operation, the bit line is selected and proximate bit lines proximate to the selected bit line are not selected. The nonvolatile semiconductor memory device is formed together with the main memory on one chip by the same process.
摘要翻译：非易失性半导体存储器件具有高读取输出，并且不受相邻位线的噪声的影响。存储器件能够执行高速读取操作。由多个存储单元形成的存储器的每一位。每个存储单元具有与主存储器的存储单元的结构相同的结构。在读操作期间，选择位线，并且不选择靠近所选位线的位线。非易失性半导体存储器件通过相同的工艺与主存储器一起形成在一个芯片上。

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