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1. 发明授权

US08040730B2 Nonvolatile memory device 失效
标题翻译：非易失性存储器件
公开(公告)号：US08040730B2
公开(公告)日：2011-10-18
申请号：US12625723
申请日：2009-11-25
申请人： Masahito Takehara , Shoichi Kawamura
发明人： Masahito Takehara , Shoichi Kawamura
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/3454 , G11C2211/5621
摘要： A nonvolatile semiconductor memory device includes a memory cell array and a control circuit configured to control reading and programming operations for reading data from and inputting data to the memory cell array, respectively. The control circuit includes first and second units. The first unit is configured to count a number of bits having logic 0 or a number of bits having logic 1, to set a logic where the counted number is greater than n/2 as an initial state to regenerate programming data, and to perform a programming operation based on the regenerated data, when simultaneously programming the programming data of n bits input for a designated address. The second unit is configured to program a recognition bit for recognizing which of the logic 0 and the logic 1 the initial state of the memory cell of the designated address is in, when the programming operation is performed.
摘要翻译：非易失性半导体存储器件包括存储单元阵列和控制电路，该控制电路被配置为分别控制从存储单元阵列读取数据和向存储单元阵列输入数据的读取和编程操作。控制电路包括第一和第二单元。第一单元被配置为对具有逻辑0或具有逻辑1的位数的位数进行计数，以将计数数大于n / 2的逻辑设置为初始状态，以重新生成编程数据，并且执行当对指定地址进行n位输入的编程数据同时编程时，基于再生数据进行编程操作。第二单元被配置为在执行编程操作时对识别位进行编程以识别逻辑0和逻辑1中的哪一个指定地址的存储单元的初始状态。

2. 发明申请

US20100135081A1 NONVOLATILE MEMORY DEVICE 失效
标题翻译：非易失性存储器件
公开(公告)号：US20100135081A1
公开(公告)日：2010-06-03
申请号：US12625723
申请日：2009-11-25
申请人： Shoichi Kawamura , Masahito Takehara
发明人： Shoichi Kawamura , Masahito Takehara
IPC分类号： G11C7/00 , G11C16/10 , G11C16/26
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/3454 , G11C2211/5621
摘要： A nonvolatile semiconductor memory device includes a memory cell array and a control circuit configured to control reading and programming operations for reading data from and inputting data to the memory cell array, respectively. The control circuit includes first and second units. The first unit is configured to count a number of bits having logic 0 or a number of bits having logic 1, to set a logic where the counted number is greater than n/2 as an initial state to regenerate programming data, and to perform a programming operation based on the regenerated data, when simultaneously programming the programming data of n bits input for a designated address. The second unit is configured to program a recognition bit for recognizing which of the logic 0 and the logic 1 the initial state of the memory cell of the designated address is in, when the programming operation is performed.
摘要翻译：非易失性半导体存储器件包括存储单元阵列和控制电路，该控制电路被配置为分别控制从存储单元阵列读取数据和向存储单元阵列输入数据的读取和编程操作。控制电路包括第一和第二单元。第一单元被配置为对具有逻辑0或具有逻辑1的位数的位数进行计数，以将计数数大于n / 2的逻辑设置为初始状态，以重新生成编程数据，并且执行当对指定地址进行n位输入的编程数据同时编程时，基于再生数据进行编程操作。第二单元被配置为在执行编程操作时对识别位进行编程以识别逻辑0和逻辑1中的哪一个指定地址的存储单元的初始状态。

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