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    • 1. 发明授权
    • C-MOS thin film transistor device manufacturing method
    • C-MOS薄膜晶体管器件的制造方法
    • US5316960A
    • 1994-05-31
    • US78409
    • 1993-06-17
    • Hirofumi WatanabeNoriyuki Terao
    • Hirofumi WatanabeNoriyuki Terao
    • H01L21/84H01L21/265
    • H01L21/84Y10S148/137Y10S148/15
    • A method for manufacturing a C-MOS thin film transistor device has the steps of implanting the n-type impurity only in the upper layer portion of the source-drain section of the n-channel transistor by controlling implantation energy of the n-type impurity; implanting the p-type impurity in the source-drain section and the gate electrode of the p-channel transistor, and the source-drain section and the gate electrode of the n-channel transistor by controlling implantation energy of the p-type impurity; and activating the implanted n-type and p-type impurities in the source-drain section of the n-channel transistor, and activating the implanted p-type impurity in the source-drain section and the gate electrode of the p-channel transistor and gate electrode of the n-channel transistor. The n-type and the p-type may be respectively changed to the p-type and the n-type in the above construction.
    • 用于制造C-MOS薄膜晶体管器件的方法具有以下步骤:通过控制n型杂质的注入能量将n型杂质仅植入在n沟道晶体管的源极 - 漏极部分的上层部分中 ; 通过控制p型杂质的注入能量,将p型杂质注入到p沟道晶体管的源极 - 漏极部分和栅极电极以及n沟道晶体管的源极 - 漏极部分和栅极电极中; 以及激活n沟道晶体管的源极 - 漏极部分中注入的n型和p型杂质,以及激活p沟道晶体管的源 - 漏部分和栅电极中注入的p型杂质,以及 n沟道晶体管的栅电极。 在上述结构中,n型和p型可以分别变为p型和n型。
    • 8. 发明申请
    • SEMICONDUCTOR DEVICE AND IMAGING APPARATUS
    • 半导体器件和成像装置
    • US20130234277A1
    • 2013-09-12
    • US13793445
    • 2013-03-11
    • Takaaki NegoroHirofumi WatanabeYutaka HayashiToshitaka OtaYasushi Nagamune
    • Takaaki NegoroHirofumi WatanabeYutaka HayashiToshitaka OtaYasushi Nagamune
    • H01L27/146H01L29/73
    • H01L27/14681H01L27/14683H01L29/73H01L29/739H01L31/1105
    • The invention relates to a semiconductor device having a vertical transistor bipolar structure of emitter, base, and collector formed in this order from a semiconductor substrate surface in a depth direction. The semiconductor device includes an electrode embedded from the semiconductor substrate surface into the inside and insulated by an oxide film. In the surface of the substrate, a first-conductivity-type first semiconductor region, a second-conductivity-type second semiconductor region, and a first-conductivity-type third semiconductor region are arranged, from the surface side, inside a semiconductor device region surrounded by the electrode and along the electrode with the oxide film interposed therebetween, the second semiconductor region located below the first semiconductor region, the third semiconductor region located below the second semiconductor region. The electrode is insulated from the first to third semiconductor regions, and current gain is variable through application of voltage to the electrode.
    • 本发明涉及一种半导体器件,其具有从半导体衬底表面沿深度方向依次形成的发射极,基极和集电极的垂直晶体管双极结构。 半导体器件包括从半导体衬底表面嵌入内部并由氧化物膜绝缘的电极。 在基板的表面中,从第一导电型第一半导体区域,第二导电型第二半导体区域和第一导电型第三半导体区域的表面侧配置在半导体器件区域 被电极围绕并且沿着电极,氧化膜插入其间,位于第一半导体区域下方的第二半导体区域,位于第二半导体区域下方的第三半导体区域。 电极与第一至第三半导体区域绝缘​​,电流增益可通过向电极施加电压而变化。
    • 10. 发明授权
    • Amplifier
    • 放大器
    • US08174319B2
    • 2012-05-08
    • US13004336
    • 2011-01-11
    • Hideyuki AotaHirofumi Watanabe
    • Hideyuki AotaHirofumi Watanabe
    • H03F3/16
    • H03F3/345G05F1/56
    • An amplifier includes a first amplifier comprising an N-type field-effect transistor receiving a reference voltage at a gate, a P-type field-effect transistor connected between a drain of the N-type field-effect transistor and a power supply voltage line, and a constant current source connected between a source of the N-type field-effect transistor and a ground, to output a voltage from a connection of the drain of the N-type and P-type field-effect transistors; a second amplifier comprising a resistance and P-type field-effect transistors connected in series between the power supply voltage line and the ground to receive the voltage output from the first amplifier at their gate, and outputting a voltage from a connection of the P-type field-effect transistor and the resistance; and a switch between an output of the first amplifier and the power supply voltage line and comprising an N-type field-effect transistor receiving a reference voltage at a gate.
    • 放大器包括:第一放大器,包括在栅极接收参考电压的N型场效应晶体管,连接在N型场效应晶体管的漏极和电源电压线之间的P型场效应晶体管 以及连接在N型场效应晶体管的源极和地之间的恒流源,以从N型和P型场效应晶体管的漏极的连接输出电压; 第二放大器,包括串联连接在电源电压线和地之间的电阻和P型场效应晶体管,以接收在其栅极处从第一放大器输出的电压,并输出来自P- 型场效应晶体管和电阻; 以及第一放大器的输出和电源电压线之间的开关,并且包括在栅极处接收参考电压的N型场效应晶体管。