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1. 发明授权

US06924239B2 Method for removal of hydrocarbon contamination on gate oxide prior to non-thermal nitridation using “spike” radical oxidation 有权
标题翻译：使用“尖峰”自由基氧化在非热氮化之前去除栅极氧化物上的烃污染的方法
公开(公告)号：US06924239B2
公开(公告)日：2005-08-02
申请号：US10684897
申请日：2003-10-14
申请人： Hiroaki Niimi , Husam N. Alshareef , Ajith Varghese
发明人： Hiroaki Niimi , Husam N. Alshareef , Ajith Varghese
IPC分类号： H01L21/20 , H01L21/28 , H01L21/302 , H01L21/306 , H01L21/31 , H01L21/314 , H01L21/316 , H01L21/36
CPC分类号： H01L21/28202 , H01L21/02046 , H01L21/28185 , H01L21/3144 , H01L21/31662
摘要： The present invention is generally directed towards a method for removing hydrocarbon contamination from a substrate prior to a nitridation step, therein providing for a generally uniform nitridation of the substrate. The method comprises placing the substrate in a process chamber and flowing an oxygen-source gas into the process chamber. A first plasma is formed in the process chamber for a first predetermined amount of time, wherein the hydrocarbons combine with one or more species of the oxygen-source gas in radical form to form product gases. The gases are removed from the process chamber and a nitrogen-source gas is flowed into the process chamber. A second plasma is then formed in the process chamber for a second predetermined amount of time, therein nitriding the substrate in a significantly uniform manner.
摘要翻译：本发明一般涉及一种在氮化步骤之前从基底去除烃类污染物的方法，其中提供基底的大致均匀的氮化。该方法包括将基板放置在处理室中并将氧源气体流入处理室。第一等离子体在处理室中形成第一预定量的时间，其中烃与一种或多种以自由基形式的氧源气体组合以形成产物气体。气体从处理室中移出，氮源气体流入处理室。然后在处理室中形成第二等离子体第二预定量的时间，其中以显着均匀的方式氮化基板。

2. 发明授权

US07682988B2 Thermal treatment of nitrided oxide to improve negative bias thermal instability 有权
标题翻译：氮化氧化物的热处理以改善负偏压热不稳定性
公开(公告)号：US07682988B2
公开(公告)日：2010-03-23
申请号：US10930230
申请日：2004-08-31
申请人： Husam N. Alshareef , Rajesh Khamankar , Ajith Varghese , Cathy A. Chancellor , Anand Krishnan , Malcolm J. Bevan
发明人： Husam N. Alshareef , Rajesh Khamankar , Ajith Varghese , Cathy A. Chancellor , Anand Krishnan , Malcolm J. Bevan
IPC分类号： H01L21/31 , H01L21/469 , H01L21/8234
CPC分类号： H01L21/02326 , H01L21/0214 , H01L21/02337 , H01L21/265 , H01L21/28202 , H01L21/3144 , H01L21/823857 , H01L29/518 , H01L29/7833
摘要： A method of reducing threshold voltage shift of a MOSFET transistor resulting after temperature and voltage stress, and an integrated circuit device fabricated according to the method. The method includes the steps of forming a nitrided dielectric layer on a semiconductor substrate, and subjecting the nitrided dielectric layer to an anneal at low pressure.
摘要翻译：一种降低在温度和电压应力之后导致的MOSFET晶体管的阈值电压偏移的方法，以及根据该方法制造的集成电路器件。该方法包括以下步骤：在半导体衬底上形成氮化介电层，并将氮化介电层在低压下进行退火。

3. 发明授权

US07514308B2 CMOS device having different amounts of nitrogen in the NMOS gate dielectric layers and PMOS gate dielectric layers 有权
标题翻译： CMOS器件在NMOS栅极电介质层和PMOS栅极电介质层中具有不同量的氮
公开(公告)号：US07514308B2
公开(公告)日：2009-04-07
申请号：US11745930
申请日：2007-05-08
申请人： Ajith Varghese , Husam N. Alshareef , Rajesh Khamankar
发明人： Ajith Varghese , Husam N. Alshareef , Rajesh Khamankar
IPC分类号： H01L21/336
CPC分类号： H01L21/28202 , H01L21/823857 , H01L29/513 , H01L29/518
摘要： The present invention provides a complementary metal oxide semiconductor (CMOS) device, a method of manufacture therefor, and an integrated circuit including the same. The CMOS device (100), in an exemplary embodiment of the present invention, includes a p-channel metal oxide semiconductor (PMOS) device (120) having a first gate dielectric layer (133) and a first gate electrode layer (138) located over a substrate (110), wherein the first gate dielectric layer (133) has an amount of nitrogen located therein. In addition to the PMOS device (120), the CMOS device further includes an n-channel metal oxide semiconductor (NMOS) device (160) having a second gate dielectric layer (173) and a second gate electrode layer (178) located over the substrate (110), wherein the second gate dielectric layer (173) has a different amount of nitrogen located therein. Accordingly, the present invention allows for the individual tuning of the threshold voltages for the PMOS device (120) and the NMOS device (160).
摘要翻译：本发明提供了一种互补金属氧化物半导体（CMOS）器件及其制造方法，以及包括该互补金属氧化物半导体器件的集成电路。在本发明的示例性实施例中，CMOS器件（100）包括具有第一栅极介电层（133）和位于第一栅极电极层（138）的p沟道金属氧化物半导体（PMOS）器件（120）在衬底（110）上，其中第一栅极电介质层（133）具有位于其中的一定量的氮。除了PMOS器件（120）之外，CMOS器件还包括具有第二栅极电介质层（173）和第二栅电极层（178）的n沟道金属氧化物半导体（NMOS）器件（160）衬底（110），其中所述第二栅极电介质层（173）具有位于其中的不同量的氮。因此，本发明允许对PMOS器件（120）和NMOS器件（160）的阈值电压进行单独调谐。

4. 发明申请

US20080268627A1 TRANSISTOR PERFORMANCE USING A TWO-STEP DAMAGE ANNEAL 有权
公开(公告)号：US20080268627A1
公开(公告)日：2008-10-30
申请号：US11742229
申请日：2007-04-30
申请人： Hiroaki Niimi , Jarvis Benjamin Jacobs , Ajith Varghese
发明人： Hiroaki Niimi , Jarvis Benjamin Jacobs , Ajith Varghese
IPC分类号： H01L21/425
CPC分类号： H01L21/324 , H01L21/265 , H01L21/26513 , H01L21/823412 , H01L21/823462 , H01L29/105 , H01L29/66477
摘要： A two-step thermal treatment method consists of performing ion implantation in a silicon substrate of the semiconductor device. A first thermal treatment procedure is performed on the semiconductor device. A second thermal treatment procedure is consecutively performed on the semiconductor device to reduce damage produced by the ion implantation.

5. 发明申请

US20080268603A1 TRANSISTOR PERFORMANCE USING A TWO-STEP DAMAGE ANNEAL 审中-公开
标题翻译：使用两步损伤天线的晶体管性能
公开(公告)号：US20080268603A1
公开(公告)日：2008-10-30
申请号：US11742186
申请日：2007-04-30
申请人： Hiroaki NIIMI , Jarvis Benjamin Jacobs , Ajith Varghese
发明人： Hiroaki NIIMI , Jarvis Benjamin Jacobs , Ajith Varghese
IPC分类号： H01L21/324 , H01L21/265
CPC分类号： H01L21/26513 , H01L21/324 , H01L27/1052
摘要： A two-step thermal treatment method consists of performing ion implantation in a silicon substrate of the semiconductor device. A first thermal treatment procedure is performed on the semiconductor device. A second thermal treatment procedure is consecutively performed on the semiconductor device to reduce damage produced by the ion implantation.
摘要翻译：两步热处理方法包括在半导体器件的硅衬底中进行离子注入。在半导体器件上执行第一热处理程序。在半导体器件上连续执行第二热处理程序以减少由离子注入产生的损伤。

6. 发明授权

US08828855B2 Transistor performance using a two-step damage anneal 有权
标题翻译：晶体管性能使用两步损伤退火
公开(公告)号：US08828855B2
公开(公告)日：2014-09-09
申请号：US11742229
申请日：2007-04-30
申请人： Hiroaki Niimi , Jarvis Benjamin Jacobs , Ajith Varghese
发明人： Hiroaki Niimi , Jarvis Benjamin Jacobs , Ajith Varghese
IPC分类号： H01L21/425 , H01L21/265 , H01L21/8234 , H01L21/324 , H01L29/10
CPC分类号： H01L21/324 , H01L21/265 , H01L21/26513 , H01L21/823412 , H01L21/823462 , H01L29/105 , H01L29/66477
摘要： A two-step thermal treatment method consists of performing ion implantation in a silicon substrate of the semiconductor device. A first thermal treatment procedure is performed on the semiconductor device. A second thermal treatment procedure is consecutively performed on the semiconductor device to reduce damage produced by the ion implantation.
摘要翻译：两步热处理方法包括在半导体器件的硅衬底中进行离子注入。在半导体器件上执行第一热处理程序。在半导体器件上连续执行第二热处理程序以减少由离子注入产生的损伤。

7. 发明申请

US20050079723A1 METHOD FOR REMOVAL OF HYDROCARBON CONTAMINATION ON GATE OXIDE PRIOR TO NON-THERMAL NITRIDATION USING "SPIKE" RADICAL OXIDATION 有权
标题翻译：使用“SPIKE”辐射氧化除去非极性氮化物之前的氮氧化物上的碳氢化合物的方法
公开(公告)号：US20050079723A1
公开(公告)日：2005-04-14
申请号：US10684897
申请日：2003-10-14
申请人： Hiroaki Niimi , Husam Alshareef , Ajith Varghese
发明人： Hiroaki Niimi , Husam Alshareef , Ajith Varghese
IPC分类号： H01L21/20 , H01L21/28 , H01L21/302 , H01L21/306 , H01L21/31 , H01L21/314 , H01L21/316 , H01L21/36
CPC分类号： H01L21/28202 , H01L21/02046 , H01L21/28185 , H01L21/3144 , H01L21/31662
摘要： The present invention is generally directed towards a method for removing hydrocarbon contamination from a substrate prior to a nitridation step, therein providing for a generally uniform nitridation of the substrate. The method comprises placing the substrate in a process chamber and flowing an oxygen-source gas into the process chamber. A first plasma is formed in the process chamber for a first predetermined amount of time, wherein the hydrocarbons combine with one or more species of the oxygen-source gas in radical form to form product gases. The gases are removed from the process chamber and a nitrogen-source gas is flowed into the process chamber. A second plasma is then formed in the process chamber for a second predetermined amount of time, therein nitriding the substrate in a significantly uniform manner.
摘要翻译：本发明一般涉及一种在氮化步骤之前从基底去除烃类污染物的方法，其中提供基底的大致均匀的氮化。该方法包括将基板放置在处理室中并将氧源气体流入处理室。第一等离子体在处理室中形成第一预定量的时间，其中烃与一种或多种以自由基形式的氧源气体组合以形成产物气体。气体从处理室中移出，氮源气体流入处理室。然后在处理室中形成第二等离子体第二预定量的时间，其中以显着均匀的方式氮化基板。

8. 发明授权

US08119470B2 Mitigation of gate to contact capacitance in CMOS flow 有权
标题翻译：栅极接触电容在CMOS流中的缓解
公开(公告)号：US08119470B2
公开(公告)日：2012-02-21
申请号：US11726253
申请日：2007-03-21
申请人： Shashank Sureshchandra Ekbote , Borna Obradovic , Lindsey Hall , Craig Huffman , Ajith Varghese
发明人： Shashank Sureshchandra Ekbote , Borna Obradovic , Lindsey Hall , Craig Huffman , Ajith Varghese
IPC分类号： H01L21/338 , H01L21/336 , H01L21/4763
CPC分类号： H01L29/7833 , H01L21/76804 , H01L21/76897 , H01L29/6656 , H01L29/6659 , Y02P80/30
摘要： Sidewall spacers that are primarily oxide, instead of nitride, are formed adjacent to a gate stack of a CMOS transistor. Individual sidewall spacers are situated between a conductive gate electrode of the gate stack and a conductive contact of the transistor. As such, a capacitance can develop between the gate electrode and the contact, depending on the dielectric constant of the interposed sidewall spacer. Accordingly, forming sidewall spacers out of oxide, which has a lower dielectric constant than nitride, mitigates capacitance that can otherwise develop between these features. Such capacitance is undesirable, at least, because it can inhibit transistor switching speeds. Accordingly, fashioning sidewall spacers as described herein can mitigate yield loss by reducing the number of devices that have unsatisfactory switching speeds and/or other undesirable performance characteristics.
摘要翻译：主要是氧化物而不是氮化物的侧壁间隔物邻近CMOS晶体管的栅极叠层形成。单独的侧壁间隔物位于栅极堆叠的导电栅电极和晶体管的导电接触之间。因此，取决于插入的侧壁间隔物的介电常数，可以在栅电极和接触之间产生电容。因此，从具有比氮化物更低的介电常数的氧化物形成侧壁间隔物减轻了另外可能在这些特征之间产生的电容。这种电容至少是不利的，因为它可以抑制晶体管的切换速度。因此，如本文所述的形成侧壁间隔件可以通过减少具有不令人满意的切换速度和/或其它不期望的性能特征的设备的数量来减轻产量损失。

9. 发明授权

US07396728B2 Methods of improving drive currents by employing strain inducing STI liners 有权
标题翻译：应用感应STI衬垫改善驱动电流的方法
公开(公告)号：US07396728B2
公开(公告)日：2008-07-08
申请号：US11170501
申请日：2005-06-29
申请人： Ajith Varghese , Narendra Singh Mehta , Jonathan McAulay Holt
发明人： Ajith Varghese , Narendra Singh Mehta , Jonathan McAulay Holt
IPC分类号： H01L21/336 , H01L21/76
CPC分类号： H01L21/823807 , H01L21/76224 , H01L21/823878
摘要： A method forms a semiconductor device comprising isolation structures that selectively induce strain into active regions of NMOS and PMOS devices. Form a hard mask layer over a semiconductor body. A resist layer is formed on the hard mask layer that exposes and defines isolation regions. The hard mask layer is patterned and trench regions are formed using the hard mask layer as a mask. An oxide trench liner that induces compressive strain into active regions of the PMOS region is formed within trench regions of the PMOS region. A nitride trench liner that induces tensile strain into active regions of the NMOS region is formed within the NMOS trench regions.
摘要翻译：一种方法形成包括选择性地将应变引入到NMOS和PMOS器件的有源区的隔离结构的半导体器件。在半导体体上形成硬掩模层。在暴露并限定隔离区域的硬掩模层上形成抗蚀剂层。图案化硬掩模层，并使用硬掩模层作为掩模形成沟槽区域。在PMOS区域的沟槽区域内形成有对PMOS区域的有源区域产生压缩应变的氧化物沟槽衬垫。在NMOS沟槽区域内形成氮化物沟槽衬垫，其将拉伸应变引入NMOS区域的有源区。

10. 发明申请

US20080006886A1 Semiconductor Device Manufactured Using a Non-Contact Implant Metrology 有权
标题翻译：使用非接触式种植体计量制造的半导体器件
公开(公告)号：US20080006886A1
公开(公告)日：2008-01-10
申请号：US11559271
申请日：2006-11-13
申请人： Narendra Mehta , Ajith Varghese , Benjamin Moser
发明人： Narendra Mehta , Ajith Varghese , Benjamin Moser
IPC分类号： H01L21/425 , H01L29/78
CPC分类号： H01L21/26513 , H01L21/31155 , H01L22/14
摘要： A method of manufacturing a semiconductor device including calibrating an ion implant process. The calibration includes forming a dielectric layer over a calibration substrate. A dopant is implanted into the dielectric layer. Charge is deposited on a surface of the dielectric layer, and voltage on the surface is measured. An electrical characteristic of the dielectric layer is determined, and a doping level of the dielectric layer is determined from the electrical characteristic. The electrical characteristic is associated with an operating set-point of the ion implant process. The calibrated ion implant process is used to implant the dopant into a semiconductor substrate.
摘要翻译：一种制造半导体器件的方法，包括校准离子注入工艺。校准包括在校准基板上形成电介质层。将掺杂剂注入电介质层。电荷沉积在电介质层的表面上，并且测量表面上的电压。确定电介质层的电特性，根据电气特性确定电介质层的掺杂程度。电特性与离子注入工艺的操作设定点相关联。校准离子注入工艺用于将掺杂剂注入到半导体衬底中。

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