专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07868336B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07868336B2
公开(公告)日：2011-01-11
申请号：US12264539
申请日：2008-11-04
申请人： Hiroaki Fujimoto , Yoshihiro Tomita
发明人： Hiroaki Fujimoto , Yoshihiro Tomita
IPC分类号： H01L33/00 , H01L23/02 , H01L21/00
CPC分类号： H01L27/14618 , H01L24/94 , H01L27/14636 , H01L27/14683 , H01L2224/73204
摘要： According to the present invention, protrusions 4 are formed on electrodes 3 of semiconductor elements 6, and an optical member 7 is secured on the semiconductor element 6 with an adhesive 8 so as to be pressed onto the protrusions 4.
摘要翻译：根据本发明，在半导体元件6的电极3上形成突起4，用粘合剂8将光学部件7固定在半导体元件6上，从而被压在突起4上。

2. 发明申请

US20090134505A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20090134505A1
公开(公告)日：2009-05-28
申请号：US12264539
申请日：2008-11-04
申请人： Hiroaki Fujimoto , Yoshihiro Tomita
发明人： Hiroaki Fujimoto , Yoshihiro Tomita
IPC分类号： H01L23/02 , H01L21/50
CPC分类号： H01L27/14618 , H01L24/94 , H01L27/14636 , H01L27/14683 , H01L2224/73204
摘要： According to the present invention, protrusions 4 are formed on electrodes 3 of semiconductor elements 6, and an optical member 7 is secured on the semiconductor element 6 with an adhesive 8 so as to be pressed onto the protrusions 4.
摘要翻译：根据本发明，在半导体元件6的电极3上形成突起4，用粘合剂8将光学部件7固定在半导体元件6上，从而被压在突起4上。

3. 发明申请

US20110147905A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110147905A1
公开(公告)日：2011-06-23
申请号：US13039937
申请日：2011-03-03
申请人： Masaki Utsumi , Hikari Sano , Hiroaki Fujimoto , Yoshihiro Tomita
发明人： Masaki Utsumi , Hikari Sano , Hiroaki Fujimoto , Yoshihiro Tomita
IPC分类号： H01L23/06 , H01L21/78
CPC分类号： H01L33/62 , H01L21/76898 , H01L23/481 , H01L27/14618 , H01L2224/0554 , H01L2224/05573 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05666 , H01L2224/13025 , H01L2224/16225 , H01L2924/00014 , H01L2924/01055 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： In a semiconductor element, upper through-hole conductor portions and lower through-hole conductor portions are formed such that pore size A of the joint surface of the upper through-hole conductor portion and the lower through-hole conductor portion is smaller than pore size B of the upper through-hole conductor portion on the major surface of the semiconductor element and pore size C of the lower through-hole conductor portion on the other surface of the semiconductor element. Further, electrode portions are formed respectively on the top surfaces of the upper through-hole conductor portions and protrusions 4 are formed respectively on the top surfaces of the electrode portions. Moreover, an optical member pressed in contact with the protrusions is fixed on the semiconductor element with an adhesive.
摘要翻译：在半导体元件中，形成上通孔导体部和下通孔导体部，使得上通孔导体部和下通孔导体部的接合面的孔径A小于孔径 B，半导体元件的主表面上的上通孔导体部分的孔径C和半导体元件另一表面上的下通孔导体部分的孔径C. 此外，电极部分分别形成在上通孔导体部分的顶表面上，突起4分别形成在电极部分的顶表面上。此外，用粘合剂固定在半导体元件上与突起接触的光学部件。

4. 发明授权

US08216085B2 Golf club 有权
标题翻译：高尔夫俱乐部
公开(公告)号：US08216085B2
公开(公告)日：2012-07-10
申请号：US12393764
申请日：2009-02-26
申请人： Hiroaki Fujimoto
发明人： Hiroaki Fujimoto
IPC分类号： A63B53/00
CPC分类号： A63B53/00 , A63B53/0466 , A63B60/24 , A63B60/42 , A63B2053/0408 , A63B2209/00
摘要： A golf club 2 includes a shaft 6, a tip member provided at a tip part of the shaft 6, and a rear end member attached to a rear end part of the shaft 6. The tip member includes a head 4. The rear end member includes a grip 8 and a weight member 20. The golf club has a club length of 1143 mm or more. A value of [W2/W1] is no less than 0.23 and no more than 0.32 when a weight of the tip member is W1 (g) and a weight of the rear end member is W2 (g). The weight member 20 is provided on a rear side relative to a tip position of the grip. The weight member 20 has a specific gravity larger than that of the shaft 6. The golf club 2 is a wood type golf club. Examples of materials for the weight member 20 include brass, a tungsten nickel alloy, an aluminum alloy, a tungsten alloy, a stainless alloy, stainless steel, and the like.
摘要翻译：高尔夫球杆2包括轴6，设置在轴6的尖端部分的末端构件和安装在轴6的后端部的后端构件。顶端构件包括头部4.后端构件包括把手8和配重构件20.高尔夫球杆具有1143mm或更大的球杆长度。当顶端构件的重量为W1（g），后端构件的重量为W2（g）时，[W2 / W1]的值不小于0.23且不大于0.32。配重构件20设置在相对于把手的尖端位置的后侧。重量构件20的比重大于轴6的比重。高尔夫球杆2是木质高尔夫球杆。用于配重构件20的材料的实例包括黄铜，钨镍合金，铝合金，钨合金，不锈钢合金，不锈钢等。

5. 发明申请

US20090111605A1 Golf putter 有权
标题翻译：高尔夫推杆
公开(公告)号：US20090111605A1
公开(公告)日：2009-04-30
申请号：US12230610
申请日：2008-09-02
申请人： Hiroaki Fujimoto
发明人： Hiroaki Fujimoto
IPC分类号： A63B53/04
CPC分类号： A63B53/0487 , A63B2053/0408 , A63B2053/0416 , A63B2053/042 , A63B2053/0433 , A63B2053/0441 , A63B2053/0491
摘要： A real loft angle of a putter (2) is one to four degrees. In a reference section (D1), an intersection point of a line which passes through a center of gravity (g1) of a head and is perpendicular to a horizontal plane (H1) and a sole surface (18) is represented by (T1), a line passing through the point (T1) and a leading edge point (Le) is represented by (S1), a point which is present on the sole surface (18) and is provided apart from the line (S1) toward a lowermost side is represented by (T2), a line which passes through the point (T2) and is parallel with the line (S1) is represented by (S2), a distance between the point (T2) and the line (S1) is represented by (K1), a line passing through the point (T2) and the point (Le) is represented by (S3), a distance in the front-rear direction between the point (T2) and the point (Le) is represented by (L), and a distance in the front-rear direction between the point (T1) and the point (Le) is represented by (M). An angle (θ1) formed by the line (S3) and the horizontal plane (H1) is equal to or greater than two degrees and is equal to or smaller than ten degrees. (K1/M) is greater than zero and is equal to or smaller than 0.10. (L/P) is equal to or greater than 0.10 and is equal to or smaller than 0.50. A lower portion (22) positioned below the line (S1) is present between the point (T1) and the point (Le).
摘要翻译：推杆（2）的真实阁楼角度为1至4度。在参考部分（D1）中，通过头部的重心（g1）并且垂直于水平面（H1）和鞋底表面（18）的直线的交点由（T1）表示，通过点（T1）和前缘点（Le）的线由（S1）表示，该点存在于鞋底表面（18）上并且与线（S1）分开设置朝向最下面（T2）表示，通过点（T2）并且与线（S1）平行的线由（S2）表示，点（T2）和线（S1）之间的距离被表示通过（K1），通过点（T2）和点（Le）的线由（S3）表示，点（T2）和点（Le）之间的前后方向上的距离由（L），点（T1）和点（Le）之间的前后方向的距离由（M）表示。由线（S3）和水平面（H1）形成的角度（θ1）等于或大于2度并且等于或小于十度。（K1 / M）大于零并且等于或小于0.10。（L / P）等于或大于0.10并且等于或小于0.50。在点（T1）和点（Le）之间存在位于线（S1）下方的下部（22）。

6. 发明申请

US20080083964A1 Semiconductor image sensor die and production method thereof, semiconductor image sensor module, image sensor device, optical device element, and optical device module 审中-公开
标题翻译：半导体图像传感器芯片及其制造方法，半导体图像传感器模块，图像传感器装置，光学元件元件和光学器件模块
公开(公告)号：US20080083964A1
公开(公告)日：2008-04-10
申请号：US11889675
申请日：2007-08-15
申请人： Hiroaki Fujimoto , Masanori Minamio , Toshiyuki Fukuda
发明人： Hiroaki Fujimoto , Masanori Minamio , Toshiyuki Fukuda
IPC分类号： H01L31/0232 , H01L21/71
CPC分类号： H01L27/14618 , H01L27/14625 , H01L31/0203 , H01L31/0232 , H01L2224/45124 , H01L2224/45144 , H01L2224/48465 , H01L2924/10252 , H01L2924/10253 , H01L2924/10272 , H01L2924/10329 , H01L2924/1033 , H01L2924/10335 , H01L2924/3025 , H01L2224/48091 , H01L2924/00014 , H01L2924/00
摘要： A semiconductor image sensor die includes a substrate, an imaging area, a surrounding circuit area, a plurality of electrode portions, a translucent member, a transparent adhesive, and a bump. The imaging area, the surrounding circuit area, and the electrode portion are provided on an upper surface of the substrate. The surrounding circuit area is provided outside the imaging area. The electrode portion is provided outside the surrounding circuit area. The translucent member is adhered via the transparent adhesive to the imaging area, covering the imaging area. The bump is provided on a portion of the electrode portions. The surface of the bump includes an upper surface which is located higher than an upper surface of the transparent adhesive.
摘要翻译：半导体图像传感器芯片包括基板，成像区域，周围电路区域，多个电极部分，半透明构件，透明粘合剂和凸块。成像区域，周围电路区域和电极部分设置在基板的上表面上。周围的电路区域设置在成像区域的外部。电极部设置在周围电路区域的外侧。半透明构件通过透明粘合剂粘附到成像区域，覆盖成像区域。凸块设置在电极部分的一部分上。凸起的表面包括位于比透明粘合剂的上表面高的上表面。

7. 发明授权

US07125751B2 Semiconductor device and method for the fabrication thereof grinding frame portion such that plural electrode constituent portions 有权
标题翻译：半导体装置及其制造方法用于研磨框架部分，使得多个电极构成部分
公开(公告)号：US07125751B2
公开(公告)日：2006-10-24
申请号：US11042163
申请日：2005-01-26
申请人： Hiroaki Fujimoto , Tsuyoshi Hamatani , Toru Nomura
发明人： Hiroaki Fujimoto , Tsuyoshi Hamatani , Toru Nomura
IPC分类号： H01L21/44 , H01L21/48 , H01L21/50 , H01L21/302 , H01L21/461
CPC分类号： H01L23/49548 , H01L21/4832 , H01L23/3107 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/97 , H01L25/105 , H01L2221/68377 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/49171 , H01L2224/73265 , H01L2224/85001 , H01L2224/92247 , H01L2224/97 , H01L2225/1029 , H01L2225/1041 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/07802 , H01L2924/12042 , H01L2924/181 , H01L2924/18165 , H01L2924/351 , H01L2924/00014 , H01L2224/85 , H01L2924/00 , H01L2924/00012
摘要： Disclosed is a semiconductor device which comprises a semiconductor element having a plurality of electrodes, a plurality of external electrodes disposed around the periphery of the semiconductor element, a fine wire electrically connected between at least one of surfaces of each of the plural external electrodes and at least one of the plural electrodes of the semiconductor element, and an encapsulating resin which encapsulates the semiconductor element, the plural external electrodes, and the fine wires and whose external shape is a rectangular parallelepiped, wherein a bottom surface of the semiconductor element and a bottom surface of each of the plural external electrode are exposed from a bottom surface of the encapsulating resin and a top surface of the semiconductor element and a top surface of each of the plural external electrode are located substantially coplanar with each other.
摘要翻译：公开了一种半导体器件，其包括具有多个电极的半导体元件，设置在半导体元件周围的多个外部电极，电连接在多个外部电极中的至少一个表面之间的细线，半导体元件的多个电极中的至少一个以及密封半导体元件，多个外部电极和细线的外形为长方体的封装树脂，其中半导体元件的底面和底部多个外部电极的表面从封装树脂的底面露出，半导体元件的上表面和多个外部电极的上表面大致共面。

8. 发明授权

US07087455B2 Semiconductor device and manufacturing method for the same 有权
标题翻译：半导体器件及其制造方法相同
公开(公告)号：US07087455B2
公开(公告)日：2006-08-08
申请号：US10636595
申请日：2003-08-08
申请人： Toshiyuki Fukuda , Hiroaki Fujimoto , Mutsuo Tsuji , Takashi Yui , Yoshiaki Takeoka
发明人： Toshiyuki Fukuda , Hiroaki Fujimoto , Mutsuo Tsuji , Takashi Yui , Yoshiaki Takeoka
IPC分类号： H01L21/44
CPC分类号： H01L21/561 , H01L21/563 , H01L23/3121 , H01L24/11 , H01L24/12 , H01L24/13 , H01L24/16 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/83 , H01L24/97 , H01L25/0657 , H01L29/0657 , H01L2224/0401 , H01L2224/05553 , H01L2224/05554 , H01L2224/05624 , H01L2224/11 , H01L2224/1134 , H01L2224/13 , H01L2224/13099 , H01L2224/13144 , H01L2224/16225 , H01L2224/2919 , H01L2224/32145 , H01L2224/32225 , H01L2224/45015 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/48471 , H01L2224/48624 , H01L2224/4943 , H01L2224/73203 , H01L2224/73204 , H01L2224/73265 , H01L2224/78301 , H01L2224/83191 , H01L2224/83855 , H01L2224/85181 , H01L2224/85186 , H01L2224/97 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06527 , H01L2225/06555 , H01L2225/06586 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01042 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01204 , H01L2924/0132 , H01L2924/014 , H01L2924/0665 , H01L2924/07802 , H01L2924/10162 , H01L2924/12042 , H01L2924/14 , H01L2924/15787 , H01L2924/181 , H01L2924/19103 , H01L2924/19105 , H01L2924/20751 , H01L2924/20752 , H01L2924/20753 , H01L2924/351 , H01L2224/85 , H01L2224/81 , H01L2224/83 , H01L2924/00 , H01L2924/01046 , H01L2924/00012 , H01L2924/00011 , H01L2924/3512 , H01L2224/92247 , H01L2224/4554
摘要： A semiconductor device and a manufacturing method for the same are provided wherein the reliability of connections of fine metal wires connecting a second semiconductor chip to a wiring board can be improved in the case wherein the second semiconductor chip, which is located above the lower, first semiconductor chip, is significantly larger than the first semiconductor chip in a configuration wherein two semiconductor chips are stacked and mounted on a wiring board. In this semiconductor device the rear surface of the first semiconductor chip and the rear surface of the second semiconductor chip are adhered to each other by means of adhesive and the side of the adhesive is inclined from the edge portions of the first semiconductor chip toward the portions of the second semiconductor chip extending from the side of the first semiconductor chip. Therefore, it becomes possible to prevent the occurrence of microcracks in the second semiconductor chip and to prevent the occurrence of defective fine metal wire connections caused by the impact at the time of electrical connection of the second semiconductor chip to the wiring board.
摘要翻译：提供了一种半导体器件及其制造方法，其中在第二半导体芯片位于下部第一半导体芯片的情况下，可以提高连接第二半导体芯片到布线板的细金属线的连接的可靠性半导体芯片明显大于其中两个半导体芯片堆叠并安装在布线板上的配置中的第一半导体芯片。在该半导体器件中，第一半导体芯片的后表面和第二半导体芯片的后表面通过粘合剂彼此粘合，并且粘合剂的侧面从第一半导体芯片的边缘部朝向部分的第二半导体芯片从第一半导体芯片的侧面延伸。因此，可以防止第二半导体芯片中的微裂纹的发生，并且防止由于第二半导体芯片与布线板的电连接时的冲击而引起的细小金属线连接不良的发生。

9. 发明授权

US06565399B2 Watercraft catalytic exhaust system 失效
公开(公告)号：US06565399B2
公开(公告)日：2003-05-20
申请号：US10094956
申请日：2002-03-08
申请人： Ryoichi Nakase , Shigeyuki Ozawa , Hiroaki Fujimoto
发明人： Ryoichi Nakase , Shigeyuki Ozawa , Hiroaki Fujimoto
IPC分类号： B63H2134
CPC分类号： F01N3/2046 , B63B35/731 , F01N1/08 , F01N3/04 , F01N3/043 , F01N3/046 , F01N3/05 , F01N3/28 , F01N3/2842 , F01N3/2885 , F01N3/2889 , F01N13/004 , F01N13/009 , F01N13/0093 , F01N13/0097 , F01N13/10 , F01N13/12 , F01N13/1811 , F01N13/1816 , F01N13/1844 , F01N13/1855 , F01N2230/04 , F01N2240/02 , F01N2260/022 , F01N2260/024 , F01N2260/04 , F01N2260/10 , F01N2450/30 , F01N2470/12 , F01N2570/12 , F01N2590/02 , F01N2590/022 , F01P3/202 , F01P3/205 , F01P2060/16 , F02B61/045 , Y02T10/26
摘要： A number of embodiments of personal watercraft having catalytic exhaust systems for treating and purifying the exhaust gases. In all of the embodiments, the catalyst is positioned and disposed so as to be protected from water. In addition, arrangements are provided for cooling the catalyst, for circulating ventilating air across it, for isolating it from other components such as the fuel tank, and for permitting its flushing with fresh water after operating in a salt water environment.

10. 发明授权

US06509638B2 Semiconductor device having a plurality of stacked semiconductor chips on a wiring board 有权
标题翻译：半导体器件在布线板上具有多个堆叠的半导体芯片
公开(公告)号：US06509638B2
公开(公告)日：2003-01-21
申请号：US09946363
申请日：2001-09-06
申请人： Hiroaki Fujimoto , Yoshinobu Kunitomo , Takashi Yui
发明人： Hiroaki Fujimoto , Yoshinobu Kunitomo , Takashi Yui
IPC分类号： H01L2302
CPC分类号： H01L25/0657 , H01L25/0652 , H01L2224/05554 , H01L2224/16145 , H01L2224/16225 , H01L2224/32145 , H01L2224/48091 , H01L2224/48225 , H01L2224/48227 , H01L2224/49171 , H01L2224/49175 , H01L2224/73253 , H01L2224/73265 , H01L2225/0651 , H01L2225/06517 , H01L2225/06555 , H01L2225/06562 , H01L2924/00014 , H01L2924/14 , H01L2924/00 , H01L2224/0401
摘要： A semiconductor device includes: a wiring board; a first semiconductor chip, which has a circuitry side and a non-circuitry side that face each other vertically and which is electrically connected to the wiring board via a raised electrode, the circuitry side of the first chip facing the principal surface of the wiring board; and a second semiconductor chip, which has a circuitry side and a non-circuitry side that face each other vertically and which includes an external electrode on the circuitry side thereof. The non-circuitry sides of the first and second semiconductor chips are secured to each other. The external electrode of the second semiconductor chip is connected to the wiring board via a metal fine wire. The external and raised electrodes are so disposed as not to overlap each other as viewed vertically downward from over the principal surface of the wiring board.
摘要翻译：一种半导体器件，包括：布线板; 第一半导体芯片，其具有垂直相对的电路侧和非电路侧，并且经由凸起电极电连接到布线板，第一芯片的电路侧面对布线板的主表面 ; 以及第二半导体芯片，其具有垂直彼此面对并且在其电路侧上包括外部电极的电路侧和非电路侧。第一和第二半导体芯片的非电路侧彼此固定。第二半导体芯片的外部电极通过金属细线连接到布线板。外电极和凸起电极被布置为从布线板的主表面的垂直向下观察不彼此重叠。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式