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1. 发明授权

US06136634A Method of manufacturing semiconductor resistors 失效
标题翻译：制造半导体电阻的方法
公开(公告)号：US06136634A
公开(公告)日：2000-10-24
申请号：US86208
申请日：1998-05-28
申请人： Katsuyuki Kato , Hiroyuki Miwa , Hiroaki Ammo
发明人： Katsuyuki Kato , Hiroyuki Miwa , Hiroaki Ammo
IPC分类号： H01L21/02 , H01L21/84 , H01L27/08 , H01L27/12 , H01L21/8238 , H01L21/8222 , H01L29/00 , H01L29/76
CPC分类号： H01L28/20 , H01L21/84 , H01L27/0802 , H01L27/1203
摘要： A high-resistance polycrystalline Si resistor having a stable resistance value even when micro-sized and a low-resistance polycrystalline Si resistor having a sufficiently low desired resistance value wherein a polycrystalline Si film is formed on an insulation film located on a Si substrate, high-resistance-making ion implantation is applied to the entire surface and medium-resistance-making ion implantation is selectively applied to a medium-resistance-making region of the polycrystalline Si film. Low-resistance-making ion implantation is selectively applied to a low-resistance-making region of the polycrystalline Si film. The product is annealed to grow the polycrystalline Si film by solid-phase growth, the film is patterned to form a high-resistance polycrystalline Si resistor, medium-resistance polycrystalline Si resistor, and low-resistance polycrystalline Si resistor.
摘要翻译：即使在具有足够低的期望电阻值的微小尺寸的情况下也具有稳定的电阻值的高电阻多晶Si电阻器，其中在位于Si衬底上的绝缘膜上形成多晶Si膜，高对整个表面施加电阻制造离子注入，并且将中等电阻制造离子注入选择性地施加到多晶Si膜的中阻制造区域。选择性地将低电阻制造离子注入施加到多晶Si膜的低电阻制造区域。将产物退火以通过固相生长生长多晶Si膜，该膜被图案化以形成高电阻多晶硅电阻器，中等电阻多晶Si电阻器和低电阻多晶Si电阻器。

2. 发明授权

US5872381A Semiconductor device and its manufacturing method 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US5872381A
公开(公告)日：1999-02-16
申请号：US861527
申请日：1997-05-22
申请人： Katsuyuki Kato , Hiroyuki Miwa , Hiroaki Ammo
发明人： Katsuyuki Kato , Hiroyuki Miwa , Hiroaki Ammo
IPC分类号： H01L21/02 , H01L21/84 , H01L27/08 , H01L27/12 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H01L28/20 , H01L21/84 , H01L27/0802 , H01L27/1203
摘要： A high-resistance polycrystalline Si resistor having a stable resistance value even when micro-sized and a low-resistance polycrystalline Si resistor having a sufficiently low desired resistance value wherein a polycrystalline Si film is formed on an insulation film located on a Si substrate, high-resistance-making ion implantation is applied to the entire surface and medium-resistance-making ion implantation is selectively applied to a medium-resistance-making region of the polycrystalline Si film. Low-resistance-making ion implantation is selectively applied to a low-resistance-making region of the polycrystalline Si film. The product is annealed to grow the polycrystalline Si film by solid-phase growth, the film is patterned to form a high-resistance polycrystalline Si resistor, medium-resistance polycrystalline Si resistor, and low-resistance polycrystalline Si resistor.
摘要翻译：即使在具有足够低的期望电阻值的微小尺寸的情况下也具有稳定的电阻值的高电阻多晶Si电阻器，其中在位于Si衬底上的绝缘膜上形成多晶Si膜，高对整个表面施加电阻制造离子注入，并且将中等电阻制造离子注入选择性地施加到多晶Si膜的中阻制造区域。选择性地将低电阻制造离子注入施加到多晶Si膜的低电阻制造区域。将产物退火以通过固相生长生长多晶Si膜，该膜被图案化以形成高电阻多晶硅电阻器，中等电阻多晶Si电阻器和低电阻多晶Si电阻器。

3. 发明授权

US5856228A Manufacturing method for making bipolar device having double polysilicon structure 失效
标题翻译：制造具有双重多晶硅结构的双极器件的制造方法
公开(公告)号：US5856228A
公开(公告)日：1999-01-05
申请号：US757335
申请日：1996-11-27
申请人： Hiroyuki Miwa , Shigeru Kanematsu , Takayuki Gomi , Hiroaki Anmo , Takashi Noguchi , Katsuyuki Kato , Hirokazu Ejiri , Norikazu Ouchi
发明人： Hiroyuki Miwa , Shigeru Kanematsu , Takayuki Gomi , Hiroaki Anmo , Takashi Noguchi , Katsuyuki Kato , Hirokazu Ejiri , Norikazu Ouchi
IPC分类号： H01L21/331 , H01L29/732
CPC分类号： H01L29/7322 , H01L29/66272 , Y10S148/01 , Y10S148/011
摘要： A semiconductor device and a manufacturing method therefor which can simultaneously realize both a reduction in base transit time by a reduction in base width and a reduction in base resistance by a reduction in link base resistance. The semiconductor device is manufactured by the method including the steps of forming a first impurity diffused layer of a first conduction type in a semiconductor substrate; forming a conducting film connected to the first impurity diffused layer; forming a first insulating film on the conducting film; forming a first hole through a laminated film composed of the first insulating film and the conducting film; forming a second impurity diffused layer of the first conduction type in the semiconductor substrate exposed to the first hole; forming a side wall from a second insulating film in the first hole to form a second hole; and forming a third impurity diffused layer of the first conduction type in the semiconductor substrate exposed to the second hole.
摘要翻译：一种半导体器件及其制造方法，其可以通过减小基极宽度同时实现基极通过时间的减少，并且通过降低基极电阻降低基极电阻。半导体器件通过包括以下步骤的方法制造：在半导体衬底中形成第一导电类型的第一杂质扩散层; 形成连接到第一杂质扩散层的导电膜; 在导电膜上形成第一绝缘膜; 通过由第一绝缘膜和导电膜构成的层压膜形成第一孔; 在暴露于第一孔的半导体衬底中形成第一导电类型的第二杂质扩散层; 从所述第一孔中的第二绝缘膜形成侧壁以形成第二孔; 以及在暴露于第二孔的半导体衬底中形成第一导电类型的第三杂质扩散层。

4. 发明授权

US5548156A Method and apparatus for SOI transistor 失效
标题翻译： SOI晶体管的方法和装置
公开(公告)号：US5548156A
公开(公告)日：1996-08-20
申请号：US400447
申请日：1995-03-07
申请人： Hiroyuki Miwa , Takayuki Gomi , Katsuyuki Kato
发明人： Hiroyuki Miwa , Takayuki Gomi , Katsuyuki Kato
IPC分类号： H01L29/73 , H01L21/22 , H01L21/331 , H01L21/38 , H01L27/082 , H01L29/72
CPC分类号： H01L29/7317 , H01L29/66265
摘要： A lateral bipolar transistor capable of forming a narrow-sized diffusion region, such as a base width, is disclosed. The transistor exhibits no scattering in the direction of the depth of the width of the diffusion region. Emitter resistance is reduced by varying an impurity diffusion source at substantially a uniform concentration in a semiconductor portion and forming a diffusion region by diffusion from the impurity diffusion source. The bipolar transistor has an SOI structure. A method of making such device is also disclosed.
摘要翻译：公开了能够形成窄尺寸扩散区域（例如基底宽度）的横向双极晶体管。晶体管在扩散区域的宽度方向上没有散射。通过在半导体部分中以大致均匀的浓度改变杂质扩散源并通过从杂质扩散源的扩散形成扩散区来减小发射极电阻。双极晶体管具有SOI结构。还公开了制造这种装置的方法。

5. 发明授权

US5629217A Method and apparatus for SOI transistor 失效
标题翻译： SOI晶体管的方法和装置
公开(公告)号：US5629217A
公开(公告)日：1997-05-13
申请号：US319150
申请日：1994-10-06
申请人： Hiroyuki Miwa , Takayuki Gomi , Katsuyuki Kato
发明人： Hiroyuki Miwa , Takayuki Gomi , Katsuyuki Kato
IPC分类号： H01L29/73 , H01L21/22 , H01L21/331 , H01L21/38 , H01L21/26 , H01L21/265 , H01L21/306 , H01L21/479
CPC分类号： H01L29/7317 , H01L29/66265
摘要： A lateral bipolar transistor capable of forming a narrow-sized diffusion region, such as a base width, is disclosed. The transistor exhibits no scattering in the direction of the depth of the width of the diffusion region. Emitter resistance is reduced by varying an impurity diffusion source at substantially a uniform concentration in a semiconductor portion and forming a diffusion region by diffusion from the impurity diffusion source. The bipolar transistor has an SOI structure. A method of making such device is also disclosed.
摘要翻译：公开了能够形成窄尺寸扩散区域（例如基底宽度）的横向双极晶体管。晶体管在扩散区域的宽度方向上没有散射。通过在半导体部分中以大致均匀的浓度改变杂质扩散源并通过从杂质扩散源的扩散形成扩散区来减小发射极电阻。双极晶体管具有SOI结构。还公开了制造这种装置的方法。

6. 发明授权

US5783472A Method of making an SOI transistor 失效
标题翻译：制造SOI晶体管的方法
公开(公告)号：US5783472A
公开(公告)日：1998-07-21
申请号：US787797
申请日：1997-01-23
申请人： Hiroyuki Miwa , Takayuki Gomi , Katsuyuki Kato
发明人： Hiroyuki Miwa , Takayuki Gomi , Katsuyuki Kato
IPC分类号： H01L29/73 , H01L21/22 , H01L21/331 , H01L21/38
CPC分类号： H01L29/7317 , H01L29/66265
摘要： A lateral bipolar transistor capable of forming a narrow-sized diffusion region, such as a base width, is disclosed. The transistor exhibits no scattering in the direction of the depth of the width of the diffusion region. Emitter resistance is reduced by varying an impurity diffusion source at substantially a uniform concentration in a semiconductor portion and forming a diffusion region by diffusion from the impurity diffusion source. The bipolar transistor has an SOI structure. A method of making such device is also disclosed.
摘要翻译：公开了能够形成窄尺寸扩散区域（例如基底宽度）的横向双极晶体管。晶体管在扩散区域的宽度方向上没有散射。通过在半导体部分中以大致均匀的浓度改变杂质扩散源并通过从杂质扩散源的扩散形成扩散区来减小发射极电阻。双极晶体管具有SOI结构。还公开了制造这种装置的方法。

7. 发明授权

US5643806A Manufacturing method for making bipolar device 失效
标题翻译：制造双极器件的方法
公开(公告)号：US5643806A
公开(公告)日：1997-07-01
申请号：US472869
申请日：1995-06-07
申请人： Hiroyuki Miwa , Shigeru Kanematsu , Takayuki Gomi , Hiroaki Anmo , Takashi Noguchi , Katsuyuki Kato , Hirokazu Ejiri , Norikazu Ouchi
发明人： Hiroyuki Miwa , Shigeru Kanematsu , Takayuki Gomi , Hiroaki Anmo , Takashi Noguchi , Katsuyuki Kato , Hirokazu Ejiri , Norikazu Ouchi
IPC分类号： H01L21/331 , H01L29/732 , H01L21/265
CPC分类号： H01L29/7322 , H01L29/66272 , Y10S148/01 , Y10S148/011
摘要： A semiconductor device and a manufacturing method therefor which can simultaneously realize both a reduction in base transit time by a reduction in base width and a reduction in base resistance by a reduction in link base resistance. The semiconductor device is manufactured by the method including the steps of forming a first impurity diffused layer of a first conduction type in a semiconductor substrate; forming a conducting film connected to the first impurity diffused layer; forming a first insulating film on the conducting film; forming a first hole through a laminated film composed of the first insulating film and the conducting film; forming a second impurity diffused layer of the first conduction type in the semiconductor substrate exposed to the first hole; forming a side wall from a second insulating film in the first hole to form a second hole; and forming a third impurity diffused layer of the first conduction type in the semiconductor substrate exposed to the second hole.
摘要翻译：一种半导体器件及其制造方法，其可以通过减小基极宽度同时实现基极通过时间的减少，并且通过降低基极电阻降低基极电阻。半导体器件通过包括以下步骤的方法制造：在半导体衬底中形成第一导电类型的第一杂质扩散层; 形成连接到第一杂质扩散层的导电膜; 在导电膜上形成第一绝缘膜; 通过由第一绝缘膜和导电膜构成的层压膜形成第一孔; 在暴露于第一孔的半导体衬底中形成第一导电类型的第二杂质扩散层; 从所述第一孔中的第二绝缘膜形成侧壁以形成第二孔; 以及在暴露于第二孔的半导体衬底中形成第一导电类型的第三杂质扩散层。

8. 发明授权

US5541124A Method for making bipolar transistor having double polysilicon structure 失效
标题翻译：制造具有双重多晶硅结构的双极晶体管的方法
公开(公告)号：US5541124A
公开(公告)日：1996-07-30
申请号：US477471
申请日：1995-06-07
申请人： Hiroyuki Miwa , Shigeru Kanematsu , Takayuki Gomi , Hiroaki Anmo , Takashi Noguchi , Katsuyuki Kato , Hirokazu Ejiri , Norikazu Ouchi
发明人： Hiroyuki Miwa , Shigeru Kanematsu , Takayuki Gomi , Hiroaki Anmo , Takashi Noguchi , Katsuyuki Kato , Hirokazu Ejiri , Norikazu Ouchi
IPC分类号： H01L21/331 , H01L29/732 , H01L21/265
CPC分类号： H01L29/7322 , H01L29/66272 , Y10S148/01 , Y10S148/011
摘要： A semiconductor device and a manufacturing method therefor which can simultaneously realize both a reduction in base transit time by a reduction in base width and a reduction in base resistance by a reduction in link base resistance. The semiconductor device is manufactured by the method including the steps of forming a first impurity diffused layer of a first conduction type in a semiconductor substrate; forming a conducting film connected to the first impurity diffused layer; forming a first insulating film on the conducting film; forming a first hole through a laminated film composed of the first insulating film and the conducting film; forming a second impurity diffused layer of the first conduction type in the semiconductor substrate exposed to the first hole; forming a side wall from a second insulating film in the first hole to form a second hole; and forming a third impurity diffused layer of the first conduction type in the semiconductor substrate exposed to the second hole.
摘要翻译：一种半导体器件及其制造方法，其可以通过减小基极宽度同时实现基极通过时间的减少，并且通过降低基极电阻降低基极电阻。半导体器件通过包括以下步骤的方法制造：在半导体衬底中形成第一导电类型的第一杂质扩散层; 形成连接到第一杂质扩散层的导电膜; 在导电膜上形成第一绝缘膜; 通过由第一绝缘膜和导电膜构成的层压膜形成第一孔; 在暴露于第一孔的半导体衬底中形成第一导电类型的第二杂质扩散层; 从所述第一孔中的第二绝缘膜形成侧壁以形成第二孔; 以及在暴露于第二孔的半导体衬底中形成第一导电类型的第三杂质扩散层。

9. 发明授权

US5786258A Method of making an SOI transistor 失效
公开(公告)号：US5786258A
公开(公告)日：1998-07-28
申请号：US786879
申请日：1997-01-23
申请人： Hiroyuki Miwa , Takayuki Gomi , Katsuyuki Kato
发明人： Hiroyuki Miwa , Takayuki Gomi , Katsuyuki Kato
IPC分类号： H01L29/73 , H01L21/22 , H01L21/331 , H01L21/38
CPC分类号： H01L29/7317 , H01L29/66265
摘要： A lateral bipolar transistor capable of forming a narrow-sized diffusion region, such as a base width, is disclosed. The transistor exhibits no scattering in the direction of the depth of the width of the diffusion region. Emitter resistance is reduced by varying an impurity diffusion source at substantially a uniform concentration in a semiconductor portion and forming a diffusion region by diffusion from the impurity diffusion source. The bipolar transistor has an SOI structure. A method of making such device is also disclosed.

10. 发明授权

US5580797A Method of making SOI Transistor 失效
标题翻译：制造SOI晶体管的方法
公开(公告)号：US5580797A
公开(公告)日：1996-12-03
申请号：US245767
申请日：1994-05-18
申请人： Hiroyuki Miwa , Takayuki Gomi , Katsuyuki Kato
发明人： Hiroyuki Miwa , Takayuki Gomi , Katsuyuki Kato
IPC分类号： H01L29/73 , H01L21/22 , H01L21/331 , H01L21/38 , H01L21/265
CPC分类号： H01L29/7317 , H01L29/66265
摘要： A lateral bipolar transistor capable of forming a narrow-sized diffusion region, such as a base width, is disclosed. The transistor exhibits no scattering in the direction of the depth of the width of the diffusion region. Emitter resistance is reduced by varying an impurity diffusion source at substantially a uniform concentration in a semiconductor portion and forming a diffusion region by diffusion from the impurity diffusion source. The bipolar transistor has an SOI structure. A method of making such device is also disclosed.
摘要翻译：公开了能够形成窄尺寸扩散区域（例如基底宽度）的横向双极晶体管。晶体管在扩散区域的宽度方向上没有散射。通过在半导体部分中以大致均匀的浓度改变杂质扩散源并通过从杂质扩散源扩散形成扩散区来减小发射极电阻。双极晶体管具有SOI结构。还公开了制造这种装置的方法。

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