专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20120086070A1 FABRICATION METHOD AND STRUCTURE OF SEMICONDUCTOR NON-VOLATILE MEMORY DEVICE 审中-公开
标题翻译：半导体非易失性存储器件的制造方法和结构
公开(公告)号：US20120086070A1
公开(公告)日：2012-04-12
申请号：US13328104
申请日：2011-12-16
申请人： Digh HISAMOTO , Shinichiro KIMURA , Kan YASUI , Nozomu MATSUZAKI
发明人： Digh HISAMOTO , Shinichiro KIMURA , Kan YASUI , Nozomu MATSUZAKI
IPC分类号： H01L29/792
CPC分类号： H01L27/11531 , H01L27/115 , H01L27/11526 , H01L27/11546 , H01L27/11568 , H01L29/40117 , H01L29/42344 , H01L29/792
摘要： A non-volatile semiconductor memory device with good write/erase characteristics is provided. A selection gate is formed on a p-type well of a semiconductor substrate via a gate insulator, and a memory gate is formed on the p-type well via a laminated film composed of a silicon oxide film, a silicon nitride film, and a silicon oxide film. The memory gate is adjacent to the selection gate via the laminated film. In the regions on both sides of the selection gate and the memory gate in the p-type well, n-type impurity diffusion layers serving as the source and drain are formed. The region controlled by the selection gate and the region controlled by the memory gate located in the channel region between said impurity diffusion layers have the different charge densities of the impurity from each other.
摘要翻译：提供具有良好写入/擦除特性的非易失性半导体存储器件。通过栅极绝缘体在半导体衬底的p型阱上形成选择栅极，并且通过由氧化硅膜，氮化硅膜和氮化硅膜构成的层叠膜在p型阱上形成存储栅极氧化硅膜。存储器栅极通过层叠膜与选择栅极相邻。在p型阱中的选择栅极和存储栅极的两侧的区域中，形成用作源极和漏极的n型杂质扩散层。由选择栅极控制的区域和由位于所述杂质扩散层之间的沟道区域中的存储栅极控制的区域具有彼此不同的杂质的电荷密度。

2. 发明申请

US20100135080A1 FABRICATION METHOD AND STRUCTURE OF SEMICONDUCTOR NON-VOLATILE MEMORY DEVICE 有权
标题翻译：半导体非易失性存储器件的制造方法和结构
公开(公告)号：US20100135080A1
公开(公告)日：2010-06-03
申请号：US12648796
申请日：2009-12-29
申请人： Digh HISAMOTO , Shinichiro Kimura , Kan Yasui , Nozomu Matsuzaki
发明人： Digh HISAMOTO , Shinichiro Kimura , Kan Yasui , Nozomu Matsuzaki
IPC分类号： G11C16/04 , H01L29/792
CPC分类号： H01L27/11531 , H01L21/28282 , H01L27/115 , H01L27/11526 , H01L27/11546 , H01L27/11568 , H01L29/42344 , H01L29/792
摘要： A non-volatile semiconductor memory device with good write/erase characteristics is provided. A selection gate is formed on a p-type well of a semiconductor substrate via a gate insulator, and a memory gate is formed on the p-type well via a laminated film composed of a silicon oxide film, a silicon nitride film, and a silicon oxide film. The memory gate is adjacent to the selection gate via the laminated film. In the regions on both sides of the selection gate and the memory gate in the p-type well, n-type impurity diffusion layers serving as the source and drain are formed. The region controlled by the selection gate and the region controlled by the memory gate located in the channel region between said impurity diffusion layers have the different charge densities of the impurity from each other.
摘要翻译：提供具有良好写入/擦除特性的非易失性半导体存储器件。通过栅极绝缘体在半导体衬底的p型阱上形成选择栅极，并且通过由氧化硅膜，氮化硅膜和氮化硅膜构成的层叠膜在p型阱上形成存储栅极氧化硅膜。存储器栅极通过层叠膜与选择栅极相邻。在p型阱中的选择栅极和存储栅极的两侧的区域中，形成用作源极和漏极的n型杂质扩散层。由选择栅极控制的区域和由位于所述杂质扩散层之间的沟道区域中的存储栅极控制的区域具有彼此不同的杂质的电荷密度。

3. 发明申请

US20120026798A1 SEMICONDUCTOR NONVOLATILE MEMORY DEVICE 有权
标题翻译：半导体非易失性存储器件
公开(公告)号：US20120026798A1
公开(公告)日：2012-02-02
申请号：US13269425
申请日：2011-10-07
申请人： Digh HISAMOTO , Kan Yasui , Tetsuya Ishimaru , Shinichiro Kimura , Daisuke Okada
发明人： Digh HISAMOTO , Kan Yasui , Tetsuya Ishimaru , Shinichiro Kimura , Daisuke Okada
IPC分类号： G11C16/10
CPC分类号： G11C16/0425 , G11C16/12 , G11C16/14 , G11C16/26 , G11C16/3454 , G11C16/3459
摘要： An operation scheme for operating stably a semiconductor nonvolatile memory device is provided.When hot-hole injection is conducted in the semiconductor nonvolatile memory device of a split gate structure, the hot-hole injection is verified using a crossing point that does not change with time. Thus, an erased state can be verified without being aware of any time-varying changes.Also, programming or programming/erasure is conducted by repeating pulse voltage or multi-step voltage application to a gate section multiple times.
摘要翻译：提供一种稳定运行半导体非易失性存储器件的操作方案。当在分裂栅极结构的半导体非易失性存储器件中进行热空穴注入时，使用不随时间变化的交叉点来验证热孔注入。因此，可以验证擦除状态，而不知道任何时变变化。此外，通过将多次脉冲电压或多级电压施加到栅极部分进行编程或编程/擦除。

4. 发明申请

US20100232231A1 SEMICONDUCTOR NONVOLATILE MEMORY DEVICE 有权
标题翻译：半导体非易失性存储器件
公开(公告)号：US20100232231A1
公开(公告)日：2010-09-16
申请号：US12787158
申请日：2010-05-25
申请人： Digh HISAMOTO , Kan Yasui , Tetsuya Ishimaru , Shinichiro Kimura , Daisuke Okada
发明人： Digh HISAMOTO , Kan Yasui , Tetsuya Ishimaru , Shinichiro Kimura , Daisuke Okada
IPC分类号： G11C16/06 , G11C11/34
CPC分类号： G11C16/0425 , G11C16/12 , G11C16/14 , G11C16/26 , G11C16/3454 , G11C16/3459
摘要： An operation scheme for operating stably a semiconductor nonvolatile memory device is provided.When hot-hole injection is conducted in the semiconductor nonvolatile memory device of a split gate structure, the hot-hole injection is verified using a crossing point that does not change with time. Thus, an erased state can be verified without being aware of any time-varying changes.Also, programming or programming/erasure is conducted by repeating pulse voltage or multi-step voltage application to a gate section multiple times.
摘要翻译：提供一种稳定运行半导体非易失性存储器件的操作方案。当在分裂栅极结构的半导体非易失性存储器件中进行热空穴注入时，使用不随时间变化的交叉点来验证热孔注入。因此，可以验证擦除状态，而不知道任何时变变化。此外，通过将多次脉冲电压或多级电压施加到栅极部分进行编程或编程/擦除。

5. 发明申请

US20100203697A1 INTEGRATED SEMICONDUCTOR NONVOLATILE STORAGE DEVICE 有权
标题翻译：集成半导体非易失存储器件
公开(公告)号：US20100203697A1
公开(公告)日：2010-08-12
申请号：US12763402
申请日：2010-04-20
申请人： Digh HISAMOTO , Shin'ichiro Kimura , Daiske Okada , Kan Yasui
发明人： Digh HISAMOTO , Shin'ichiro Kimura , Daiske Okada , Kan Yasui
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , G11C16/0425 , H01L21/28282 , H01L27/11568 , H01L29/792
摘要： An object of the present invention is to provide an integrated semiconductor nonvolatile storage device that can be read at high speed and reprogrammed an increased number of times.In the case of conventional nonvolatile semiconductor storage devices having a split-gate structure, there is a tradeoff between the read current and the maximum allowable number of reprogramming operations. To overcome this problem, an integrated semiconductor nonvolatile storage device of the present invention is configured such that memory cells having different memory gate lengths are integrated on the same chip. This allows the device to be read at high speed and reprogrammed an increased number of times.
摘要翻译：本发明的目的是提供一种可以高速读取并重新编程次数增加的集成半导体非易失性存储装置。在具有分割栅结构的常规非易失性半导体存储器件的情况下，读取电流和最大可允许重编程操作次数之间存在权衡。为了克服这个问题，本发明的集成半导体非易失性存储装置被配置成使得具有不同存储器栅极长度的存储单元集成在同一芯片上。这允许以高速读取设备并重新编程增加的次数。

6. 发明申请

US20090122609A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20090122609A1
公开(公告)日：2009-05-14
申请号：US12354867
申请日：2009-01-16
申请人： Tsutomu OKAZAKI , Daisuke OKADA , Kyoya NITTA , Toshihiro TANAKA , Akira KATA , Toshikazu MATSUI , Yasushi ISHII , Digh HISAMOTO , Kan YASUI
发明人： Tsutomu OKAZAKI , Daisuke OKADA , Kyoya NITTA , Toshihiro TANAKA , Akira KATA , Toshikazu MATSUI , Yasushi ISHII , Digh HISAMOTO , Kan YASUI
IPC分类号： G11C16/04 , H01L27/115
CPC分类号： H01L27/1157 , G11C16/0425 , H01L21/28282 , H01L27/0207 , H01L27/105 , H01L27/115 , H01L27/11568 , H01L29/0649 , H01L29/4234 , H01L29/42344 , H01L29/518 , H01L29/66833 , H01L29/792
摘要： A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.
摘要翻译：半导体存储器阵列包括具有第一电荷存储层和第一非易失性存储单元的第一非易失性存储单元，第一非易失性存储单元与第一存储单元相邻，具有第二电荷存储层和第二栅电极。第一电极和第二电极在垂直于第一方向的第二方向上延伸，第一电极具有在第一方向上朝向第二电极延伸的第一接触部分，并且第二电极具有朝向第一电极的第二接触部分第一个方向第一和第二接触位置分别沿第二方向移动，第一电极和第一接触部分与第二电极和第二接触部分电气分离。

7. 发明申请

US20080197362A1 SEMICONDUCTOR LED, OPTO-ELECTRONIC INTEGRATED CIRCUITS (OEIC), AND METHOD OF FABRICATING OEIC 有权
标题翻译：半导体LED，光电集成电路（OEIC）和制造OEIC的方法
公开(公告)号：US20080197362A1
公开(公告)日：2008-08-21
申请号：US11935904
申请日：2007-11-06
申请人： Digh HISAMOTO , Shinichi Saito , Shinichiro Kimura
发明人： Digh HISAMOTO , Shinichi Saito , Shinichiro Kimura
IPC分类号： H01L33/00
CPC分类号： H01L27/15 , G02B6/13 , G02B6/43 , H01L33/02 , H01L33/34
摘要： A light emitting diode demonstrating high luminescence efficiency and comprising a Group IV semiconductor such as silicon or germanium equivalent thereto as a basic component formed on a silicon substrate by a prior art silicon process, and a fabricating method of waveguide thereof are provided. The light emitting diode of the invention comprises a first electrode for implanting electrons, a second electrode for implanting holes, and a light emitting section electrically connected to the first and the second electrode, wherein the light emitting section is made out of single crystalline silicon and has a first surface and a second surface facing the first surface, wherein with respect to plane orientation (100) of the first and second surfaces, the light emitting section crossing at right angles to the first and second surfaces is made thinner, and wherein a material having a high refractive index is arranged around the thin film section.
摘要翻译：提供了高发光效率的发光二极管，并且包括通过现有技术的硅工艺在硅衬底上形成的等价于其的硅或锗等IV族半导体作为基底部件，以及其波导管的制造方法。本发明的发光二极管包括用于注入电子的第一电极，用于注入孔的第二电极和与第一和第二电极电连接的发光部分，其中发光部分由单晶硅制成，具有面对第一表面的第一表面和第二表面，其中相对于第一表面和第二表面的平面取向（100），使与第一表面和第二表面成直角交叉的发光部分变薄，并且其中具有高折射率的材料设置在薄膜部分周围。

8. 发明申请

US20110001179A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110001179A1
公开(公告)日：2011-01-06
申请号：US12820468
申请日：2010-06-22
申请人： Itaru YANAGI , Digh HISAMOTO , Daisuke OKADA , Atushi YOSHITOMI , Yasufumi MORIMOTO , Toshiyuki MINE
发明人： Itaru YANAGI , Digh HISAMOTO , Daisuke OKADA , Atushi YOSHITOMI , Yasufumi MORIMOTO , Toshiyuki MINE
IPC分类号： H01L27/115 , H01L29/788
CPC分类号： H01L29/42344 , G11C16/0408 , H01L27/11568 , H01L29/40117 , H01L29/66833 , H01L29/792
摘要： In a non-volatile memory in which charge is injected from a gate electrode to a charge accumulating layer, charge injection efficiency, charge retention characteristic and reliability are all improved compared with a conventional gate structure. In a nonvolatile memory which carries out write/erasure by changing the total charge amount by injecting electrons and holes into a silicon nitride film which makes up a charge accumulating layer, in order to highly efficiently carry out charge injection from a gate electrode, the gate electrode of a memory cell is made up of a two-layer film of a non-doped polysilicon layer and a metal material electrode layer.
摘要翻译：在从栅电极向电荷累积层注入电荷的非易失性存储器中，与常规栅极结构相比，电荷注入效率，电荷保持特性和可靠性都得到改善。在通过将电子和空穴注入构成电荷积聚层的氮化硅膜中来改变总电荷量而进行写入/擦除的非易失性存储器中，为了从栅电极高效地进行电荷注入，存储单元的电极由非掺杂多晶硅层和金属材料电极层的两层膜构成。

9. 发明申请

US20090273014A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 审中-公开
标题翻译：非易失性半导体存储器件
公开(公告)号：US20090273014A1
公开(公告)日：2009-11-05
申请号：US12430088
申请日：2009-04-26
申请人： Tsuyoshi ARIGANE , Digh HISAMOTO , Yasuhiro SHIMAMOTO , Hideo KASAI , Ken MATSUBARA
发明人： Tsuyoshi ARIGANE , Digh HISAMOTO , Yasuhiro SHIMAMOTO , Hideo KASAI , Ken MATSUBARA
IPC分类号： H01L29/788 , H01L29/792
CPC分类号： H01L29/4234 , H01L27/11568 , H01L27/11573 , H01L29/792
摘要： Each of a memory gate, a control gate, a source diffusion layer, and a drain diffusion layer is connected to a control circuit for controlling potential, and the control circuit operates so as to supply a first potential to the memory gate, a second potential to the control gate, a third potential to the drain diffusion layer, and a fourth potential to the source diffusion layer. Here, after setting the memory gate to be in a floating state by shifting a switch transistor from an ON state to an OFF state, the control circuit operates so as to supply a sixth potential which is higher than the second potential to the control gate to make the memory gate have a fifth potential which is higher than the first potential, thereby boosting the memory gate.
摘要翻译：存储器栅极，控制栅极，源极扩散层和漏极扩散层中的每一个连接到用于控制电位的控制电路，并且控制电路工作以向存储栅极提供第一电位，第二电位到所述控制栅极，到所述漏极扩散层的第三电位，以及到所述源极扩散层的第四电位。这里，通过将开关晶体管从导通状态切换到断开状态，在将存储栅极设定为浮置状态之后，控制电路动作以向控制栅极提供比第二电位高的第六电位，使存储器栅极具有高于第一电位的第五电位，从而提高存储器栅极。

10. 发明申请

US20080073705A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20080073705A1
公开(公告)日：2008-03-27
申请号：US11829248
申请日：2007-07-27
申请人： Digh HISAMOTO , Itaru Yanagi , Yasuhiro Shimamoto , Toshiyuki Mine , Yutaka Okuyama
发明人： Digh HISAMOTO , Itaru Yanagi , Yasuhiro Shimamoto , Toshiyuki Mine , Yutaka Okuyama
IPC分类号： H01L29/792
CPC分类号： H01L29/792 , G11C16/0425 , G11C16/10 , H01L27/115 , H01L27/11568 , H01L29/66833
摘要： A gate dielectric functioning as a charge-trapping layer of a non-volatile memory cell with a structure of an insulator gate field effect transistor is formed by laminating a first insulator formed of a silicon oxide film, a second insulator formed of a silicon nitride film, a third insulator formed of a silicon nitride film containing oxygen, and a fourth insulator formed of a silicon oxide film in this order on a main surface of a semiconductor substrate. Holes are injected into the charge-trapping layer from a gate electrode side. Accordingly, since the operations can be achieved without the penetration of the holes through the interface in contact to the channel and the first insulator, the deterioration in rewriting endurance and the charge-trapping characteristics due to the deterioration of the first insulator does not occur, and highly efficient rewriting (writing and erasing) characteristics and stable charge-trapping characteristics can be achieved.
摘要翻译：作为具有绝缘体栅极场效应晶体管的结构的非易失性存储单元的电荷捕获层的栅极介质通过层叠由氧化硅膜形成的第一绝缘体，由氮化硅膜形成的第二绝缘体由半导体衬底的主表面依次由含有氧的氮化硅膜构成的第三绝缘体和由氧化硅膜形成的第四绝缘体构成。孔从栅电极侧注入电荷捕获层。因此，由于可以在没有孔穿过与沟道和第一绝缘体接触的界面的情况下实现操作，所以不会发生由于第一绝缘体的劣化导致的重写耐久性和电荷捕获特性的劣化，并且可以实现高效的重写（写入和擦除）特性和稳定的电荷捕获特性。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式