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热词
    • 1. 发明授权
    • Testable integrated circuit, integrated circuit design-for-testability method, and computer-readable medium storing a program for implementing the design-for-testability method
    • 可测试的集成电路,用于可测试性的集成电路设计方法和存储用于实现可设计性测试方法的程序的计算机可读介质
    • US06334200B1
    • 2001-12-25
    • US09203372
    • 1998-12-02
    • Hideo FujiwaraToshimitsu MasuzawaSatoshi Ohtake
    • Hideo FujiwaraToshimitsu MasuzawaSatoshi Ohtake
    • G01R3128
    • G01R31/318392G01R31/318522
    • Apparatus for testing integrated circuits containing a controller or other sequential circuit at actual operating speed while minimizing the length of the test sequence and achieving high fault coverage are provided. The states of a state register are assumed controllable and observable, and a set of test patterns is obtained for a combinational circuit not containing said state register. An invalid-state generation logic circuit is added for generating invalid states, which are states contained in the generated test patterns but cannot be set by a normal transition from the reset state. A multiplexer is added for selecting the output of a next-state generation logic circuit or the invalid-state generation logic circuit for input to the state register based on a state transition mode selection signal. Signals corresponding to pseudo-primary outputs during test generation are made observable, and the multiplexer output signal is externally detectable as a state output signal.
    • 提供了用于在实际操作速度下测试包含控制器或其他顺序电路的集成电路的装置,同时最小化测试序列的长度并实现高故障覆盖。 状态寄存器的状态是可控的和可观察的,并且对于不包含所述状态寄存器的组合电路获得一组测试图案。 添加无效状态生成逻辑电路,用于生成无效状态,这些状态是生成的测试模式中包含的状态,但不能通过从复位状态的正常转换来设置。 添加多路复用器,用于根据状态转换模式选择信号选择下一状态生成逻辑电路的输出或无效状态生成逻辑电路,以输入到状态寄存器。 在测试生成期间对应于伪初级输出的信号是可观察的,并且多路复用器输出信号作为状态输出信号在外部可检测。
    • 2. 发明授权
    • Integrated circuit with design for testability and method for designing the same
    • 具有可测试性设计的集成电路及其设计方法
    • US06735730B1
    • 2004-05-11
    • US09699478
    • 2000-10-31
    • Hideo FujiwaraToshimitsu MasuzawaSatoshi Ohtake
    • Hideo FujiwaraToshimitsu MasuzawaSatoshi Ohtake
    • G01R3128
    • G01R31/3183G01R31/31724
    • A test controller 4 has a test plan generating unit 11 for generating a test plan of a data path 2 which is formed to have a fixed control testability in which a test plan constituted by three phases, that is, the propagation of a test vector to a data input, the execution of a test and the propagation of an output response is present for each test object module. Thus, an integrated circuit is capable of supplying a test plan as a time series of a control signal to a control input of a data path, shortening a test execution time and generating the test plan at the normal operation speed of the circuit, thereby carrying out a test at an actual operation speed and an integrated circuit designing method.
    • 测试控制器4具有测试计划生成单元11,用于生成数据路径2的测试计划,数据路径2形成为具有固定控制可测试性,其中由三个阶段构成的测试计划,即测试向量的传播到 对于每个测试对象模块,存在数据输入,测试的执行和输出响应的传播。 因此,集成电路能够将作为控制信号的时间序列的测试计划提供给数据路径的控制输入,缩短测试执行时间,并以电路的正常操作速度生成测试计划,从而携带 以实际运行速度进行测试和集成电路设计方法。