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    • 6. 发明授权
    • Integrated circuit with design for testability and method for designing the same
    • 具有可测试性设计的集成电路及其设计方法
    • US06735730B1
    • 2004-05-11
    • US09699478
    • 2000-10-31
    • Hideo FujiwaraToshimitsu MasuzawaSatoshi Ohtake
    • Hideo FujiwaraToshimitsu MasuzawaSatoshi Ohtake
    • G01R3128
    • G01R31/3183G01R31/31724
    • A test controller 4 has a test plan generating unit 11 for generating a test plan of a data path 2 which is formed to have a fixed control testability in which a test plan constituted by three phases, that is, the propagation of a test vector to a data input, the execution of a test and the propagation of an output response is present for each test object module. Thus, an integrated circuit is capable of supplying a test plan as a time series of a control signal to a control input of a data path, shortening a test execution time and generating the test plan at the normal operation speed of the circuit, thereby carrying out a test at an actual operation speed and an integrated circuit designing method.
    • 测试控制器4具有测试计划生成单元11,用于生成数据路径2的测试计划,数据路径2形成为具有固定控制可测试性,其中由三个阶段构成的测试计划,即测试向量的传播到 对于每个测试对象模块,存在数据输入,测试的执行和输出响应的传播。 因此,集成电路能够将作为控制信号的时间序列的测试计划提供给数据路径的控制输入,缩短测试执行时间,并以电路的正常操作速度生成测试计划,从而携带 以实际运行速度进行测试和集成电路设计方法。