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1. 发明授权

US08329559B2 Damascene process for use in fabricating semiconductor structures having micro/nano gaps 有权
标题翻译：用于制造具有微/纳米间隙的半导体结构的镶嵌工艺
公开(公告)号：US08329559B2
公开(公告)日：2012-12-11
申请号：US11737545
申请日：2007-04-19
申请人： Hideki Takeuchi , Emmanuel P. Quevy , Tsu-Jae King , Roger T. Howe
发明人： Hideki Takeuchi , Emmanuel P. Quevy , Tsu-Jae King , Roger T. Howe
IPC分类号： H01L21/46 , H01L21/78 , H01L21/301
CPC分类号： B81C1/00142 , B81B2201/0271 , B81C2201/0109 , Y10S438/933
摘要： In fabricating a microelectromechanical structure (MEMS), a method of forming a narrow gap in the MEMS includes a) depositing a layer of sacrificial material on the surface of a supporting substrate, b) photoresist masking and at least partially etching the sacrificial material to form at least one blade of sacrificial material, c) depositing a structural layer over the sacrificial layer, and d) removing the sacrificial layer including the blade of the sacrificial material with a narrow gap remaining in the structural layer where the blade of sacrificial material was removed.
摘要翻译：在制造微机电结构（MEMS）中，在MEMS中形成窄间隙的方法包括：a）在支撑衬底的表面上沉积牺牲材料层，b）光致抗蚀剂掩模并且至少部分蚀刻牺牲材料以形成至少一个牺牲材料刀片，c）在所述牺牲层上沉积结构层，以及d）去除包括所述牺牲材料刀片的所述牺牲层，其中所述牺牲材料刀片被去除的所述结构层中残留有窄间隙。

2. 发明申请

US20120171798A1 DAMASCENE PROCESS FOR USE IN FABRICATING SEMICONDUCTOR STRUCTURES HAVING MICRO/NANO GAPS 有权
标题翻译：用于制造具有微米/纳米GAPS的半导体结构的大分子方法
公开(公告)号：US20120171798A1
公开(公告)日：2012-07-05
申请号：US11737545
申请日：2007-04-19
申请人： Hideki Takeuchi , Emmanuel P. Quevy , Tsu-Jae King , Roger T. Howe
发明人： Hideki Takeuchi , Emmanuel P. Quevy , Tsu-Jae King , Roger T. Howe
IPC分类号： H01L21/02
CPC分类号： B81C1/00142 , B81B2201/0271 , B81C2201/0109 , Y10S438/933
摘要： In fabricating a microelectromechanical structure (MEMS), a method of forming a narrow gap in the MEMS includes a) depositing a layer of sacrificial material on the surface of a supporting substrate, b) photoresist masking and at least partially etching the sacrificial material to form at least one blade of sacrificial material, c) depositing a structural layer over the sacrificial layer, and d) removing the sacrificial layer including the blade of the sacrificial material with a narrow gap remaining in the structural layer where the blade of sacrificial material was removed.
摘要翻译：在制造微机电结构（MEMS）中，在MEMS中形成窄间隙的方法包括：a）在支撑衬底的表面上沉积牺牲材料层，b）光致抗蚀剂掩模并且至少部分蚀刻牺牲材料以形成至少一个牺牲材料刀片，c）在所述牺牲层上沉积结构层，以及d）去除包括所述牺牲材料刀片的所述牺牲层，其中所述牺牲材料刀片被去除的所述结构层中残留有窄间隙。

3. 发明授权

US07256107B2 Damascene process for use in fabricating semiconductor structures having micro/nano gaps 有权
标题翻译：用于制造具有微/纳米间隙的半导体结构的镶嵌工艺
公开(公告)号：US07256107B2
公开(公告)日：2007-08-14
申请号：US11121690
申请日：2005-05-03
申请人： Hideki Takeuchi , Emmanuel P. Quevy , Tsu-Jae King , Roger T. Howe
发明人： Hideki Takeuchi , Emmanuel P. Quevy , Tsu-Jae King , Roger T. Howe
IPC分类号： H01L21/46 , H01L21/78 , H01L21/301
CPC分类号： B81C1/00142 , B81B2201/0271 , B81C2201/0109 , Y10S438/933
摘要： In fabricating a microelectromechanical structure (MEMS), a method of forming a narrow gap in the MEMS includes a) depositing a layer of sacrificial material on the surface of a supporting substrate, b) photoresist masking and at least partially etching the sacrificial material to form at least one blade of sacrificial material, c) depositing a structural layer over the sacrificial layer, and d) removing the sacrificial layer including the blade of the sacrificial material with a narrow gap remaining in the structural layer where the blade of sacrificial material was removed.
摘要翻译：在制造微机电结构（MEMS）中，在MEMS中形成窄间隙的方法包括：a）在支撑衬底的表面上沉积牺牲材料层，b）光致抗蚀剂掩模并且至少部分蚀刻牺牲材料以形成至少一个牺牲材料刀片，c）在所述牺牲层上沉积结构层，以及d）去除包括所述牺牲材料刀片的所述牺牲层，其中所述牺牲材料刀片被去除的所述结构层中残留有窄间隙。

4. 发明授权

US06448622B1 Polycrystalline silicon-germanium films for micro-electromechanical systems application 有权
标题翻译：用于微机电系统应用的多晶硅锗膜
公开(公告)号：US06448622B1
公开(公告)日：2002-09-10
申请号：US09617300
申请日：2000-07-17
申请人： Andrea Franke , Roger T. Howe , Tsu-Jae King
发明人： Andrea Franke , Roger T. Howe , Tsu-Jae King
IPC分类号： H01L2982
CPC分类号： B81C1/00246 , B81B2203/0118 , B81C2201/0109 , B81C2203/0735 , Y10S438/933
摘要： This invention relates to micro-electromechanical systems using silicon-germanium films. Such a system includes one or more layers of Si1−xGex, deposited on a substrate, where 0
摘要翻译：本发明涉及使用硅 - 锗膜的微机电系统。这种系统包括沉积在衬底上的一层或多层Si1-xGex，其中0

5. 发明授权

US06210988B1 Polycrystalline silicon germanium films for forming micro-electromechanical systems 有权
标题翻译：用于形成微机电系统的多晶硅锗膜
公开(公告)号：US06210988B1
公开(公告)日：2001-04-03
申请号：US09483222
申请日：2000-01-14
申请人： Roger T. Howe , Andrea Franke , Tsu-Jae King
发明人： Roger T. Howe , Andrea Franke , Tsu-Jae King
IPC分类号： H01L2100
CPC分类号： B81C1/00246 , B81B2203/0118 , B81C2201/0109 , B81C2203/0735 , Y10S438/933
摘要： This invention relates to micro-electromechanical systems using silicon-germanium films.
摘要翻译：本发明涉及使用硅 - 锗膜的微机电系统

6. 发明申请

US20050250236A1 Damascene process for use in fabricating semiconductor structures having micro/nano gaps 有权
标题翻译：用于制造具有微/纳米间隙的半导体结构的镶嵌工艺
公开(公告)号：US20050250236A1
公开(公告)日：2005-11-10
申请号：US11121690
申请日：2005-05-03
申请人： Hideki Takeuchi , Emmanuel Quevy , Tsu-Jae King , Roger Howe
发明人： Hideki Takeuchi , Emmanuel Quevy , Tsu-Jae King , Roger Howe
IPC分类号： H01L21/00
CPC分类号： B81C1/00142 , B81B2201/0271 , B81C2201/0109 , Y10S438/933
摘要： In fabricating a microelectromechanical structure (MEMS), a method of forming a narrow gap in the MEMS includes a) depositing a layer of sacrificial material on the surface of a supporting substrate, b) photoresist masking and at least partially etching the sacrificial material to form at least one blade of sacrificial material, c) depositing a structural layer over the sacrificial layer, and d) removing the sacrificial layer including the blade of the sacrificial material with a narrow gap remaining in the structural layer where the blade of sacrificial material was removed.
摘要翻译：在制造微机电结构（MEMS）中，在MEMS中形成窄间隙的方法包括：a）在支撑衬底的表面上沉积牺牲材料层，b）光致抗蚀剂掩模并且至少部分蚀刻牺牲材料以形成至少一个牺牲材料刀片，c）在所述牺牲层上沉积结构层，以及d）去除包括所述牺牲材料刀片的所述牺牲层，其中所述牺牲材料刀片被去除的所述结构层中残留有窄间隙。

7. 发明申请

US20090128221A1 METAL-INSULATOR-METAL (MIM) SWITCHING DEVICES 有权
标题翻译：金属绝缘子金属（MIM）开关器件
公开(公告)号：US20090128221A1
公开(公告)日：2009-05-21
申请号：US12261865
申请日：2008-10-30
申请人： Hei Kam , Tsu-Jae King
发明人： Hei Kam , Tsu-Jae King
IPC分类号： H01L27/092 , H03K17/687
CPC分类号： G11C23/00 , B82Y10/00 , H01H1/0094
摘要： A gated nano-electro-mechanical (NEM) switch employing metal-insulator-metal (MIM) technology and related devices and methods which can facilitate implementation of low-power, radiation-hardened, high-temperature electronic devices and circuits. In one example embodiment a gate electrode is configured as a cantilever beam whose free end is coupled to a MIM stack. The stack moves into bridging contact across a source and drain region when the applied gate voltage generates a sufficient electrostatic force to overcome the mechanical biasing of the cantilever beam. A second set of contacts can be added on the cantilever beam to form a complementary switching structure, or to a separate cantilever beam. The switching can be configured as non-volatile in response to stiction forces. NEM circuits provide a number of advantages within a variety of circuit types, including but not limited to: logic, memory, sleep circuits, pass circuits, and so forth.
摘要翻译：采用金属 - 绝缘体 - 金属（MIM）技术的门控纳米机电（NEM）开关及相关设备和方法，可以促进低功耗，辐射硬化，高温电子器件和电路的实现。在一个示例实施例中，栅电极被配置为悬臂梁，其自由端耦合到MIM堆叠。当施加的栅极电压产生足够的静电力以克服悬臂梁的机械偏置时，堆叠移动跨越源极和漏极区域的桥接接触。可以在悬臂梁上添加第二组触点以形成互补的开关结构，或者形成单独的悬臂梁。响应于静力，可以将开关配置为非易失性。 NEM电路在各种电路类型中提供了许多优点，包括但不限于：逻辑，存储器，睡眠电路，通过电路等。

8. 发明申请

US20090121273A1 Low-voltage memory having flexible gate charging element 审中-公开
标题翻译：具有柔性栅极充电元件的低电压存储器
公开(公告)号：US20090121273A1
公开(公告)日：2009-05-14
申请号：US11664018
申请日：2005-09-22
申请人： Tsu-Jae King , Gang Liu , Min She
发明人： Tsu-Jae King , Gang Liu , Min She
IPC分类号： H01L29/68 , H01L29/788
CPC分类号： H01L21/28194 , H01L27/115 , H01L27/11521 , H01L29/40114 , H01L29/42324 , H01L29/518
摘要： In a non-volatile semiconductor memory device including a source region separated from a drain region by a channel region and with an electrically floating gate electrode spaced from and overlying the channel region, a flexible member is spaced from the floating gate and capable of being flexed towards the floating gate for depositing or removing electrical charge on the floating gate in response to a voltage potential between the flexible member and the channel region. In one embodiment, the flexible member comprises a contact gate electrode. In another embodiment, only a single gate electrode is employed without a separate floating gate.
摘要翻译：在非易失性半导体存储器件中，包括通过沟道区域与漏极区域分离的源极区域和与沟道区域间隔开并且覆盖沟道区域的电浮置栅电极，柔性构件与浮动栅极间隔开并能够弯曲朝向浮动栅极，以响应于柔性构件和沟道区域之间的电压电位在浮栅上沉积或去除电荷。在一个实施例中，柔性构件包括接触栅电极。在另一个实施例中，仅使用单个栅电极而没有单独的浮栅。

9. 发明申请

US20070183185A1 FINFET-BASED SRAM WITH FEEDBACK 审中-公开
标题翻译：具有反馈功能的基于FINFET的SRAM
公开(公告)号：US20070183185A1
公开(公告)日：2007-08-09
申请号：US11622305
申请日：2007-01-11
申请人： Zheng Guo , Sriram Balasubramanian , Radu Zlatanovici , Tsu-Jae King , Borivoje Nikolic
发明人： Zheng Guo , Sriram Balasubramanian , Radu Zlatanovici , Tsu-Jae King , Borivoje Nikolic
IPC分类号： G11C11/00
CPC分类号： G11C11/412 , H01L27/11 , H01L27/1104 , H01L27/1108 , H01L29/785
摘要： Intrinsic variations and challenging leakage control in current bulk-Si MOSFETs force undesired tradeoffs to be made and limit the scaling of SRAM circuits. Circuits and mechanisms are taught herein which improve leakage and noise margin in SRAM cells, such as those comprising either six-transistor (6-T) SRAM cell designs, or four-transistor (4-T) SRAM cell designs. The inventive SRAM cells utilize a feedback means coupling a portion of the storage node to a back-gate of an access transistor. Preferably feedback is coupled in this manner to both access transistors. SRAM cells designed with this built-in feedback achieve significant improvements in cell static noise margin (SNM) without area penalty. Use of the feedback scheme also results in the creation of a practical 4-T FinFET-based SRAM cell that achieves sub-100 pA per-cell standby current and offers similar improvements in SNM as the 6-T cell with feedback.
摘要翻译：当前体硅Si MOSFET中的固有变化和具有挑战性的泄漏控制迫使不需要的折衷，并限制了SRAM电路的缩放。本文教导了改善SRAM单元中的泄漏和噪声容限的电路和机构，例如包括六晶体管（6-T）SRAM单元设计或四晶体管（4-T）SRAM单元设计）的那些。本发明的SRAM单元利用将存储节点的一部分耦合到存取晶体管的后栅极的反馈装置。反馈优选以这种方式耦合到两个存取晶体管。使用这种内置反馈设计的SRAM单元实现了细胞静态噪声容限（SNM）的显着改进，无区域损失。反馈方案的使用还导致创建了实用的基于4-T FinFET的SRAM单元，其实现了每个100pA的每个电池的待机电流，并且具有与具有反馈的6-T电池相似的SNM改进。

10. 发明授权

US07141858B2 Dual work function CMOS gate technology based on metal interdiffusion 失效
公开(公告)号：US07141858B2
公开(公告)日：2006-11-28
申请号：US10871338
申请日：2004-06-18
申请人： Igor Polishchuk , Pushkar Ranade , Tsu-Jae King , Chenming Hu
发明人： Igor Polishchuk , Pushkar Ranade , Tsu-Jae King , Chenming Hu
IPC分类号： H01L29/49
CPC分类号： H01L21/28079 , H01L21/823842 , H01L29/4958
摘要： A gate structure for a MOSFET device comprises a gate insulation layer, a first layer of a first metal abutting the gate insulation layer, and a second layer overlying the first layer and comprising a mixture of the metal of the first layer and a second metal, the metal layers formed by the diffusion of the first metal into and through the second metal. The second metal can be used as the gate for a n-MOS transistor, and the mixture of first metal and second metal overlying a layer of the first metal can be used as a gate for a p-MOS transistor where the first metal has a work function of about 5.2 eV and the second metal has a work function of about 4.1 eV.

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