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    • 9. 发明授权
    • Information processing apparatus capable of reading data from memory at high speed
    • 能够高速地从存储器读取数据的信息处理装置
    • US06330651B1
    • 2001-12-11
    • US09563754
    • 2000-05-01
    • Hitoshi KawaguchiKoichi KimuraHideki KamimakiTakayuki TamuraKazushi Kobayashi
    • Hitoshi KawaguchiKoichi KimuraHideki KamimakiTakayuki TamuraKazushi Kobayashi
    • G06F1314
    • G06F13/1689
    • An information processing apparatus is provided which is capable of carrying out the higher memory access. The information processing apparatus includes a memory unit of a synchronous DRAM device which serves to output data synchronously with the supplied clock signal, and a control unit for controlling the access to the memory unit in accordance with an instruction issued from a CPU. The clock signal which is to be supplied to the memory unit is outputted from the control unit. The clock signal which has been outputted from the control unit is supplied to the memory unit and also is pulled back to the control unit. The control unit fetches therein the data, which has been outputted from the storage unit, at the timing which is determined on the basis of the pulled back clock signal. As a result, the control unit reduces the difference between a delay of the data which is outputted from the control unit and a delay of the clock signal which is used to determine the timing at which the data is fetched therein.
    • 提供一种能够执行较高存储器访问的信息处理装置。 信息处理装置包括用于与所提供的时钟信号同步地输出数据的同步DRAM装置的存储单元,以及用于根据从CPU发出的指令来控制对存储器单元的访问的控制单元。 从控制单元输出要提供给存储单元的时钟信号。 从控制单元输出的时钟信号被提供给存储单元,并且还被拉回到控制单元。 控制单元在基于拉回时钟信号确定的定时从其中取出已经从存储单元输出的数据。 结果,控制单元减少从控制单元输出的数据的延迟与用于确定其中提取数据的定时的时钟信号的延迟之间的差异。
    • 10. 发明授权
    • Information processing apparatus with connection between memory and
memory control unit
    • 具有存储器和存储器控制单元之间的连接的信息处理设备
    • US5828871A
    • 1998-10-27
    • US601546
    • 1996-02-14
    • Hitoshi KawaguchiKoichi KimuraHideki KamimakiTakayuki TamuraKazushi Kobayashi
    • Hitoshi KawaguchiKoichi KimuraHideki KamimakiTakayuki TamuraKazushi Kobayashi
    • G06F12/00G06F1/10G06F1/12G06F13/16G11C11/401G11C11/407
    • G06F13/1689
    • An information processing apparatus is provided which is capable of carrying out the higher memory access. The information processing apparatus includes a memory unit of a synchronous DRAM device which serves to output data synchronously with the supplied clock signal, and a control unit for controlling the access to the memory unit in accordance with an instruction issued from a CPU. The clock signal which is to be supplied to the memory unit is outputted from the control unit. The clock signal which has been outputted from the control unit is supplied to the memory unit and also is pulled back to the control unit. The control unit fetches therein the data, which has been outputted from the storage unit, at the timing which is determined on the basis of the pulled back clock signal. As a result, the control unit reduces the difference between a delay of the data which is outputted from the control unit and a delay of the clock signal which is used to determine the timing at which the data is fetched therein.
    • 提供一种能够执行较高存储器访问的信息处理装置。 信息处理装置包括用于与所提供的时钟信号同步地输出数据的同步DRAM装置的存储单元,以及用于根据从CPU发出的指令来控制对存储器单元的访问的控制单元。 从控制单元输出要提供给存储单元的时钟信号。 从控制单元输出的时钟信号被提供给存储单元,并且还被拉回到控制单元。 控制单元在基于拉回时钟信号确定的定时从其中取出已经从存储单元输出的数据。 结果,控制单元减少从控制单元输出的数据的延迟与用于确定其中提取数据的定时的时钟信号的延迟之间的差异。