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1. 发明授权

US09454048B2 Liquid crystal display device and manufacturing method of liquid crystal display device 有权
标题翻译：液晶显示装置及液晶显示装置的制造方法
公开(公告)号：US09454048B2
公开(公告)日：2016-09-27
申请号：US13416077
申请日：2012-03-09
申请人： Hidekazu Miyairi , Tetsuji Ishitani , Daisuke Kubota , Shinya Sasagawa
发明人： Hidekazu Miyairi , Tetsuji Ishitani , Daisuke Kubota , Shinya Sasagawa
IPC分类号： G02F1/1343 , C09K19/02 , G02F1/1362
CPC分类号： G02F1/134363 , C09K19/0275 , G02F1/1362
摘要： A horizontal electric field mode liquid crystal display device having a novel electrode structure, and a manufacturing method thereof are provided. The liquid crystal display device includes a first substrate having an insulating surface; a first conductive film and a second conductive film over the insulating surface; a first insulating film over the first conductive film; a second insulating film over the second conductive film; a second substrate facing the first substrate; and a liquid crystal layer positioned between the first substrate and the second substrate. Part of the first conductive film exists also on a side portion of the first insulating film, and part of the second conductive film exists also on a side portion of the second insulating film. The liquid crystal layer includes liquid crystal exhibiting a blue phase.
摘要翻译：提供具有新型电极结构的水平电场模式液晶显示装置及其制造方法。液晶显示装置包括具有绝缘面的第一基板; 绝缘表面上的第一导电膜和第二导电膜; 第一导电膜上的第一绝缘膜; 在第二导电膜上的第二绝缘膜; 面对所述第一基板的第二基板; 以及位于第一基板和第二基板之间的液晶层。第一导电膜的一部分也存在于第一绝缘膜的侧部，第二导电膜的一部分也存在于第二绝缘膜的侧部。液晶层包括呈蓝色相的液晶。

2. 发明申请

US20120229724A1 LIQUID CRYSTAL DISPLAY DEVICE AND MANUFACTURING METHOD OF LIQUID CRYSTAL DISPLAY DEVICE 有权
标题翻译：液晶显示装置的液晶显示装置及液晶显示装置的制造方法
公开(公告)号：US20120229724A1
公开(公告)日：2012-09-13
申请号：US13416077
申请日：2012-03-09
申请人： Hidekazu MIYAIRI , Tetsuji Ishitani , Daisuke Kubota , Shinya Sasagawa
发明人： Hidekazu MIYAIRI , Tetsuji Ishitani , Daisuke Kubota , Shinya Sasagawa
IPC分类号： G02F1/136 , B05D3/10 , G02F1/1333
CPC分类号： G02F1/134363 , C09K19/0275 , G02F1/1362
摘要： A horizontal electric field mode liquid crystal display device having a novel electrode structure, and a manufacturing method thereof are provided. The liquid crystal display device includes a first substrate having an insulating surface; a first conductive film and a second conductive film over the insulating surface; a first insulating film over the first conductive film; a second insulating film over the second conductive film; a second substrate facing the first substrate; and a liquid crystal layer positioned between the first substrate and the second substrate. Part of the first conductive film exists also on a side portion of the first insulating film, and part of the second conductive film exists also on a side portion of the second insulating film. The liquid crystal layer includes liquid crystal exhibiting a blue phase.
摘要翻译：提供具有新型电极结构的水平电场模式液晶显示装置及其制造方法。液晶显示装置包括具有绝缘面的第一基板; 绝缘表面上的第一导电膜和第二导电膜; 第一导电膜上的第一绝缘膜; 在第二导电膜上的第二绝缘膜; 面对所述第一基板的第二基板; 以及位于第一基板和第二基板之间的液晶层。第一导电膜的一部分也存在于第一绝缘膜的侧部，第二导电膜的一部分也存在于第二绝缘膜的侧部。液晶层包括呈蓝色相的液晶。

3. 发明授权

US08349671B2 Methods for manufacturing thin film transistor and display device 有权
公开(公告)号：US08349671B2
公开(公告)日：2013-01-08
申请号：US12230048
申请日：2008-08-22
申请人： Hidekazu Miyairi , Shinya Sasagawa , Akihiro Ishizuka
发明人： Hidekazu Miyairi , Shinya Sasagawa , Akihiro Ishizuka
IPC分类号： H01L21/336
CPC分类号： H01L29/6675 , H01L29/04 , H01L29/66765 , H01L29/78696 , H01L33/0058 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a method for manufacturing a highly reliable semiconductor device with a small amount of leakage current. In a method for manufacturing a thin film transistor, etching is conducted using a resist mask to form a back channel portion in the thin film transistor, the resist mask is removed, a part of the back channel is etched to remove etching residue and the like left over the back channel portion, whereby leakage current caused by the residue and the like can be reduced. The etching step of the back channel portion can be conducted by dry etching using non-bias.

4. 发明授权

US08829522B2 Thin film transistor 有权
标题翻译：薄膜晶体管
公开(公告)号：US08829522B2
公开(公告)日：2014-09-09
申请号：US12972994
申请日：2010-12-20
申请人： Hidekazu Miyairi , Shinya Sasagawa , Motomu Kurata
发明人： Hidekazu Miyairi , Shinya Sasagawa , Motomu Kurata
IPC分类号： H01L29/786
CPC分类号： H01L29/78678 , H01L29/66765 , H01L29/78618 , H01L29/78648
摘要： A thin film transistor having favorable electric characteristics with high productively is provided. The thin film transistor includes a gate insulating layer covering a gate electrode, a semiconductor layer in contact with the gate insulating layer, an impurity semiconductor layer which is in contact with part of the semiconductor layer and functions as a source region and a drain region, and a wiring in contact with the impurity semiconductor layer. The semiconductor layer includes a microcrystalline semiconductor region having a concave-convex shape, which is formed on the gate insulating layer side, and an amorphous semiconductor region in contact with the microcrystalline semiconductor region. A barrier region is provided between the semiconductor layer and the wiring.
摘要翻译：提供了具有良好的电特性的高效生产的薄膜晶体管。薄膜晶体管包括覆盖栅极的栅极绝缘层，与栅极绝缘层接触的半导体层，与半导体层的一部分接触并用作源极区域和漏极区域的杂质半导体层，以及与杂质半导体层接触的布线。半导体层包括形成在栅绝缘层侧的具有凹凸形状的微晶半导体区域和与微晶半导体区域接触的非晶半导体区域。在半导体层和布线之间设置有阻挡区域。

5. 发明申请

US20090061573A1 Methods for manufacturing thin film transistor and display device 有权
标题翻译：制造薄膜晶体管和显示装置的方法
公开(公告)号：US20090061573A1
公开(公告)日：2009-03-05
申请号：US12230048
申请日：2008-08-22
申请人： Hidekazu Miyairi , Shinya Sasagawa , Akihiro Ishizuka
发明人： Hidekazu Miyairi , Shinya Sasagawa , Akihiro Ishizuka
IPC分类号： H01L21/336
CPC分类号： H01L29/6675 , H01L29/04 , H01L29/66765 , H01L29/78696 , H01L33/0058 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a method for manufacturing a highly reliable semiconductor device with a small amount of leakage current. In a method for manufacturing a thin film transistor, etching is conducted using a resist mask to form a back channel portion in the thin film transistor, the resist mask is removed, a part of the back channel is etched to remove etching residue and the like left over the back channel portion, whereby leakage current caused by the residue and the like can be reduced. The etching step of the back channel portion can be conducted by dry etching using non-bias.
摘要翻译：本发明提供了一种制造具有少量漏电流的高可靠性半导体器件的方法。在制造薄膜晶体管的方法中，使用抗蚀剂掩模进行蚀刻以在薄膜晶体管中形成背沟道部分，去除抗蚀剂掩模，蚀刻一部分后沟道以除去蚀刻残留物等留在后通道部分，由此可以减少由残渣等引起的泄漏电流。背沟道部分的蚀刻步骤可以通过使用非偏压的干蚀刻来进行。

6. 发明授权

US09230826B2 Etching method using mixed gas and method for manufacturing semiconductor device 有权
标题翻译：使用混合气体的蚀刻方法和制造半导体器件的方法
公开(公告)号：US09230826B2
公开(公告)日：2016-01-05
申请号：US13213130
申请日：2011-08-19
申请人： Shinya Sasagawa , Hiroshi Fujiki , Shinobu Furukawa , Hidekazu Miyairi
发明人： Shinya Sasagawa , Hiroshi Fujiki , Shinobu Furukawa , Hidekazu Miyairi
IPC分类号： H01L21/20 , H01L21/3213 , H01L29/66 , H01L29/786
CPC分类号： H01L21/32137 , H01L29/6675 , H01L29/66765 , H01L29/78663 , H01L29/78669 , H01L29/78672 , H01L29/78678 , H01L29/78687
摘要： A method for etching is provided in which the etching selectivity of an amorphous semiconductor film to a crystalline semiconductor film is high. Part of a stacked semiconductor film in which an amorphous semiconductor film is provided on a crystalline semiconductor film is etched using a mixed gas of a Br-based gas, a F-based gas, and an oxygen gas, so that part of the crystalline semiconductor film provided in the stacked semiconductor film is exposed. Reduction in the film thickness of the exposed portion can be suppressed by performing the etching in such a manner. Moreover, when etching for forming a back channel portion of a thin film transistor is performed with the method for etching, favorable electric characteristics of the thin film transistor can be obtained. An insulating layer is preferably provided over the thin film transistor.
摘要翻译：提供了一种用于蚀刻的方法，其中非晶半导体膜对结晶半导体膜的蚀刻选择性高。使用Br基气体，F系气体和氧气的混合气体蚀刻在结晶半导体膜上设置非晶半导体膜的层叠半导体膜的一部分，使部分结晶半导体提供在堆叠的半导体膜中的膜被暴露。可以通过以这种方式进行蚀刻来抑制曝光部分的膜厚度的降低。此外，当利用蚀刻方法进行用于形成薄膜晶体管的背沟道部分的蚀刻时，可以获得薄膜晶体管的良好的电特性。绝缘层优选设置在薄膜晶体管的上方。

7. 发明授权

US08436403B2 Semiconductor device including transistor provided with sidewall and electronic appliance 有权
标题翻译：包括设置有侧壁和电子设备的晶体管的半导体器件
公开(公告)号：US08436403B2
公开(公告)日：2013-05-07
申请号：US13014081
申请日：2011-01-26
申请人： Shunpei Yamazaki , Hiromichi Godo , Hideomi Suzawa , Shinya Sasagawa , Motomu Kurata , Mayumi Mikami
发明人： Shunpei Yamazaki , Hiromichi Godo , Hideomi Suzawa , Shinya Sasagawa , Motomu Kurata , Mayumi Mikami
IPC分类号： H01L21/84
CPC分类号： H01L29/7869 , H01L29/41733 , H01L29/45 , H01L29/66969 , Y10T428/24421
摘要： One object is to provide a semiconductor device that includes an oxide semiconductor and is reduced in size with favorable characteristics maintained. The semiconductor device includes an oxide semiconductor layer, a source electrode and a drain electrode in contact with the oxide semiconductor layer, a gate electrode overlapping with the oxide semiconductor layer; and a gate insulating layer between the oxide semiconductor layer and the gate electrode. The source electrode or the drain electrode includes a first conductive layer and a second conductive layer having a region extended in a channel length direction from an end face of the first conductive layer. The sidewall insulating layer has a length of a bottom surface in the channel length direction smaller than a length in the channel length direction of the extended region of the second conductive layer and is provided over the extended region.
摘要翻译：一个目的是提供一种包括氧化物半导体的半导体器件，并且尺寸减小，并保持良好的特性。半导体器件包括与氧化物半导体层接触的氧化物半导体层，源电极和漏电极，与氧化物半导体层重叠的栅电极; 以及在氧化物半导体层和栅电极之间的栅极绝缘层。源电极或漏极包括第一导电层和具有从第一导电层的端面在沟道长度方向上延伸的区域的第二导电层。侧壁绝缘层的沟道长度方向的底面的长度小于第二导电层的延伸区域的沟道长度方向的长度，并且设置在延伸区域上。

8. 发明授权

US08236635B2 Method for manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08236635B2
公开(公告)日：2012-08-07
申请号：US12582074
申请日：2009-10-20
申请人： Hideomi Suzawa , Shinya Sasagawa , Taiga Muraoka
发明人： Hideomi Suzawa , Shinya Sasagawa , Taiga Muraoka
IPC分类号： H01L21/00 , H01L21/336 , H01L21/8234 , H01L21/84 , H01L21/20
CPC分类号： H01L27/1288 , H01L27/1214 , H01L27/1225 , H01L29/7869
摘要： In a method for manufacturing a semiconductor device including a channel-etched inverted-staggered thin film transistor, an oxide semiconductor film and a conductive film are etched using a mask layer formed with the use of a multi-tone mask which is a light-exposure mask through which light is transmitted so as to have a plurality of intensities. The etching step is performed by dry etching in which an etching gas is used.
摘要翻译：在制造包括通道蚀刻反交错薄膜晶体管的半导体器件的方法中，使用使用作为曝光的多色调掩模形成的掩模层来蚀刻氧化物半导体膜和导电膜光透过该掩模以具有多个强度。蚀刻步骤通过使用蚀刻气体的干蚀刻进行。

9. 发明授权

US08207025B2 Manufacturing method of semiconductor device 有权
标题翻译：半导体器件的制造方法
公开(公告)号：US08207025B2
公开(公告)日：2012-06-26
申请号：US13078020
申请日：2011-04-01
申请人： Hideomi Suzawa , Shinya Sasagawa
发明人： Hideomi Suzawa , Shinya Sasagawa
IPC分类号： H01L21/336
CPC分类号： H01L29/78636 , G11C16/0433 , H01L27/0688 , H01L27/11521 , H01L27/11551 , H01L27/1156 , H01L27/1214 , H01L27/1225 , H01L27/1288 , H01L29/66969 , H01L29/7869
摘要： In an embodiment, an insulating film is formed over a flat surface; a mask is formed over the insulating film; a slimming process is performed on the mask; an etching process is performed on the insulating film using the mask; a conductive film covering the insulating film is formed; a polishing process is performed on the conductive film and the insulating film, so that the conductive film and the insulating film have equal thicknesses; the conductive film is etched, so that a source electrode and a drain electrode which are thinner than the conductive film are formed; an oxide semiconductor film is formed in contact with the insulating film, the source electrode, and the drain electrode; a gate insulating film covering the oxide semiconductor film is formed; and a gate electrode is formed in a region which is over the gate insulating film and overlaps with the insulating film.
摘要翻译：在一个实施例中，在平坦表面上形成绝缘膜; 在绝缘膜上形成掩模; 在面罩上进行减肥过程; 使用掩模对绝缘膜进行蚀刻处理; 形成覆盖绝缘膜的导电膜; 对导电膜和绝缘膜进行抛光处理，使得导电膜和绝缘膜具有相等的厚度; 蚀刻导电膜，形成比导电膜薄的源电极和漏电极; 形成与绝缘膜，源电极和漏电极接触的氧化物半导体膜; 形成覆盖氧化物半导体膜的栅极绝缘膜; 并且栅电极形成在栅极绝缘膜上并与绝缘膜重叠的区域中。

10. 发明授权

US07998801B2 Manufacturing method of thin film transistor having altered semiconductor layer 有权
标题翻译：具有改变的半导体层的薄膜晶体管的制造方法
公开(公告)号：US07998801B2
公开(公告)日：2011-08-16
申请号：US12424563
申请日：2009-04-16
申请人： Shinya Sasagawa , Motomu Kurata , Sho Osada
发明人： Shinya Sasagawa , Motomu Kurata , Sho Osada
IPC分类号： H01L21/00 , H01L21/302
CPC分类号： H01L27/1288 , H01L27/1214 , H01L29/04 , H01L29/40 , H01L29/41733 , H01L29/66765 , H01L29/78669 , H01L29/78678 , H01L29/78696
摘要： Decrease of the off-state current, increase of the on-state current, and reduction of variations of electrical characteristics. A method for manufacturing a channel-etched inversed staggered thin film transistor includes the following steps: removing, by first dry-etching, a part of a semiconductor layer including an impurity element which imparts one conductivity type, which is exposed from the source and drain electrodes, and partially a part of an amorphous semiconductor layer just below and in contact with the part of the semiconductor layer; removing, by second dry-etching, partially the part of the amorphous semiconductor layer which is exposed by the first dry-etching; and performing plasma treatment on the surface of the part of the amorphous semiconductor layer which is exposed by the second dry-etching so that an altered layer is formed.
摘要翻译：关闭状态电流的减小，导通电流的增加以及电特性变化的减小。用于制造通道蚀刻反向交错薄膜晶体管的方法包括以下步骤：通过首先干蚀刻除去包括从源极和漏极暴露的赋予一种导电类型的杂质元素的半导体层的一部分电极，以及半导体层的正下方并与半导体层的一部分接触的部分非晶半导体层的一部分; 通过第二干法蚀刻部分地除去通过第一干法蚀刻暴露的部分非晶半导体层; 并且通过第二干蚀刻曝光的非晶半导体层的部分的表面进行等离子体处理，从而形成改变的层。

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