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1. 发明授权

US08436403B2 Semiconductor device including transistor provided with sidewall and electronic appliance 有权
标题翻译：包括设置有侧壁和电子设备的晶体管的半导体器件
公开(公告)号：US08436403B2
公开(公告)日：2013-05-07
申请号：US13014081
申请日：2011-01-26
申请人： Shunpei Yamazaki , Hiromichi Godo , Hideomi Suzawa , Shinya Sasagawa , Motomu Kurata , Mayumi Mikami
发明人： Shunpei Yamazaki , Hiromichi Godo , Hideomi Suzawa , Shinya Sasagawa , Motomu Kurata , Mayumi Mikami
IPC分类号： H01L21/84
CPC分类号： H01L29/7869 , H01L29/41733 , H01L29/45 , H01L29/66969 , Y10T428/24421
摘要： One object is to provide a semiconductor device that includes an oxide semiconductor and is reduced in size with favorable characteristics maintained. The semiconductor device includes an oxide semiconductor layer, a source electrode and a drain electrode in contact with the oxide semiconductor layer, a gate electrode overlapping with the oxide semiconductor layer; and a gate insulating layer between the oxide semiconductor layer and the gate electrode. The source electrode or the drain electrode includes a first conductive layer and a second conductive layer having a region extended in a channel length direction from an end face of the first conductive layer. The sidewall insulating layer has a length of a bottom surface in the channel length direction smaller than a length in the channel length direction of the extended region of the second conductive layer and is provided over the extended region.
摘要翻译：一个目的是提供一种包括氧化物半导体的半导体器件，并且尺寸减小，并保持良好的特性。半导体器件包括与氧化物半导体层接触的氧化物半导体层，源电极和漏电极，与氧化物半导体层重叠的栅电极; 以及在氧化物半导体层和栅电极之间的栅极绝缘层。源电极或漏极包括第一导电层和具有从第一导电层的端面在沟道长度方向上延伸的区域的第二导电层。侧壁绝缘层的沟道长度方向的底面的长度小于第二导电层的延伸区域的沟道长度方向的长度，并且设置在延伸区域上。

2. 发明授权

US08492840B2 Semiconductor device having an oxide semiconductor layer 有权
标题翻译：具有氧化物半导体层的半导体器件
公开(公告)号：US08492840B2
公开(公告)日：2013-07-23
申请号：US13008285
申请日：2011-01-18
申请人： Shunpei Yamazaki , Hiromichi Godo , Hideomi Suzawa , Shinya Sasagawa , Motomu Kurata , Mayumi Mikami
发明人： Shunpei Yamazaki , Hiromichi Godo , Hideomi Suzawa , Shinya Sasagawa , Motomu Kurata , Mayumi Mikami
IPC分类号： H01L27/12
CPC分类号： H01L29/7869
摘要： An object is to provide a semiconductor device including an oxide semiconductor, which maintains favorable characteristics and achieves miniaturization. The semiconductor device includes an oxide semiconductor layer, a source electrode and a drain electrode in contact with the oxide semiconductor layer, a gate electrode overlapping with the oxide semiconductor layer, and a gate insulating layer provided between the oxide semiconductor layer and the gate electrode, in which the source electrode and the drain electrode each include a first conductive layer, and a second conductive layer having a region which extends in a channel length direction from an end portion of the first conductive layer.
摘要翻译：本发明的目的是提供一种包含氧化物半导体的半导体器件，其保持有利的特性并实现小型化。半导体器件包括与氧化物半导体层接触的氧化物半导体层，源极和漏电极，与氧化物半导体层重叠的栅电极，以及设置在氧化物半导体层和栅电极之间的栅极绝缘层，其中源电极和漏极各自包括第一导电层，以及具有从第一导电层的端部在沟道长度方向上延伸的区域的第二导电层。

3. 发明申请

US20110147744A1 THIN FILM TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：薄膜晶体管及其制造方法
公开(公告)号：US20110147744A1
公开(公告)日：2011-06-23
申请号：US12972859
申请日：2010-12-20
申请人： Yasuhiro Jinbo , Hideomi Suzawa , Hiromichi Godo , Shinya Sasagawa
发明人： Yasuhiro Jinbo , Hideomi Suzawa , Hiromichi Godo , Shinya Sasagawa
IPC分类号： H01L29/786
CPC分类号： H01L29/78696 , H01L29/66765 , H01L29/786 , H01L29/78663
摘要： An object is to increase the on-state current of a thin film transistor. A solution is to provide a projection in a back-channel portion of the thin film transistor. The projection is provided so as to be off a tangent in the back-channel portion between a source or a drain and a channel formation region. With the projection, a portion where electric charge is trapped and a path of the on-state current can be apart from each other, so that the on-state current can be increased. The shape of a side surface of the back-channel portion may be curved, or may be represented as straight lines in a cross section. Further, a method for forming such a shape by performing one etching step is provided.
摘要翻译：目的是增加薄膜晶体管的导通电流。解决方案是在薄膜晶体管的后通道部分中提供投影。突起被设置成在源极或漏极之间的后部沟道部分和沟道形成区域之间切断切线。通过投影，电荷被捕获的部分和导通状态电流的路径可以彼此分开，从而可以增加导通电流。背沟道部分的侧表面的形状可以是弯曲的，或者可以在横截面中表示为直线。此外，提供了通过执行一个蚀刻步骤来形成这种形状的方法。

4. 发明授权

US09202929B2 Thin film transistor and method for manufacturing the same 有权
标题翻译：薄膜晶体管及其制造方法
公开(公告)号：US09202929B2
公开(公告)日：2015-12-01
申请号：US12972859
申请日：2010-12-20
申请人： Yasuhiro Jinbo , Hideomi Suzawa , Hiromichi Godo , Shinya Sasagawa
发明人： Yasuhiro Jinbo , Hideomi Suzawa , Hiromichi Godo , Shinya Sasagawa
IPC分类号： H01L29/786 , H01L29/66
CPC分类号： H01L29/78696 , H01L29/66765 , H01L29/786 , H01L29/78663
摘要： An object is to increase the on-state current of a thin film transistor. A solution is to provide a projection in a back-channel portion of the thin film transistor. The projection is provided so as to be off a tangent in the back-channel portion between a source or a drain and a channel formation region. With the projection, a portion where electric charge is trapped and a path of the on-state current can be apart from each other, so that the on-state current can be increased. The shape of a side surface of the back-channel portion may be curved, or may be represented as straight lines in a cross section. Further, a method for forming such a shape by performing one etching step is provided.
摘要翻译：目的是增加薄膜晶体管的导通电流。解决方案是在薄膜晶体管的后通道部分中提供投影。突起被设置成在源极或漏极之间的后部沟道部分和沟道形成区域之间切断切线。通过投影，电荷被捕获的部分和导通状态电流的路径可以彼此分开，从而可以增加导通电流。背沟道部分的侧表面的形状可以是弯曲的，或者可以在横截面中表示为直线。此外，提供了通过执行一个蚀刻步骤来形成这种形状的方法。

5. 发明授权

US08624321B2 Thin film transistor including a microcrystalline semiconductor layer and amorphous semiconductor layer and display device including the same 有权
标题翻译：包括微晶半导体层和非晶半导体层的薄膜晶体管以及包括其的显示装置
公开(公告)号：US08624321B2
公开(公告)日：2014-01-07
申请号：US12398295
申请日：2009-03-05
申请人： Shunpei Yamazaki , Yoshiyuki Kurokawa , Hiromichi Godo , Hidekazu Miyairi
发明人： Shunpei Yamazaki , Yoshiyuki Kurokawa , Hiromichi Godo , Hidekazu Miyairi
IPC分类号： H01L23/62
CPC分类号： H01L29/78696 , H01L29/04 , H01L29/66765
摘要： A thin film transistor is provided, which includes a gate insulating layer covering a gate electrode, a microcrystalline semiconductor layer provided over the gate insulating layer, an amorphous semiconductor layer overlapping the microcrystalline semiconductor layer and the gate insulating layer, and a pair of impurity semiconductor layers which are provided over the amorphous semiconductor layer and to which an impurity element imparting one conductivity type is added to form a source region and a drain region. The gate insulating layer has a step adjacent to a portion in contact with an end portion of the microcrystalline semiconductor layer. A second thickness of the gate insulating layer in a portion outside the microcrystalline semiconductor layer is smaller than a first thickness thereof in a portion in contact with the microcrystalline semiconductor layer.
摘要翻译：提供一种薄膜晶体管，其包括覆盖栅极的栅极绝缘层，设置在栅极绝缘层上的微晶半导体层，与微晶半导体层和栅极绝缘层重叠的非晶半导体层，以及一对杂质半导体提供在非晶半导体层上并且添加赋予一种导电类型的杂质元素以形成源区和漏区的层。栅极绝缘层具有与微晶半导体层的端部接触的部分相邻的台阶。在与微晶半导体层接触的部分中，微晶半导体层外部的栅极绝缘层的第二厚度小于其第一厚度。

6. 发明授权

US08253138B2 Thin film transistor and display device having the thin film transistor 有权
标题翻译：薄膜晶体管和具有薄膜晶体管的显示装置
公开(公告)号：US08253138B2
公开(公告)日：2012-08-28
申请号：US12263702
申请日：2008-11-03
申请人： Shunpei Yamazaki , Satoshi Kobayashi , Yoshiyuki Kurokawa , Hiromichi Godo
发明人： Shunpei Yamazaki , Satoshi Kobayashi , Yoshiyuki Kurokawa , Hiromichi Godo
IPC分类号： H01L29/04
CPC分类号： H01L29/04 , H01L21/02532 , H01L21/0262 , H01L29/41733 , H01L29/66765 , H01L29/78696
摘要： A thin film transistor includes a gate electrode, a gate insulating layer covering the gate electrode, a microcrystalline semiconductor layer over the gate insulating layer, an amorphous semiconductor layer over the microcrystalline semiconductor layer, source and drain regions over the amorphous semiconductor layer, source and drain electrodes in contact with and over the source and drain regions, and a part of the amorphous semiconductor layer overlapping with the source and drain regions is thicker than a part of the amorphous semiconductor layer overlapping with a channel formation region. The side face of the source and drain regions and the side face of the amorphous semiconductor form a tapered shape together with an outmost surface of the amorphous semiconductor layer. The taper angle of the tapered shape is such an angle that decrease electric field concentration around a junction portion between the source and drain regions and the amorphous semiconductor layer.
摘要翻译：薄膜晶体管包括栅电极，覆盖栅电极的栅极绝缘层，栅极绝缘层上的微晶半导体层，微晶半导体层上的非晶半导体层，非晶半导体层上的源极和漏极区，源极和与源极和漏极区域接触和超过的漏极电极，与源极和漏极区域重叠的部分非晶半导体层比与沟道形成区域重叠的非晶半导体层的一部分更厚。源极和漏极区域的侧面和非晶半导体的侧面与非晶半导体层的最外表面一起形成锥形形状。锥形形状的锥角是减小源极和漏极区域与非晶半导体层之间的接合部周围的电场浓度的角度。

7. 发明申请

US20110278571A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20110278571A1
公开(公告)日：2011-11-17
申请号：US13101644
申请日：2011-05-05
申请人： Shunpei Yamazaki , Kiyoshi Kato , Yutaka Shionoiri , Yusuke Sekine , Kazuma Furutani , Hiromichi Godo
发明人： Shunpei Yamazaki , Kiyoshi Kato , Yutaka Shionoiri , Yusuke Sekine , Kazuma Furutani , Hiromichi Godo
IPC分类号： H01L29/786
CPC分类号： H01L29/7869 , G11C16/0433 , G11C16/26 , H01L27/11521 , H01L27/1156 , H01L27/1225 , H01L28/40 , H01L29/41733 , H01L29/78621
摘要： A semiconductor device including a first transistor and a second transistor and a capacitor which are over the first transistor is provided. A semiconductor layer of the second transistor includes an offset region. In the second transistor provided with an offset region, the off-state current of the second transistor can be reduced. Thus, a semiconductor device which can hold data for a long time can be provided.
摘要翻译：提供了包括在第一晶体管之上的第一晶体管和第二晶体管和电容器的半导体器件。第二晶体管的半导体层包括偏移区域。在设置有偏移区域的第二晶体管中，可以减小第二晶体管的截止电流。因此，可以提供能够长时间保持数据的半导体器件。

8. 发明申请

US20110233542A1 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20110233542A1
公开(公告)日：2011-09-29
申请号：US13071845
申请日：2011-03-25
申请人： Shunpei Yamazaki , Hiromichi Godo
发明人： Shunpei Yamazaki , Hiromichi Godo
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L29/7869 , H01L27/1225
摘要： In a transistor including an oxide semiconductor film, a metal oxide film which has a function of preventing electrification and covers a source electrode and a drain electrode is formed in contact with the oxide semiconductor film, and then, heat treatment is performed. Through the heat treatment, impurities such as hydrogen, moisture, a hydroxyl group, or hydride are intentionally removed from the oxide semiconductor film, whereby the oxide semiconductor film is highly purified. By providing the metal oxide film, generation of a parasitic channel on the back channel side of the oxide semiconductor film in the transistor can be prevented.
摘要翻译：在包括氧化物半导体膜的晶体管中，形成与氧化物半导体膜接触的具有防止起电并且覆盖源电极和漏电极的功能的金属氧化物膜，然后进行热处理。通过热处理，有意地从氧化物半导体膜去除氢，水分，羟基或氢化物等杂质，由此氧化物半导体膜被高度纯化。通过设置金属氧化物膜，可以防止在晶体管中的氧化物半导体膜的背面通道侧产生寄生沟道。

9. 发明申请

US20110127525A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20110127525A1
公开(公告)日：2011-06-02
申请号：US12954222
申请日：2010-11-24
申请人： Shunpei Yamazaki , Hiromichi Godo , Daisuke Kawae
发明人： Shunpei Yamazaki , Hiromichi Godo , Daisuke Kawae
IPC分类号： H01L29/786
CPC分类号： H01L29/78693 , H01L29/41733 , H01L29/42384 , H01L29/4908 , H01L29/66969 , H01L29/7869 , H01L29/78696
摘要： An intrinsic or substantially intrinsic semiconductor, which has been subjected to a step of dehydration or dehydrogenation and a step of adding oxygen so that the carrier concentration is less than 1×1012/cm3 is used for an oxide semiconductor layer of an insulated gate transistor, in which a channel region is formed. The length of the channel formed in the oxide semiconductor layer is set to 0.2 μm to 3.0 μm an inclusive and the thicknesses of the oxide semiconductor layer and the gate insulating layer are set to 15 nm to 30 nm inclusive and 20 nm to 50 nm inclusive, respectively, or 15 nm to 100 nm inclusive and 10 nm to 20 nm inclusive, respectively. Consequently, a short-channel effect can be suppressed, and the amount of change in threshold voltage can be less than 0.5 V in the range of the above channel lengths.
摘要翻译：对于绝缘栅极晶体管的氧化物半导体层，使用已进行脱水或脱氢工序的本征或本质上本征的半导体，以及添加氧以使载流子浓度小于1×10 12 / cm 3的步骤，其中形成沟道区。将形成在氧化物半导体层中的沟道的长度设定为0.2μm〜3.0μm，氧化物半导体层和栅极绝缘层的厚度为15nm〜30nm，包括20nm〜50nm ，或分别为15nm〜100nm，10nm〜20nm。因此，可以抑制短沟道效应，并且在上述通道长度的范围内阈值电压的变化量可以小于0.5V。

10. 发明申请

US20090194803A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20090194803A1
公开(公告)日：2009-08-06
申请号：US12362462
申请日：2009-01-29
申请人： Shunpei Yamazaki , Atsuo Isobe , Tetsuji Yamaguchi , Hiromichi Godo
发明人： Shunpei Yamazaki , Atsuo Isobe , Tetsuji Yamaguchi , Hiromichi Godo
IPC分类号： H01L29/788 , H01L23/04
CPC分类号： H01L27/127 , H01L24/32 , H01L24/73 , H01L27/11526 , H01L27/11546 , H01L27/1214 , H01L27/13 , H01L29/78621 , H01L29/78624 , H01L29/78627 , H01L2029/7863 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2224/73265 , H01L2224/83385 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/0103 , H01L2924/01032 , H01L2924/01033 , H01L2924/0104 , H01L2924/01042 , H01L2924/01045 , H01L2924/01046 , H01L2924/01047 , H01L2924/01056 , H01L2924/0106 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/0132 , H01L2924/07811 , H01L2924/10253 , H01L2924/10329 , H01L2924/12042 , H01L2924/13091 , H01L2924/14 , H01L2924/15311 , H01L2924/15787 , H01L2924/15788 , H01L2924/181 , H01L2924/19041 , H01L2924/3025 , H01L2924/00014 , H01L2924/00012 , H01L2924/00 , H01L2924/01014
摘要： The present invention provides a semiconductor device capable of being mass-produced and a manufacturing method of the semiconductor device. The present invention also provides a semiconductor device using an extreme thin integrated circuit and a manufacturing method of the semiconductor device. Further, the present invention provides a low power consumption semiconductor device and a manufacturing method of the semiconductor device. According to one aspect of the present invention, a semiconductor device that has a semiconductor nonvolatile memory element transistor over an insulating surface in which a floating gate electrode of the memory transistor is formed by a plurality of conductive particles or semiconductor particles is provided.
摘要翻译：本发明提供一种能够大规模生产的半导体器件和该半导体器件的制造方法。本发明还提供了使用极薄集成电路的半导体器件和半导体器件的制造方法。此外，本发明提供一种半导体器件的低功耗半导体器件和制造方法。根据本发明的一个方面，提供了一种在绝缘表面上具有半导体非易失性存储元件晶体管的半导体器件，其中存储晶体管的浮置栅电极由多个导电粒子或半导体粒子形成。

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