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1. 发明申请

US20120223322A1 III-Nitride Transistor Stacked with Diode in a Package 有权
标题翻译： III型氮化物晶体管与二极管堆叠在一起
公开(公告)号：US20120223322A1
公开(公告)日：2012-09-06
申请号：US13053646
申请日：2011-03-22
申请人： Heny Lin , Jason Zhang , Alberto Guerra
发明人： Heny Lin , Jason Zhang , Alberto Guerra
IPC分类号： H01L29/20
CPC分类号： H01L27/0727 , H01L23/49562 , H01L24/29 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/065 , H01L25/18 , H01L27/0605 , H01L29/2003 , H01L29/778 , H01L2224/2919 , H01L2224/32245 , H01L2224/45014 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48147 , H01L2224/48247 , H01L2224/48257 , H01L2224/49111 , H01L2224/73265 , H01L2924/01013 , H01L2924/01014 , H01L2924/10253 , H01L2924/10323 , H01L2924/1033 , H01L2924/10334 , H01L2924/10344 , H01L2924/10346 , H01L2924/12032 , H01L2924/12036 , H01L2924/12041 , H01L2924/1306 , H01L2924/19104 , H01L2924/30107 , H01L2924/00 , H01L2924/00014
摘要： One exemplary disclosed embodiment comprises a two-terminal stacked-die package including a diode, such as a silicon diode, stacked atop a III-nitride transistor, such that a cathode of the diode resides on and is electrically coupled to a source of the III-nitride transistor. A first terminal of the package is coupled to a drain of the III-nitride transistor, and a second terminal of the package is coupled to an anode of the diode. In this manner, devices such as cascoded rectifiers may be packaged in a stacked-die form, resulting in reduced parasitic inductance and resistance, improved thermal dissipation, smaller form factor, and lower manufacturing cost compared to conventional packages.
摘要翻译：一个示例性的公开的实施例包括二端子堆叠管芯封装，其包括二极管，例如硅二极管，堆叠在III族氮化物晶体管的顶部，使得二极管的阴极位于III的源极上并与其电耦合氮化晶体管。封装的第一端子耦合到III族氮化物晶体管的漏极，并且封装的第二端子耦合到二极管的阳极。以这种方式，诸如级联整流器的器件可以以堆叠的管芯形式封装，与常规封装相比，导致减小的寄生电感和电阻，改善的散热，更小的外形尺寸以及更低的制造成本。

2. 发明授权

US08963338B2 III-nitride transistor stacked with diode in a package 有权
标题翻译：在封装中堆叠二极管的III族氮化物晶体管
公开(公告)号：US08963338B2
公开(公告)日：2015-02-24
申请号：US13053646
申请日：2011-03-22
申请人： Heny Lin , Jason Zhang , Alberto Guerra
发明人： Heny Lin , Jason Zhang , Alberto Guerra
IPC分类号： H01L23/48 , H01L23/495 , H01L23/58 , H01L25/18 , H01L23/00 , H01L29/778 , H01L29/20
CPC分类号： H01L27/0727 , H01L23/49562 , H01L24/29 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/065 , H01L25/18 , H01L27/0605 , H01L29/2003 , H01L29/778 , H01L2224/2919 , H01L2224/32245 , H01L2224/45014 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48147 , H01L2224/48247 , H01L2224/48257 , H01L2224/49111 , H01L2224/73265 , H01L2924/01013 , H01L2924/01014 , H01L2924/10253 , H01L2924/10323 , H01L2924/1033 , H01L2924/10334 , H01L2924/10344 , H01L2924/10346 , H01L2924/12032 , H01L2924/12036 , H01L2924/12041 , H01L2924/1306 , H01L2924/19104 , H01L2924/30107 , H01L2924/00 , H01L2924/00014
摘要： One exemplary disclosed embodiment comprises a two-terminal stacked-die package including a diode, such as a silicon diode, stacked atop a III-nitride transistor, such that a cathode of the diode resides on and is electrically coupled to a source of the III-nitride transistor. A first terminal of the package is coupled to a drain of the III-nitride transistor, and a second terminal of the package is coupled to an anode of the diode. In this manner, devices such as cascoded rectifiers may be packaged in a stacked-die form, resulting in reduced parasitic inductance and resistance, improved thermal dissipation, smaller form factor, and lower manufacturing cost compared to conventional packages.
摘要翻译：一个示例性的公开的实施例包括二端子堆叠管芯封装，其包括二极管，例如硅二极管，堆叠在III族氮化物晶体管的顶部，使得二极管的阴极位于III的源极上并与其电耦合氮化晶体管。封装的第一端子耦合到III族氮化物晶体管的漏极，并且封装的第二端子耦合到二极管的阳极。以这种方式，诸如级联整流器的器件可以以堆叠的管芯形式封装，与常规封装相比，导致减小的寄生电感和电阻，改善的散热，更小的外形尺寸以及更低的制造成本。

3. 发明申请

US20120223321A1 III-Nitride Transistor Stacked with FET in a Package 有权
标题翻译： III型氮化物晶体管与封装中的FET堆叠
公开(公告)号：US20120223321A1
公开(公告)日：2012-09-06
申请号：US13053556
申请日：2011-03-22
申请人： Heny Lin , Jason Zhang , Alberto Guerra
发明人： Heny Lin , Jason Zhang , Alberto Guerra
IPC分类号： H01L29/12
CPC分类号： H01L25/074 , H01L23/49562 , H01L23/49575 , H01L24/29 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/69 , H01L24/72 , H01L24/73 , H01L29/16 , H01L29/2003 , H01L29/772 , H01L29/778 , H01L2224/0603 , H01L2224/2919 , H01L2224/32145 , H01L2224/32245 , H01L2224/45014 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48145 , H01L2224/48247 , H01L2224/49111 , H01L2224/73265 , H01L2225/06506 , H01L2225/0651 , H01L2225/06568 , H01L2924/00014 , H01L2924/01013 , H01L2924/01014 , H01L2924/10253 , H01L2924/10323 , H01L2924/1033 , H01L2924/10334 , H01L2924/10344 , H01L2924/10346 , H01L2924/1306 , H01L2924/15787 , H01L2924/30107 , H01L2924/00 , H01L2924/00012 , H01L2224/85399 , H01L2224/05599
摘要： One exemplary disclosed embodiment comprises a three-terminal stacked-die package including a field effect transistor (FET), such as a silicon FET, stacked atop a III-nitride transistor, such that a drain of the FET resides on and is electrically coupled to a source of the III-nitride transistor. A first terminal of the package is coupled to a gate of the FET, a second terminal of the package is coupled to a drain of the III-nitride transistor. A third terminal of the package is coupled to a source of the FET. In this manner, devices such as cascoded switches may be packaged in a stacked-die form, resulting in reduced parasitic inductance and resistance, improved thermal dissipation, smaller form factor, and lower manufacturing cost compared to conventional packages.
摘要翻译：一个示例性的公开的实施例包括三端堆叠管芯封装，其包括堆叠在III族氮化物晶体管顶部的场效应晶体管（FET），例如硅FET，使得FET的漏极驻留在电耦合到 III族氮化物晶体管的源极。封装的第一端子耦合到FET的栅极，封装的第二端子耦合到III族氮化物晶体管的漏极。封装的第三端子耦合到FET的源极。以这种方式，诸如级联开关的器件可以以堆叠的管芯形式被封装，从而与常规封装相比，减小了寄生电感和电阻，改善的散热，更小的外形尺寸和更低的制造成本。

4. 发明授权

US08847408B2 III-nitride transistor stacked with FET in a package 有权
标题翻译：在封装中堆叠有FET的III族氮化物晶体管
公开(公告)号：US08847408B2
公开(公告)日：2014-09-30
申请号：US13053556
申请日：2011-03-22
申请人： Heny Lin , Jason Zhang , Alberto Guerra
发明人： Heny Lin , Jason Zhang , Alberto Guerra
IPC分类号： H01L25/18 , H01L23/495 , H01L23/00 , H01L29/20 , H01L29/778
CPC分类号： H01L25/074 , H01L23/49562 , H01L23/49575 , H01L24/29 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/69 , H01L24/72 , H01L24/73 , H01L29/16 , H01L29/2003 , H01L29/772 , H01L29/778 , H01L2224/0603 , H01L2224/2919 , H01L2224/32145 , H01L2224/32245 , H01L2224/45014 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48145 , H01L2224/48247 , H01L2224/49111 , H01L2224/73265 , H01L2225/06506 , H01L2225/0651 , H01L2225/06568 , H01L2924/00014 , H01L2924/01013 , H01L2924/01014 , H01L2924/10253 , H01L2924/10323 , H01L2924/1033 , H01L2924/10334 , H01L2924/10344 , H01L2924/10346 , H01L2924/1306 , H01L2924/15787 , H01L2924/30107 , H01L2924/00 , H01L2924/00012 , H01L2224/85399 , H01L2224/05599
摘要： One exemplary disclosed embodiment comprises a three-terminal stacked-die package including a field effect transistor (FET), such as a silicon FET, stacked atop a III-nitride transistor, such that a drain of the FET resides on and is electrically coupled to a source of the III-nitride transistor. A first terminal of the package is coupled to a gate of the FET, a second terminal of the package is coupled to a drain of the III-nitride transistor. A third terminal of the package is coupled to a source of the FET. In this manner, devices such as cascoded switches may be packaged in a stacked-die form, resulting in reduced parasitic inductance and resistance, improved thermal dissipation, smaller form factor, and lower manufacturing cost compared to conventional packages.
摘要翻译：一个示例性的公开的实施例包括三端堆叠管芯封装，其包括堆叠在III族氮化物晶体管顶部的场效应晶体管（FET），例如硅FET，使得FET的漏极驻留在电耦合到 III族氮化物晶体管的源极。封装的第一端子耦合到FET的栅极，封装的第二端子耦合到III族氮化物晶体管的漏极。封装的第三端子耦合到FET的源极。以这种方式，诸如级联开关的器件可以以堆叠的管芯形式被封装，从而与常规封装相比，减小了寄生电感和电阻，改善的散热，更小的外形尺寸和更低的制造成本。

5. 发明授权

US09362905B2 Composite semiconductor device with turn-on prevention control 有权
标题翻译：具有开启防止控制的复合半导体器件
公开(公告)号：US09362905B2
公开(公告)日：2016-06-07
申请号：US13415779
申请日：2012-03-08
申请人： Jason Zhang
发明人： Jason Zhang
IPC分类号： H01L29/30 , H03K17/30 , H03K17/10 , H03K17/16 , H03K17/567
CPC分类号： H03K17/30 , H03K17/107 , H03K17/168 , H03K17/567 , H03K2017/6875
摘要： There are disclosed herein various implementations of composite III-nitride semiconductor devices having turn-on prevention control. In one exemplary implementation, a normally OFF composite semiconductor device comprises a normally ON III-nitride power transistor and a low voltage (LV) device cascoded with the normally ON III-nitride power transistor to form the normally OFF composite semiconductor device. The LV device is configured to have a noise-resistant threshold voltage to provide the turn-on prevention control for the normally OFF composite semiconductor device by preventing noise current from flowing through a channel of the normally ON III-nitride power transistor in a noisy system.
摘要翻译：这里公开了具有开启防止控制的复合III族氮化物半导体器件的各种实现方式。在一个示例性实施方式中，正常关闭复合半导体器件包括通常为ON III族氮化物功率晶体管和与常规ON III族氮化物功率晶体管共同组成的低电压（LV）器件，以形成正常关闭复合半导体器件。 LV装置被配置为具有抗噪声阈值电压，以通过防止噪声电流在噪声系统中流过正常导通的III族氮化物功率晶体管的沟道来为正常关闭复合半导体器件提供导通防止控制。

6. 发明授权

US09263439B2 III-nitride switching device with an emulated diode 有权
标题翻译：具有仿真二极管的III族氮化物开关器件
公开(公告)号：US09263439B2
公开(公告)日：2016-02-16
申请号：US12800902
申请日：2010-05-24
申请人： Jason Zhang
发明人： Jason Zhang
IPC分类号： H01L27/06 , H01L27/085 , H03K17/687 , H01L21/8252
CPC分类号： H01L27/0255 , H01L21/8252 , H01L27/0605 , H01L27/0629 , H01L27/085 , H01L29/2003 , H01L29/205 , H01L29/7787 , H01L29/872 , H03K17/687
摘要： Some exemplary embodiments of a III-nitride switching device with an emulated diode have been disclosed. One exemplary embodiment comprises a GaN switching device fabricated on a substrate comprising a high threshold GaN transistor coupled across a low threshold GaN transistor, wherein a gate and a source of the low threshold GaN transistor are shorted with an interconnect metal to function as a parallel diode in a reverse mode. The high threshold GaN transistor is configured to provide noise immunity for the GaN switching device when in a forward mode. The high threshold GaN transistor and the low threshold GaN transistor are typically fabricated on the same substrate, and with significantly different thresholds. As a result, the superior switching characteristics of III-nitride devices may be leveraged while retaining the functionality and the monolithic structure of the inherent body diode in traditional silicon FETs.
摘要翻译：已经公开了具有仿真二极管的III族氮化物开关器件的一些示例性实施例。一个示例性实施例包括制造在包括跨越低阈值GaN晶体管的高阈值GaN晶体管的衬底上的GaN开关器件，其中低阈值GaN晶体管的栅极和源极与互连金属短路以用作并联二极管在反向模式。高阈值GaN晶体管被配置为当处于正向模式时为GaN开关器件提供抗噪声能力。高阈值GaN晶体管和低阈值GaN晶体管通常制造在相同的衬底上，具有明显不同的阈值。结果，可以利用III族氮化物器件的优异的开关特性，同时保持传统硅FET中固有体二极管的功能和单片结构。

7. 发明授权

US08766375B2 Composite semiconductor device with active oscillation prevention 有权
标题翻译：具有主动振荡防护的复合半导体器件
公开(公告)号：US08766375B2
公开(公告)日：2014-07-01
申请号：US13417143
申请日：2012-03-09
申请人： Tony Bramian , Jason Zhang
发明人： Tony Bramian , Jason Zhang
IPC分类号： H01L27/088 , H01L21/8236
CPC分类号： H01L27/085 , H01L21/8236 , H01L21/8258 , H01L25/18 , H01L27/0883 , H01L29/16 , H01L29/2003 , H01L29/78 , H01L2924/0002 , H03K17/107 , H03K17/168 , H03K17/302 , H03K17/567 , H01L2924/00
摘要： There are disclosed herein various implementations of composite semiconductor devices with active oscillation control. In one exemplary implementation, a normally OFF composite semiconductor device comprises a normally ON III-nitride power transistor and a low voltage (LV) device cascoded with the normally ON III-nitride power transistor to form the normally OFF composite semiconductor device. The LV device may be configured to include one or both of a reduced output resistance due to, for example, a modified body implant and a reduced transconductance due to, for example, a modified oxide thickness to cause a gain of the composite semiconductor device to be less than approximately 10,000.
摘要翻译：这里公开了具有主动振荡控制的复合半导体器件的各种实现方式。在一个示例性实施方式中，正常关闭复合半导体器件包括通常为ON III族氮化物功率晶体管和与常规ON III族氮化物功率晶体管共同组成的低电压（LV）器件，以形成正常关闭复合半导体器件。 LV器件可以被配置为包括由于例如修改的体植入物引起的减小的输出电阻中的一个或两个，以及由于例如修改的氧化物厚度导致的复合半导体器件的增益的减小的跨导小于约10,000。

8. 发明授权

US08148957B2 Power switch-mode circuit with devices of different threshold voltages 有权
标题翻译：具有不同阈值电压的器件的电源开关模式电路
公开(公告)号：US08148957B2
公开(公告)日：2012-04-03
申请号：US12108569
申请日：2008-04-24
申请人： Jason Zhang
发明人： Jason Zhang
IPC分类号： G05F1/40
CPC分类号： H02M3/1584 , H02M1/088 , H02M3/1588 , Y02B70/1466
摘要： The high side or low side FET of a buck converter, or both, are replaced by plural parallel devices of different threshold voltage and are turned on and off in a sequence which offers the best turn on and turn off characteristics related to high and low threshold voltages. The parallel devices can have the same or different active areas.
摘要翻译：降压转换器的高侧或低侧FET或两者均由具有不同阈值电压的多个并联器件代替，并且以提供最佳导通和关断与高和低阈值相关的特性的顺序导通和截止电压。并行设备可以具有相同或不同的活动区域。

9. 发明授权

US07839131B2 Gate driving scheme for depletion mode devices in buck converters 有权
标题翻译：降压转换器中耗尽型器件的栅极驱动方案
公开(公告)号：US07839131B2
公开(公告)日：2010-11-23
申请号：US12163100
申请日：2008-06-27
申请人： Bo Yang , Jason Zhang , Michael A. Briere
发明人： Bo Yang , Jason Zhang , Michael A. Briere
IPC分类号： G05F1/40
CPC分类号： H02M3/1588 , H02J7/0018 , H02J7/345 , Y02B40/90 , Y02B70/1466 , Y10T307/747
摘要： A circuit comprising a gate driver including first and second switching stages for driving respective sync and control switches, at least one of which is a normally ON depletion mode device, and another circuit connected to the first and second switching stages and including first and second circuits. The first circuit is coupled to the first switching stage and to the sync switch, the first switching stage having a first state wherein the sync switch is on, and a second state wherein a first bias voltage is switched to the gate of the sync switch to turn it off. The second circuit has a first state wherein the control switch is on when the sync switch is off, and a second state wherein the control switch is switched off when the sync switch is on by switching a second bias voltage to the gate of the control switch.
摘要翻译：一种包括栅极驱动器的电路，包括用于驱动相应的同步和控制开关的第一和第二开关级，其中至少一个是正常耗尽型器件，以及连接到第一和第二开关级的另一个电路，包括第一和第二电路。第一电路耦合到第一开关级和同步开关，第一开关级具有第一状态，其中同步开关导通，以及第二状态，其中第一偏置电压切换到同步开关的栅极至把它关掉。第二电路具有第一状态，其中当同步开关断开时控制开关接通;以及第二状态，其中当同步开关接通时，通过将第二偏置电压切换到控制开关的门，控制开关断开。

10. 发明申请

US20080265851A1 POWER SWITCH-MODE CIRCUIT WITH DEVICES OF DIFFERENT THRESHOLD VOLTAGES 有权
标题翻译：具有不同阈值电压的器件的电源开关电路
公开(公告)号：US20080265851A1
公开(公告)日：2008-10-30
申请号：US12108569
申请日：2008-04-24
申请人： Jason Zhang
发明人： Jason Zhang
IPC分类号： G05F1/00
CPC分类号： H02M3/1584 , H02M1/088 , H02M3/1588 , Y02B70/1466
摘要： The high side or low side FET of a buck converter, or both, are replaced by plural parallel devices of different threshold voltage and are turned on and off in a sequence which offers the best turn on and turn off characteristics related to high and low threshold voltages. The parallel devices can have the same or different active areas.
摘要翻译：降压转换器的高侧或低侧FET或两者均由具有不同阈值电压的多个并联器件代替，并且以提供最佳导通和关断与高和低阈值相关的特性的顺序导通和截止电压。并行设备可以具有相同或不同的活动区域。

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