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1. 发明申请

US20090091396A1 METHOD AND SYSTEM FOR CALIBRATION OF A TANK CIRCUIT IN A PHASE LOCK LOOP 有权
标题翻译：用于在相位锁定环中校准电路的方法和系统
公开(公告)号：US20090091396A1
公开(公告)日：2009-04-09
申请号：US11868306
申请日：2007-10-05
申请人： Heng-Yu Jian , Zhiwei Xu , Yi-Cheng Wu , Charles Chien
发明人： Heng-Yu Jian , Zhiwei Xu , Yi-Cheng Wu , Charles Chien
IPC分类号： H03L7/099 , H03L7/08
CPC分类号： H03L7/10 , H03L7/099
摘要： A phase lock loop includes a calibration loop for calibrating a tank circuit for capacitance variation through process variations of manufacturing an integrated circuit including the phase lock loop. A capacitance profile for setting the frequency of the phase lock loop at a process corner, such as a typical process corner is stored in driver software or a host processor. At power up, or after an idle time, a calibration is performed at two frequencies. The capacitances of operating the phase lock loop at the two frequencies are determined and stored. During a frequency change, the capacitance of operating the phase lock loop is determined from the capacitance profile and stored capacitances. In one aspect, the capacitance of the phase lock loop is presumed to change linearly with frequency and the two stored capacitances are used to determine a difference capacitance at the selected frequency by linear interpolating between the two stored capacitances. The interpolated difference capacitance is added to the capacitance in the capacitance profile at the selected frequency to generate an operating capacitance. The capacitance of a tank circuit of the phase lock loop is set to the operating capacitance.
摘要翻译：锁相环包括用于通过制造包括锁相环的集成电路的过程变化来校准用于电容变化的储能电路的校准回路。用于设置过程角（例如典型过程角）的锁相环频率的电容分布存储在驱动软件或主机处理器中。在上电或空闲时间后，以两个频率进行校准。确定并存储在两个频率下操作锁相环的电容。在频率变化期间，根据电容曲线和存储的电容确定操作锁相环的电容。在一个方面，假设锁相环的电容随频率线性变化，并且两个存储的电容用于通过两个存储电容之间的线性内插来确定所选频率处的差电容。内插差分电容以所选频率加到电容分布中的电容上，以产生一个工作电容。锁相环的电路电容设定为工作电容。

2. 发明授权

US07860470B2 Cross coupled high frequency buffer 有权
标题翻译：交叉耦合高频缓冲器
公开(公告)号：US07860470B2
公开(公告)日：2010-12-28
申请号：US11781198
申请日：2007-07-20
申请人： Zhiwei Xu , Heng-Yu Jian , Yi-Cheng Wu , Charles Chien
发明人： Zhiwei Xu , Heng-Yu Jian , Yi-Cheng Wu , Charles Chien
IPC分类号： H03J7/32
CPC分类号： H04B1/30 , H03F3/245 , H03F3/45183 , H03F3/45237 , H03F2203/45631 , H03F2203/45638
摘要： A local oscillator (LO) buffer circuit comprises first and second LO buffers arranged in a cross coupled configuration. The first LO buffer generates in-phase output signals in response to in-phase input signals, and quadrature output signals from the second LO buffer. The second LO buffer generates the quadrature output signals in response to quadrature input signals and the in-phase output signals. The LO buffers may include inductive loads. The LO buffers may include MOS transistors or bipolar junction transistors.
摘要翻译：本地振荡器（LO）缓冲电路包括以交叉耦合配置布置的第一和第二LO缓冲器。第一LO缓冲器响应于同相输入信号和来自第二LO缓冲器的正交输出信号产生同相输出信号。第二LO缓冲器响应于正交输入信号和同相输出信号产生正交输出信号。 LO缓冲器可以包括感性负载。 LO缓冲器可以包括MOS晶体管或双极结型晶体管。

3. 发明授权

US07609122B2 Method and system for calibration of a tank circuit in a phase lock loop 有权
标题翻译：在锁相环中调节电路的方法和系统
公开(公告)号：US07609122B2
公开(公告)日：2009-10-27
申请号：US11868306
申请日：2007-10-05
申请人： Heng-Yu Jian , Zhiwei Xu , Yi-Cheng Wu , Charles Chien
发明人： Heng-Yu Jian , Zhiwei Xu , Yi-Cheng Wu , Charles Chien
IPC分类号： H03B5/08
CPC分类号： H03L7/10 , H03L7/099
摘要： A phase lock loop (PLL) includes a calibration loop for calibrating a tank circuit for capacitance variation through process variations of manufacturing an integrated circuit including the PLL. A capacitance profile for setting the frequency of the PLL at a process comer is stored. At power up, or after an idle time, a calibration is performed at two frequencies. The capacitances of operating the phase lock loop at the two frequencies are determined and stored. During a frequency change, the capacitance of operating the PLL is determined from the capacitance profile and stored capacitances. The capacitance of the PLL is presumed to change linearly with frequency and the two stored capacitances are used to determine a difference capacitance at the selected frequency by linear interpolating between the two stored capacitances, which is added to the capacitance in the capacitance profile at the selected frequency to generate an operating capacitance.
摘要翻译：锁相环（PLL）包括用于通过制造包括PLL的集成电路的过程变化校准用于电容变化的振荡电路的校准回路。存储用于在处理角设定PLL的频率的电容分布。在上电或空闲时间后，以两个频率进行校准。确定并存储在两个频率下操作锁相环的电容。在频率变化期间，操作PLL的电容由电容曲线和存储的电容确定。假设PLL的电容随频率线性变化，并且两个存储的电容用于通过在所选择的电容分布中的电容相加的两个存储的电容之间的线性内插来确定所选频率处的差电容，产生一个工作电容的频率。

4. 发明授权

US08193845B2 Binary-weighted delta-sigma fractional-N frequency synthesizer with digital-to-analog differentiators canceling quantization noise 有权
$Binary-weighted delta-sigma fractional-N frequency synthesizer with digital-to-analog differentiators canceling quantization noise$
标题翻译：二进制加权的delta-sigma分数N频率合成器，具有数字到模拟微分器来消除量化噪声
公开(公告)号：US08193845B2
公开(公告)日：2012-06-05
申请号：US12831208
申请日：2010-07-06
申请人： Heng-Yu Jian , Zhiwei Xu , Yi-Cheng Wu , Mau-Chung Frank Chang
发明人： Heng-Yu Jian , Zhiwei Xu , Yi-Cheng Wu , Mau-Chung Frank Chang
IPC分类号： H03L7/06
CPC分类号： H03L7/1976
摘要： A phase lock loop includes a quantization circuit that generators an out of phase noise cancellation signal from an error in a delta-sigma modulator and applies the noise cancellation signal to the charge pump. The quantization circuit includes a digital-to-analog differentiator. The digital-to-analog differentiator may be, for example, a single-bit first-order digital-to-analog differentiator, a single-bit second-order digital-to-analog differentiator, or a full M-bit binary-weighted digital to analog differentiator.
摘要翻译：锁相环包括量化电路，其从Δ-Σ调制器中的误差产生异相噪声消除信号，并将噪声消除信号施加到电荷泵。量化电路包括数模转换微分器。数/模微分器可以是例如单位一阶数模比较器，单位二阶数模比较器或全M位二进制加权数字到模拟微分器。

5. 发明申请

US20120007643A1 Binary-Weighted Delta-Sigma Fractional-N Frequency Synthesizer With Digital-To-Analog Differentiators Canceling Quantization Noise 有权
标题翻译：二进制加权Delta-Sigma分数N频率合成器，具有数字到模拟差分器取消量化噪声
公开(公告)号：US20120007643A1
公开(公告)日：2012-01-12
申请号：US12831208
申请日：2010-07-06
申请人： Heng-Yu Jian , Zhiwei Xu , Yi-Cheng Wu , Mau-Chung Frank Chang
发明人： Heng-Yu Jian , Zhiwei Xu , Yi-Cheng Wu , Mau-Chung Frank Chang
IPC分类号： H03L7/08
CPC分类号： H03L7/1976
摘要： A phase lock loop includes a quantization circuit that generators an out of phase noise cancellation signal from an error in a delta-sigma modulator and applies the noise cancellation signal to the charge pump. The quantization circuit includes a digital-to-analog differentiator. The digital-to-analog differentiator may be, for example, a single-bit first-order digital-to-analog differentiator, a single-bit second-order digital-to-analog differentiator, or a full M-bit binary-weighted digital to analog differentiator.
摘要翻译：锁相环包括量化电路，其从Δ-Σ调制器中的误差产生异相噪声消除信号，并将噪声消除信号施加到电荷泵。量化电路包括数模转换微分器。数/模微分器可以是例如单位一阶数模比较器，单位二阶数模比较器或全M位二进制加权数字到模拟微分器。

6. 发明授权

US07012472B2 Digital control loop to improve phase noise performance and RX/TX linearity 有权
标题翻译：数字控制回路，以提高相位噪声性能和RX / TX线性度
公开(公告)号：US07012472B2
公开(公告)日：2006-03-14
申请号：US10888861
申请日：2004-07-09
申请人： Zhiwei Xu , Yi-Cheng Wu , Mau-Chung Frank Chang
发明人： Zhiwei Xu , Yi-Cheng Wu , Mau-Chung Frank Chang
IPC分类号： H03L7/00
CPC分类号： H03L5/00 , H03B5/04 , H03B5/1212 , H03B5/1228 , H03B5/124 , H03B5/1278 , H03B5/1293
摘要： A system or method for controlling a voltage controlled oscillator (VCO) or LO buffer includes an amplitude detector for detecting an amplitude value at a node corresponding to the at least one output line. A comparator compares the detected amplitude value with a predetermined amplitude value, and outputs a first digital value when the detected amplitude value is greater than the predetermined amplitude value, and a second digital value when the detected amplitude value is less than the predetermined amplitude value. An accumulator accumulates outputs of the comparator so as to provide an accumulated digital amplitude value. A digital-to-analog converter converts the accumulated digital amplitude value to an accumulated analog amplitude value. The analog accumulated amplitude value is provided as an updated bias control signal to the bias transistor of the VCO or LO buffer.
摘要翻译：用于控制压控振荡器（VCO）或LO缓冲器的系统或方法包括：幅度检测器，用于检测与至少一条输出线对应的节点处的振幅值。比较器将检测到的振幅值与预定的振幅值进行比较，当检测到的振幅值大于预定振幅值时，输出第一数字值，当检测到的振幅值小于预定振幅值时，输出第二数字值。累加器累积比较器的输出，以提供累加的数字振幅值。数模转换器将累积的数字振幅值转换为累积的模拟幅度值。模拟累积振幅值作为更新的偏置控制信号提供给VCO或LO缓冲器的偏置晶体管。

7. 发明申请

US20060006951A1 DIGITAL CONTROL LOOP TO IMPROVE PHASE NOISE PERFORMANCE AND RX/TX LINEARITY 有权
标题翻译：数字控制环路提高了相位噪声性能和RX / TX线性
公开(公告)号：US20060006951A1
公开(公告)日：2006-01-12
申请号：US10888861
申请日：2004-07-09
申请人： Zhiwei Xu , Yi-Cheng Wu , Mau-Chung Chang
发明人： Zhiwei Xu , Yi-Cheng Wu , Mau-Chung Chang
IPC分类号： H03L7/00
CPC分类号： H03L5/00 , H03B5/04 , H03B5/1212 , H03B5/1228 , H03B5/124 , H03B5/1278 , H03B5/1293
摘要： A system or method for controlling a voltage controlled oscillator (VCO) or LO buffer includes an amplitude detector for detecting an amplitude value at a node corresponding to the at least one output line. A comparator compares the detected amplitude value with a predetermined amplitude value, and outputs a first digital value when the detected amplitude value is greater than the predetermined amplitude value, and a second digital value when the detected amplitude value is less than the predetermined amplitude value. An accumulator accumulates outputs of the comparator so as to provide an accumulated digital amplitude value. A digital-to-analog converter converts the accumulated digital amplitude value to an accumulated analog amplitude value. The analog accumulated amplitude value is provided as an updated bias control signal to the bias transistor of the VCO or LO buffer.
摘要翻译：用于控制压控振荡器（VCO）或LO缓冲器的系统或方法包括：幅度检测器，用于检测与至少一条输出线对应的节点处的振幅值。比较器将检测到的振幅值与预定的振幅值进行比较，当检测到的振幅值大于预定振幅值时，输出第一数字值，当检测到的振幅值小于预定振幅值时，输出第二数字值。累加器累积比较器的输出，以提供累加的数字振幅值。数模转换器将累积的数字振幅值转换为累积的模拟幅度值。模拟累积振幅值作为更新的偏置控制信号提供给VCO或LO缓冲器的偏置晶体管。

8. 发明申请

US20050103404A1 Low nickel containing chromim-nickel-mananese-copper austenitic stainless steel 审中-公开
标题翻译：低镍含铬铬镍锰锰铜奥氏体不锈钢
公开(公告)号：US20050103404A1
公开(公告)日：2005-05-19
申请号：US10993674
申请日：2004-11-19
申请人： Meng-Hsin Hsieh , Yi-Cheng Wu , Pei-Te Huang , Hao-Shang Liu
发明人： Meng-Hsin Hsieh , Yi-Cheng Wu , Pei-Te Huang , Hao-Shang Liu
IPC分类号： C22C38/42
CPC分类号： C22C38/42 , C22C38/001 , C22C38/02 , C22C38/58
摘要： An austenitic stainless steel includes (a) 0.03 wt % to 0.12 wt % of C, (b) 0.2 wt % to 1.0 wt % of Si, (c) 7.5 wt % to 10.5 wt % of Mn, (d) 14.0 wt % to 16.0 wt % of Cr, (e) 4.05 wt % to 4.31 wt % of Ni, (f) 0.04 wt % to 0.07 wt % of N, (g) 1.0 wt % to 3.5 wt % of Cu, (h) trace amount of Mo, and the balance being Fe and incidental impurities. The austenitic stainless steel has a δ-ferrite content less than 8.5 and equal to 6.77[(d)+(h)+1.5(b)]−4.85[(e)+30(a)+30(f)+0.5(c)+0.3(g)]−52.75.
摘要翻译：奥氏体不锈钢包括（a）0.03重量％至0.12重量％的C，（b）0.2重量％至1.0重量％的Si，（c）7.5重量％至10.5重量％的Mn，（d）14.0重量％至6.0重量％的Cr，（e）4.05重量％至4.31重量％的Ni，（f）0.04重量％至0.07重量％的N，（g）1.0重量％至3.5重量％的Cu，（h）痕量 Mo量，余量为Fe和杂质。奥氏体不锈钢的δ-铁素体含量小于8.5，等于6.77 [（d）+（h）+1.5（b）] - 4.85 [（e）+30（a）+30（f）+0.5（ c）+0.3（g）] - 52.75。

9. 发明授权

US07780908B2 Low nickel containing chromium-nickel-manganese- copper austenitic stainless steel 有权
标题翻译：低镍含铬镍锰铜奥氏体不锈钢
公开(公告)号：US07780908B2
公开(公告)日：2010-08-24
申请号：US11866869
申请日：2007-10-03
申请人： Meng-Hsin Hsieh , Yi-Cheng Wu , Pei-Te Huang , Hao-Shang Liu
发明人： Meng-Hsin Hsieh , Yi-Cheng Wu , Pei-Te Huang , Hao-Shang Liu
IPC分类号： C22C38/58
CPC分类号： C22C38/42 , C22C38/001 , C22C38/02 , C22C38/58
摘要： An austenitic stainless steel includes (a) 0.03 wt % to 0.12 wt % of C, (b) 0.2 wt % to 1.0 wt % of Si, (c) 8.55 wt % to 10.12 wt % of Mn, (d) 14.0 wt % to 16.0 wt % of Cr, (e) 4.05 wt % to 4.31 wt % of Ni, (f) 0.04 wt % to 0.07 wt % of N, (g) 1.0 wt % to 3.5 wt % of Cu, (h) trace amount of Mo, and the balance being Fe and incidental impurities. The austenitic stainless steel has a δ-ferrite content less than 8.5 and equal to 6.77[(d)+(h)+1.5(b)]−4.85[(e)+30(a)+30(f)+0.5(c)+0.3(g)]−52.75.
摘要翻译：奥氏体不锈钢包括（a）0.03重量％至0.12重量％的C，（b）0.2重量％至1.0重量％的Si，（c）8.55重量％至10.12重量％的Mn，（d）14.0重量％至6.0重量％的Cr，（e）4.05重量％至4.31重量％的Ni，（f）0.04重量％至0.07重量％的N，（g）1.0重量％至3.5重量％的Cu，（h）痕量 Mo量，余量为Fe和杂质。奥氏体不锈钢的δ-铁素体含量小于8.5，等于6.77 [（d）+（h）+1.5（b）] - 4.85 [（e）+30（a）+30（f）+0.5（ c）+0.3（g）] - 52.75。

10. 发明申请

US20080075623A1 LOW NICKEL CONTAINING CHROMIUM-NICKEL-MANGANESE- COPPER AUSTENITIC STAINLESS STEEL 有权
标题翻译：低镍含铬铬锰锰铜奥氏体不锈钢
公开(公告)号：US20080075623A1
公开(公告)日：2008-03-27
申请号：US11866869
申请日：2007-10-03
申请人： Meng-Hsin Hsieh , Yi-Cheng Wu , Pei-Te Huang , Hao-Shang Liu
发明人： Meng-Hsin Hsieh , Yi-Cheng Wu , Pei-Te Huang , Hao-Shang Liu
IPC分类号： C22C38/58
CPC分类号： C22C38/42 , C22C38/001 , C22C38/02 , C22C38/58
摘要： An austenitic stainless steel includes (a) 0.03 wt % to 0.12 wt % of C, (b) 0.2 wt % to 1.0 wt % of Si, (c) 8.55 wt % to 10.12 wt % of Mn, (d) 14.0 wt % to 16.0 wt % of Cr, (e) 4.05 wt % to 4.31 wt % of Ni, (f) 0.04 wt % to 0.07 wt % of N, (g) 1.0 wt % to 3.5 wt % of Cu, (h) trace amount of Mo, and the balance being Fe and incidental impurities. The austenitic stainless steel has a δ-ferrite content less than 8.5 and equal to 6.77[(d)+(h)+1.5(b)]−4.85[(e)+30(a)+30(f)+0.5(c)+0.3(g)]−52.75.
摘要翻译：奥氏体不锈钢包括（a）0.03重量％至0.12重量％的C，（b）0.2重量％至1.0重量％的Si，（c）8.55重量％至10.12重量％的Mn，（d）14.0重量％至6.0重量％的Cr，（e）4.05重量％至4.31重量％的Ni，（f）0.04重量％至0.07重量％的N，（g）1.0重量％至3.5重量％的Cu，（h）痕量 Mo量，余量为Fe和杂质。奥氏体不锈钢的δ-铁素体含量小于8.5，等于6.77 [（d）+（h）+1.5（b）] - 4.85 [（e）+30（a）+30（f）+0.5（ c）+0.3（g）] - 52.75。

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