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1. 发明授权

US06670801B2 Second harmonic tuning of an active RF device 有权
标题翻译：有源RF器件的二次谐波调谐
公开(公告)号：US06670801B2
公开(公告)日：2003-12-30
申请号：US09920276
申请日：2001-07-31
申请人： Heng-Yu Jian , Thomas Marra
发明人： Heng-Yu Jian , Thomas Marra
IPC分类号： G01R2304
CPC分类号： H04B1/0458
摘要： Second-order harmonic tuning of an active device, such as a transistor used in a radio frequency (RF) power amplifier circuit, is accomplished by positioning a quarter-wavelength stub along a transmission line coupled to an output of the device, such that the output is presented with a desired impedance for the second harmonic.
摘要翻译：有源器件（例如在射频（RF）功率放大器电路中使用的晶体管）的二次谐波调谐通过沿着耦合到器件的输出的传输线定位四分之一波长短截线来实现，使得输出具有用于二次谐波的期望阻抗。

2. 发明授权

US08193845B2 Binary-weighted delta-sigma fractional-N frequency synthesizer with digital-to-analog differentiators canceling quantization noise 有权
$Binary-weighted delta-sigma fractional-N frequency synthesizer with digital-to-analog differentiators canceling quantization noise$
标题翻译：二进制加权的delta-sigma分数N频率合成器，具有数字到模拟微分器来消除量化噪声
公开(公告)号：US08193845B2
公开(公告)日：2012-06-05
申请号：US12831208
申请日：2010-07-06
申请人： Heng-Yu Jian , Zhiwei Xu , Yi-Cheng Wu , Mau-Chung Frank Chang
发明人： Heng-Yu Jian , Zhiwei Xu , Yi-Cheng Wu , Mau-Chung Frank Chang
IPC分类号： H03L7/06
CPC分类号： H03L7/1976
摘要： A phase lock loop includes a quantization circuit that generators an out of phase noise cancellation signal from an error in a delta-sigma modulator and applies the noise cancellation signal to the charge pump. The quantization circuit includes a digital-to-analog differentiator. The digital-to-analog differentiator may be, for example, a single-bit first-order digital-to-analog differentiator, a single-bit second-order digital-to-analog differentiator, or a full M-bit binary-weighted digital to analog differentiator.
摘要翻译：锁相环包括量化电路，其从Δ-Σ调制器中的误差产生异相噪声消除信号，并将噪声消除信号施加到电荷泵。量化电路包括数模转换微分器。数/模微分器可以是例如单位一阶数模比较器，单位二阶数模比较器或全M位二进制加权数字到模拟微分器。

3. 发明授权

US07860470B2 Cross coupled high frequency buffer 有权
标题翻译：交叉耦合高频缓冲器
公开(公告)号：US07860470B2
公开(公告)日：2010-12-28
申请号：US11781198
申请日：2007-07-20
申请人： Zhiwei Xu , Heng-Yu Jian , Yi-Cheng Wu , Charles Chien
发明人： Zhiwei Xu , Heng-Yu Jian , Yi-Cheng Wu , Charles Chien
IPC分类号： H03J7/32
CPC分类号： H04B1/30 , H03F3/245 , H03F3/45183 , H03F3/45237 , H03F2203/45631 , H03F2203/45638
摘要： A local oscillator (LO) buffer circuit comprises first and second LO buffers arranged in a cross coupled configuration. The first LO buffer generates in-phase output signals in response to in-phase input signals, and quadrature output signals from the second LO buffer. The second LO buffer generates the quadrature output signals in response to quadrature input signals and the in-phase output signals. The LO buffers may include inductive loads. The LO buffers may include MOS transistors or bipolar junction transistors.
摘要翻译：本地振荡器（LO）缓冲电路包括以交叉耦合配置布置的第一和第二LO缓冲器。第一LO缓冲器响应于同相输入信号和来自第二LO缓冲器的正交输出信号产生同相输出信号。第二LO缓冲器响应于正交输入信号和同相输出信号产生正交输出信号。 LO缓冲器可以包括感性负载。 LO缓冲器可以包括MOS晶体管或双极结型晶体管。

4. 发明授权

US07609122B2 Method and system for calibration of a tank circuit in a phase lock loop 有权
标题翻译：在锁相环中调节电路的方法和系统
公开(公告)号：US07609122B2
公开(公告)日：2009-10-27
申请号：US11868306
申请日：2007-10-05
申请人： Heng-Yu Jian , Zhiwei Xu , Yi-Cheng Wu , Charles Chien
发明人： Heng-Yu Jian , Zhiwei Xu , Yi-Cheng Wu , Charles Chien
IPC分类号： H03B5/08
CPC分类号： H03L7/10 , H03L7/099
摘要： A phase lock loop (PLL) includes a calibration loop for calibrating a tank circuit for capacitance variation through process variations of manufacturing an integrated circuit including the PLL. A capacitance profile for setting the frequency of the PLL at a process comer is stored. At power up, or after an idle time, a calibration is performed at two frequencies. The capacitances of operating the phase lock loop at the two frequencies are determined and stored. During a frequency change, the capacitance of operating the PLL is determined from the capacitance profile and stored capacitances. The capacitance of the PLL is presumed to change linearly with frequency and the two stored capacitances are used to determine a difference capacitance at the selected frequency by linear interpolating between the two stored capacitances, which is added to the capacitance in the capacitance profile at the selected frequency to generate an operating capacitance.
摘要翻译：锁相环（PLL）包括用于通过制造包括PLL的集成电路的过程变化校准用于电容变化的振荡电路的校准回路。存储用于在处理角设定PLL的频率的电容分布。在上电或空闲时间后，以两个频率进行校准。确定并存储在两个频率下操作锁相环的电容。在频率变化期间，操作PLL的电容由电容曲线和存储的电容确定。假设PLL的电容随频率线性变化，并且两个存储的电容用于通过在所选择的电容分布中的电容相加的两个存储的电容之间的线性内插来确定所选频率处的差电容，产生一个工作电容的频率。

5. 发明申请

US20090023413A1 Cross Coupled High Frequency Buffer 有权
标题翻译：交叉耦合高频缓冲器
公开(公告)号：US20090023413A1
公开(公告)日：2009-01-22
申请号：US11781198
申请日：2007-07-20
申请人： Zhiwei XU , Heng-Yu JIAN , Yi-Cheng WU , Charles CHIEN
发明人： Zhiwei XU , Heng-Yu JIAN , Yi-Cheng WU , Charles CHIEN
IPC分类号： H04B1/26
CPC分类号： H04B1/30 , H03F3/245 , H03F3/45183 , H03F3/45237 , H03F2203/45631 , H03F2203/45638
摘要： A local oscillator (LO) buffer circuit comprises first and second LO buffers arranged in a cross coupled configuration. The first LO buffer generates in-phase output signals in response to in-phase input signals, and quadrature output signals from the second LO buffer. The second LO buffer generates the quadrature output signals in response to quadrature input signals and the in-phase output signals. The LO buffers may include inductive loads. The LO buffers may include MOS transistors or bipolar junction transistors.
摘要翻译：本地振荡器（LO）缓冲电路包括以交叉耦合配置布置的第一和第二LO缓冲器。第一LO缓冲器响应于同相输入信号和来自第二LO缓冲器的正交输出信号产生同相输出信号。第二LO缓冲器响应于正交输入信号和同相输出信号产生正交输出信号。 LO缓冲器可以包括感性负载。 LO缓冲器可以包括MOS晶体管或双极结型晶体管。

6. 发明申请

US20090091396A1 METHOD AND SYSTEM FOR CALIBRATION OF A TANK CIRCUIT IN A PHASE LOCK LOOP 有权
标题翻译：用于在相位锁定环中校准电路的方法和系统
公开(公告)号：US20090091396A1
公开(公告)日：2009-04-09
申请号：US11868306
申请日：2007-10-05
申请人： Heng-Yu Jian , Zhiwei Xu , Yi-Cheng Wu , Charles Chien
发明人： Heng-Yu Jian , Zhiwei Xu , Yi-Cheng Wu , Charles Chien
IPC分类号： H03L7/099 , H03L7/08
CPC分类号： H03L7/10 , H03L7/099
摘要： A phase lock loop includes a calibration loop for calibrating a tank circuit for capacitance variation through process variations of manufacturing an integrated circuit including the phase lock loop. A capacitance profile for setting the frequency of the phase lock loop at a process corner, such as a typical process corner is stored in driver software or a host processor. At power up, or after an idle time, a calibration is performed at two frequencies. The capacitances of operating the phase lock loop at the two frequencies are determined and stored. During a frequency change, the capacitance of operating the phase lock loop is determined from the capacitance profile and stored capacitances. In one aspect, the capacitance of the phase lock loop is presumed to change linearly with frequency and the two stored capacitances are used to determine a difference capacitance at the selected frequency by linear interpolating between the two stored capacitances. The interpolated difference capacitance is added to the capacitance in the capacitance profile at the selected frequency to generate an operating capacitance. The capacitance of a tank circuit of the phase lock loop is set to the operating capacitance.
摘要翻译：锁相环包括用于通过制造包括锁相环的集成电路的过程变化来校准用于电容变化的储能电路的校准回路。用于设置过程角（例如典型过程角）的锁相环频率的电容分布存储在驱动软件或主机处理器中。在上电或空闲时间后，以两个频率进行校准。确定并存储在两个频率下操作锁相环的电容。在频率变化期间，根据电容曲线和存储的电容确定操作锁相环的电容。在一个方面，假设锁相环的电容随频率线性变化，并且两个存储的电容用于通过两个存储电容之间的线性内插来确定所选频率处的差电容。内插差分电容以所选频率加到电容分布中的电容上，以产生一个工作电容。锁相环的电路电容设定为工作电容。

7. 发明授权

US07266354B2 Reducing the peak-to-average power ratio of a communication signal 有权
标题翻译：降低通信信号的峰均功率比
公开(公告)号：US07266354B2
公开(公告)日：2007-09-04
申请号：US09888795
申请日：2001-06-25
申请人： Heng-Yu Jian , Lennart Mathe
发明人： Heng-Yu Jian , Lennart Mathe
IPC分类号： H04B1/06
CPC分类号： H04B1/707 , H04B2201/70706
摘要： Systems and methods are provided for reducing the peak to average ratio of signals, so that the signals can be amplified more efficiently. An error signal that corresponds to crests of the input signal is generated, and subtracted from the input signal. When a crest is so long that it corresponds to more than one sample, only the maximum sample contained in the crest is used to form the error signal. Optionally, multiple stages of decresting may be implemented sequentially.
摘要翻译：提供的系统和方法用于降低信号的峰均比，从而可以更有效地放大信号。产生对应于输入信号的波峰的误差信号，并从输入信号中减去。当一个峰值长到多于一个样本时，仅使用波峰中包含的最大样本来形成误差信号。可选地，顺序地实施多个递减阶段。

8. 发明申请

US20120007643A1 Binary-Weighted Delta-Sigma Fractional-N Frequency Synthesizer With Digital-To-Analog Differentiators Canceling Quantization Noise 有权
标题翻译：二进制加权Delta-Sigma分数N频率合成器，具有数字到模拟差分器取消量化噪声
公开(公告)号：US20120007643A1
公开(公告)日：2012-01-12
申请号：US12831208
申请日：2010-07-06
申请人： Heng-Yu Jian , Zhiwei Xu , Yi-Cheng Wu , Mau-Chung Frank Chang
发明人： Heng-Yu Jian , Zhiwei Xu , Yi-Cheng Wu , Mau-Chung Frank Chang
IPC分类号： H03L7/08
CPC分类号： H03L7/1976
摘要： A phase lock loop includes a quantization circuit that generators an out of phase noise cancellation signal from an error in a delta-sigma modulator and applies the noise cancellation signal to the charge pump. The quantization circuit includes a digital-to-analog differentiator. The digital-to-analog differentiator may be, for example, a single-bit first-order digital-to-analog differentiator, a single-bit second-order digital-to-analog differentiator, or a full M-bit binary-weighted digital to analog differentiator.
摘要翻译：锁相环包括量化电路，其从Δ-Σ调制器中的误差产生异相噪声消除信号，并将噪声消除信号施加到电荷泵。量化电路包括数模转换微分器。数/模微分器可以是例如单位一阶数模比较器，单位二阶数模比较器或全M位二进制加权数字到模拟微分器。

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