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    • 2. 发明申请
    • METHOD AND SYSTEM FOR CALIBRATION OF A TANK CIRCUIT IN A PHASE LOCK LOOP
    • 用于在相位锁定环中校准电路的方法和系统
    • US20090091396A1
    • 2009-04-09
    • US11868306
    • 2007-10-05
    • Heng-Yu JianZhiwei XuYi-Cheng WuCharles Chien
    • Heng-Yu JianZhiwei XuYi-Cheng WuCharles Chien
    • H03L7/099H03L7/08
    • H03L7/10H03L7/099
    • A phase lock loop includes a calibration loop for calibrating a tank circuit for capacitance variation through process variations of manufacturing an integrated circuit including the phase lock loop. A capacitance profile for setting the frequency of the phase lock loop at a process corner, such as a typical process corner is stored in driver software or a host processor. At power up, or after an idle time, a calibration is performed at two frequencies. The capacitances of operating the phase lock loop at the two frequencies are determined and stored. During a frequency change, the capacitance of operating the phase lock loop is determined from the capacitance profile and stored capacitances. In one aspect, the capacitance of the phase lock loop is presumed to change linearly with frequency and the two stored capacitances are used to determine a difference capacitance at the selected frequency by linear interpolating between the two stored capacitances. The interpolated difference capacitance is added to the capacitance in the capacitance profile at the selected frequency to generate an operating capacitance. The capacitance of a tank circuit of the phase lock loop is set to the operating capacitance.
    • 锁相环包括用于通过制造包括锁相环的集成电路的过程变化来校准用于电容变化的储能电路的校准回路。 用于设置过程角(例如典型过程角)的锁相环频率的电容分布存储在驱动软件或主机处理器中。 在上电或空闲时间后,以两个频率进行校准。 确定并存储在两个频率下操作锁相环的电容。 在频率变化期间,根据电容曲线和存储的电容确定操作锁相环的电容。 在一个方面,假设锁相环的电容随频率线性变化,并且两个存储的电容用于通过两个存储电容之间的线性内插来确定所选频率处的差电容。 内插差分电容以所选频率加到电容分布中的电容上,以产生一个工作电容。 锁相环的电路电容设定为工作电容。
    • 6. 发明授权
    • Method and system for calibration of a tank circuit in a phase lock loop
    • 在锁相环中调节电路的方法和系统
    • US07609122B2
    • 2009-10-27
    • US11868306
    • 2007-10-05
    • Heng-Yu JianZhiwei XuYi-Cheng WuCharles Chien
    • Heng-Yu JianZhiwei XuYi-Cheng WuCharles Chien
    • H03B5/08
    • H03L7/10H03L7/099
    • A phase lock loop (PLL) includes a calibration loop for calibrating a tank circuit for capacitance variation through process variations of manufacturing an integrated circuit including the PLL. A capacitance profile for setting the frequency of the PLL at a process comer is stored. At power up, or after an idle time, a calibration is performed at two frequencies. The capacitances of operating the phase lock loop at the two frequencies are determined and stored. During a frequency change, the capacitance of operating the PLL is determined from the capacitance profile and stored capacitances. The capacitance of the PLL is presumed to change linearly with frequency and the two stored capacitances are used to determine a difference capacitance at the selected frequency by linear interpolating between the two stored capacitances, which is added to the capacitance in the capacitance profile at the selected frequency to generate an operating capacitance.
    • 锁相环(PLL)包括用于通过制造包括PLL的集成电路的过程变化校准用于电容变化的振荡电路的校准回路。 存储用于在处理角设定PLL的频率的电容分布。 在上电或空闲时间后,以两个频率进行校准。 确定并存储在两个频率下操作锁相环的电容。 在频率变化期间,操作PLL的电容由电容曲线和存储的电容确定。 假设PLL的电容随频率线性变化,并且两个存储的电容用于通过在所选择的电容分布中的电容相加的两个存储的电容之间的线性内插来确定所选频率处的差电容, 产生一个工作电容的频率。