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1. 发明授权

US5930596A Semiconductor component for vertical integration and manufacturing method 失效
标题翻译：半导体元件垂直整合制造方法
公开(公告)号：US5930596A
公开(公告)日：1999-07-27
申请号：US721980
申请日：1996-09-27
申请人： Helmut Klose , Werner Weber , Emmerich Bertagnolli , Siegmar Koppe , Holger Hubner
发明人： Helmut Klose , Werner Weber , Emmerich Bertagnolli , Siegmar Koppe , Holger Hubner
IPC分类号： H01L25/18 , H01L23/48 , H01L25/065 , H01L25/07 , H01L27/00 , H01L21/00 , H01L21/4763
CPC分类号： H01L24/72 , H01L2924/01005 , H01L2924/01033 , H01L2924/01058 , H01L2924/01074 , H01L2924/01087 , H01L2924/14
摘要： A terminal metallization (8) is applied onto and structured on a layer structure on the upper side of the component, the terminal metallization is applied on the upper side of an insulating layer (7) with an opening on a metallization (6) provided for electrical connection. By filling a hole produced in a covering dielectric with metal, a contact rod (12) seated on this terminal metallization (8) is formed. This contact rod is resiliently movable in a surrounding opening (14) of the component on the free part of the terminal metallization (8) anchored in the layer structure. This enables the reversible contacting of the component to a further component arranged vertically thereto, whereby the planar upper sides lying opposite one another can be brought into intimate contact because the contact rod (12) pressed against a contact (15) of the other component is pressed back into the opening (14) and an adequately firm connection of the contacts is achieved by the spring power of the terminal metallization (8).
摘要翻译： PCT No.PCT / DE95 / 00313 Sec。 371日期1996年9月27日第 102（e）1996年9月27日PCT 1995年3月7日PCT PCT。公开号WO96 / 26568 PCT 日期1995年10月5日端子金属化（8）被施加到构件的上侧上的层结构上并在其上构造，端子金属化被施加在绝缘层（7）的上侧，金属化开口（6）用于电连接。通过用金属填充在覆盖电介质中产生的孔，形成了位于该端子金属化（8）上的接触棒（12）。该接触杆可以在锚定在层结构中的端子金属化（8）的自由部分上的部件的周围开口（14）中弹性移动。这使得部件与其垂直方向布置的另一部件可逆地接触，由此，压接在另一部件的接触件（15）上的接触杆（12）是彼此相对的平面上侧面压入到开口（14）中，通过端子金属化（8）的弹簧功率实现触点的充分牢固的连接。

2. 发明授权

US5969534A Semiconductor testing apparatus 失效
标题翻译：半导体测试仪器
公开(公告)号：US5969534A
公开(公告)日：1999-10-19
申请号：US666491
申请日：1996-07-11
申请人： Holger Hubner , Werner Weber , Siegmar Koppe , Helmut Klose
发明人： Holger Hubner , Werner Weber , Siegmar Koppe , Helmut Klose
IPC分类号： G01R31/26 , G01R1/06 , G01R1/067 , G01R1/073 , H01L21/66 , G01R31/02
CPC分类号： G01R1/06783
摘要： A method and apparatus for the reversible contacting of a semiconductor circuit level to assist in performing a function test. The apparatus includes a testing head having test points arranged at a test side lying opposite the contact surfaces of a semiconductor circuit level. The test points are formed of liquid contacts in recesses in the test side of the testing head wherein the liquid contacts form menisci that project beyond the surface of the testing head. The recesses, in turn, are provided for metallizations which are connected to electrically-conductive leads. In addition, the surface may be provided with a roughening or with etched trenches.
摘要翻译： PCT No.PCT / DE95 / 00013 Sec。 371日期：1996年7月11日 102（e）日期1996年7月11日PCT 1995年1月9日PCT PCT。公开号WO95 / 18975 日期1995年7月13日用于半导体电路级的可逆接触以辅助执行功能测试的方法和装置。该装置包括具有布置在与半导体电路电平的接触表面相对的测试侧的测试点的测试头。测试点由测试头测试侧的凹槽中的液体触点形成，其中液体触点形成突出超出测试头表面的半月板。这些凹槽又被提供用于连接到导电引线的金属化。此外，表面可以设置有粗糙化或具有蚀刻的沟槽。

3. 发明授权

US5358882A Method for manufacturing a bipolar transistor in a substrate 失效
标题翻译：在基板中制造双极晶体管的方法
公开(公告)号：US5358882A
公开(公告)日：1994-10-25
申请号：US030901
申请日：1993-03-15
申请人： Emmerich Bertagnolli , Helmut Klose
发明人： Emmerich Bertagnolli , Helmut Klose
IPC分类号： H01L29/73 , H01L21/331 , H01L21/74 , H01L29/732 , H01L21/265
CPC分类号： H01L29/66272 , H01L21/743 , H01L29/7325 , Y10S148/011
摘要： A method for producing a bipolar transistor completely surrounded by an insulating trench in a substrate. Insulating regions at the surface of the substrate can be produced by depositing an SiO.sub.2 layer on the basis of thermal decomposition of TEOS and subsequent structuring of the SiO.sub.2 layer. The insulating regions can be employed as a self-aligning mask for the production of a collector terminal and of a substrate terminal.
摘要翻译：一种完全由基板中的绝缘沟槽围绕的双极晶体管的制造方法。可以通过在TEOS的热分解和SiO 2层的结构化的基础上沉积SiO 2层来制造衬底表面的绝缘区域。绝缘区域可以用作用于生产集电极端子和衬底端子的自对准掩模。

4. 发明授权

US5767001A Process for producing semiconductor components between which contact is made vertically 失效
标题翻译：用于制造在其之间进行触点的半导体部件的制造方法
公开(公告)号：US5767001A
公开(公告)日：1998-06-16
申请号：US545650
申请日：1995-11-03
申请人： Emmerich Bertagnolli , Helmut Klose
发明人： Emmerich Bertagnolli , Helmut Klose
IPC分类号： H01L21/768 , H01L23/48 , H01L25/065 , H01L27/00 , H01L27/06 , H01L21/283 , H01L21/302
CPC分类号： H01L25/0657 , H01L21/76898 , H01L23/481 , H01L25/50 , H01L27/0688 , H01L2225/06513 , H01L2225/06524 , H01L2225/06541 , H01L2924/0002
摘要： A process for producing components having a contact structure provides for vertical contact-making, in which, for the connection of a metal contact of a first component to a metal contact of a second component, the substrate is etched out, starting from the top, in a region provided for a vertical, conductive connection, this recess is filled with a metal so that said metal is connected to the surface of the metal contact, the rear side of the substrate is removed until the metal projects beyond the rear side, a metallization layer made of a metal having a low melting point, for example AuIn, is applied to the metal contact of the second component, the surface of the second component is provided with a planar layer, the two components are arranged vertically with respect to one another and a permanent contact is produced between the metal of the first component and the metallization layer of the second component by pressing one onto the other and heating.
摘要翻译： PCT No.PCT / DE94 / 00486 Sec。 371日期：1995年11月3日 102（e）1995年11月3日日期PCT 1994年5月2日PCT PCT。 WO94 / 25981 PCT公开日期1994年11月10日具有接触结构的部件的制造方法提供垂直接触，其中为了将第一部件的金属接触件与第二部件的金属接触件连接，蚀刻出基板，从顶部开始，在设置用于垂直导电连接的区域中，该凹部填充有金属，使得所述金属连接到金属接触件的表面，基板的后侧被移除，直到金属突出超出背面，由具有低熔点的金属（例如AuIn）制成的金属化层被施加到第二部件的金属接触件，第二部件的表面设置有平面层，两个部件被布置在第一部件的金属和第二部件的金属化层之间通过将其彼此挤压并加热而产生永久接触。

5. 发明授权

US06172391B2 DRAM cell arrangement and method for the manufacture thereof 有权
标题翻译： DRAM单元布置及其制造方法
公开(公告)号：US06172391B2
公开(公告)日：2001-01-09
申请号：US09140972
申请日：1998-08-27
申请人： Bernd Goebel , Emmerich Bertagnolli , Helmut Klose
发明人： Bernd Goebel , Emmerich Bertagnolli , Helmut Klose
IPC分类号： H01L2978
CPC分类号： H01L27/10841 , H01L21/76237 , H01L27/10808 , H01L27/10823 , H01L27/10876 , H01L29/4232 , H01L29/4238
摘要： An element that prevents the formation of a channel is arranged in a level of the channel region (Kaa) at one of two opposite sidewalls of a semiconductor structure that has a source/drain region (S/D1a) and a channel region (Kaa) of a vertical selection transistor arranged therebelow. The source/drain region as well as a respective word line (W1a) adjoin at both sidewalls. For folded bit lines (B1a), respectively two word lines (W1a) can be formed in the trenches (G2a). The elements of semiconductor structures neighboring along one of the trenches (G2a) are then arranged in alternation at a sidewall of the trench (G2a) and at a sidewall of a neighboring trench (D2a). A storage capacitor can be arranged over a substrate (1a) or can be buried in the substrate (1a). The connection of the selection transistor to a bit line (B1a) can ensue in many ways.
摘要翻译：防止形成通道的元件被布置在具有源极/漏极区域（S / D1a）和沟道区域（Kaa））的半导体结构的两个相对侧壁之一处的沟道区域（Kaa）的水平面中，的垂直选择晶体管。源极/漏极区域以及相应的字线（W1a）在两个侧壁处相邻。对于折叠位线（B1a），可以在沟槽（G2a）中分别形成两个字线（W1a）。然后沿沟槽（G2a）之一相邻的半导体结构的元件交替地布置在沟槽（G2a）的侧壁和相邻沟槽（D2a）的侧壁处。存储电容器可以布置在基板（1a）上方或者可以被埋在基板（1a）中。选择晶体管与位线（B1a）的连接可以以许多方式进行。

6. 发明授权

US06583464B1 Memory cell using amorphous material to stabilize the boundary face between polycrystalline semiconductor material of a capacitor and monocrystalline semiconductor material of a transistor 有权
标题翻译：使用非晶材料的存储单元稳定电容器的多晶半导体材料与晶体管的单晶半导体材料之间的边界面
公开(公告)号：US06583464B1
公开(公告)日：2003-06-24
申请号：US09201733
申请日：1998-11-30
申请人： Emmerich Bertagnolli , Gustav Beckmann , Michael Bianco , Helmut Klose
发明人： Emmerich Bertagnolli , Gustav Beckmann , Michael Bianco , Helmut Klose
IPC分类号： H01L27108
CPC分类号： H01L27/10861 , H01L27/10829
摘要： A memory cell array has memory cells in which there is an electrical connection between a polycrystalline semiconductor material of a capacitor electrode and a monocrystalline semiconductor region. Islands made of an amorphous material are disposed in a vicinity of the electrical connection between the polycrystalline semiconductor material and the monocrystalline semiconductor region. The islands are produced in particular by thermally breaking up an amorphous layer which has been formed by thermal oxidation. The memory cell array is in particular a DRAM array with a trench capacitor.
摘要翻译：存储单元阵列具有存储单元，其中在电容器电极的多晶半导体材料和单晶半导体区域之间存在电连接。由非晶材料制成的岛状物设置在多晶半导体材料和单晶半导体区域之间的电连接附近。这些岛特别是通过热分解由热氧化形成的非晶层而产生的。存储单元阵列特别是具有沟槽电容器的DRAM阵列。

7. 发明授权

US06211019B1 Read-only memory cell device and method for its production 有权
标题翻译：只读存储单元器件及其生产方法
公开(公告)号：US06211019B1
公开(公告)日：2001-04-03
申请号：US09130051
申请日：1998-08-06
申请人： Helmut Klose , Emmerich Bertagnolli
发明人： Helmut Klose , Emmerich Bertagnolli
IPC分类号： H01L218234
CPC分类号： H01L27/1126 , H01L27/112
摘要： A read-only memory cell device includes a substrate formed of semiconductor material and having a main area. Memory cells in the vicinity of the main area are disposed in matrix form in columns and rows in a cell field. Each memory cell has in each case at least one MOS transistor with a source region, a drain region, a channel region, a gate dielectric and a gate electrode. The MOS transistors of a column are connected in series one after the other. Each column is connected to a bit line and the gate electrodes of the MOS transistors of a row are connected to a word line. The source and drain regions of the MOS transistors of a column are formed in source/drain webs running substantially parallel to one another at a predetermined spacing, are electrically insulated from one another, are produced from the semiconductor material of the substrate and have a predetermined web depth, starting from the main area of the substrate. The word lines for connection of the gate electrodes of the MOS transistors run transversely with respect to the longitudinal direction of the source/drain webs.
摘要翻译：只读存储单元器件包括由半导体材料形成并具有主区域的衬底。在主区域附近的存储单元以矩阵形式在单元格区域中的列和行中排列。每个存储单元在每种情况下都具有至少一个具有源极区，漏极区，沟道区，栅极电介质和栅电极的MOS晶体管。柱的MOS晶体管一个接一个地串联连接。每列连接到位线，并且一行的MOS晶体管的栅电极连接到字线。柱的MOS晶体管的源极和漏极区域以预定的间隔彼此电绝缘的方式形成在源极/漏极幅片中，彼此电绝缘，由基板的半导体材料制成，并且具有预定的纸幅深度，从基材的主要区域开始。用于连接MOS晶体管晶体管的栅电极的字线相对于源极/漏极引线的纵向方向横向延伸。

8. 发明授权

US5741733A Method for the production of a three-dimensional circuit arrangement 失效
标题翻译：制作三维电路装置的方法
公开(公告)号：US5741733A
公开(公告)日：1998-04-21
申请号：US676164
申请日：1996-07-15
申请人： Emmerich Bertagnolli , Helmut Klose
发明人： Emmerich Bertagnolli , Helmut Klose
IPC分类号： H01L21/768 , H01L21/02 , H01L21/822 , H01L27/00 , H01L27/06 , H01L27/12 , H01L21/84 , H01L21/00
CPC分类号： H01L21/76898 , H01L21/8221 , H01L23/481 , H01L27/0688 , H01L2924/0002
摘要： To produce a three-dimensional circuit arrangement, a first substrate (1) is thinned, stacked onto a second substrate (2) and fixedly connected to the latter. The first substrate (1) and the second substrate (2) in this case each comprise circuit structures (12, 22) and metallization planes (13, 23). At least one first contact hole (16) and one second contact hole (4) are opened, which reach the metallization plane (13, 23) in the first substrate (1) and second substrate (2), respectively, the second contact hole (4) passing through the first substrate (1). The metallization planes (13, 23) of the two substrates (1, 2) are electrically connected to one another via a conductive layer (7).
摘要翻译： PCT No.PCT / DE95 / 00031 Sec。 371日期：1996年7月15日 102（e）日期1996年7月15日PCT提交1995年1月12日PCT公布。 WO95 / 19642 PCT出版物日期1995年7月20日为了制造三维电路装置，将第一衬底（1）变薄，层叠到第二衬底（2）上并且固定地连接到第二衬底（2）。在这种情况下，第一基板（1）和第二基板（2）分别包括电路结构（12,22）和金属化平面（13,23）。至少一个第一接触孔（16）和一个第二接触孔（4）分别到达第一基板（1）和第二基板（2）中的金属化平面（13,23），第二接触孔（4）穿过第一基板（1）。两个基板（1,2）的金属化平面（13,23）经由导电层（7）彼此电连接。

9. 发明授权

US5460982A Method for manufacturing lateral bipolar transistors 失效
标题翻译：制造横向双极晶体管的方法
公开(公告)号：US5460982A
公开(公告)日：1995-10-24
申请号：US261263
申请日：1994-06-14
申请人： Emmerich Bertagnolli , Helmut Klose
发明人： Emmerich Bertagnolli , Helmut Klose
IPC分类号： H01L21/316 , H01L21/331 , H01L29/73 , H01L21/265 , H01L21/20 , H01L21/302 , H01L21/76
CPC分类号： H01L29/66265 , H01L29/7317
摘要： Manufacturing method for lateral bipolar transistors, wherein a highly doped emitter zone and collector zone as well as a base terminal zone are manufactured in a region in the silicon layer of a SOI substrate having a basic doping. The zones are manufactured by implantation using a mask. A base zone is then produced by implantation of dopant using the mask. The base zone is produced between the emitter zone and the collector zone.
摘要翻译：在具有基本掺杂的SOI衬底的硅层中的区域中制造横向双极晶体管的制造方法，其中高掺杂发射极区和集电极区以及基极端区。这些区域通过使用掩模的植入来制造。然后通过使用掩模注入掺杂剂来制备基区。基区在发射区和集电区之间产生。

10. 发明授权

US5407843A Method for manufacturing lateral bipolar transistors 失效
标题翻译：制造横向双极晶体管的方法
公开(公告)号：US5407843A
公开(公告)日：1995-04-18
申请号：US261142
申请日：1994-06-14
申请人： Emmerich Bertagnolli , Helmut Klose
发明人： Emmerich Bertagnolli , Helmut Klose
IPC分类号： H01L21/331 , H01L29/73 , H01L21/265
CPC分类号： H01L29/66265 , H01L29/7317 , Y10S148/01
摘要： Method for manufacturing lateral bipolar transistors on a SOI substrate, whereby a basic doping for the conductivity type of emitter and collector is produced in the silicon layer of this SOI substrate, insulation regions are produced outside the region provided for the transistor, contact layers and dielectric layers are applied over a highly doped emitter zone and over a highly doped collector zone produced by a mask technique and are structured, so that a trench is located over a base zone to be produced and in the middle between emitter zone and collector zone, an auxiliary layer is then conformally deposited surface-wide with constant thickness, as a result whereof the trench having the width is reduced to a gap having the width of the base zone to be produced, an implantation of dopant for the operational sign of the conductivity of the base is undertaken through this gap, the regions situated laterally relative to this base zone are shielded by the vertical portions of the auxiliary layer that cover the sidewalls of the trench, via holes are then etched into the auxiliary layer and into the dielectric layer and metal contacts are produced for the electrical connection of emitter, collector and base.
摘要翻译：在SOI衬底上制造横向双极晶体管的方法，由此在该SOI衬底的硅层中产生用于发射极和集电极的导电类型的基本掺杂，在为晶体管，接触层和电介质提供的区域之外产生绝缘区层被施加在高度掺杂的发射极区域上并且通过掩模技术产生的高度掺杂的集电极区域上并且被构造为使得沟槽位于待产生的基极区域上方，并且位于发射极区域和收集器区域之间的中间，辅助层然后以恒定的厚度共面沉积在表面宽度上，其结果是具有宽度的沟槽被减小到具有要产生的基极区宽度的间隙，掺杂剂的注入用于电导率的操作符号通过该间隙进行基座，相对于该基部区域横向设置的区域被辅助件的垂直部分屏蔽覆盖沟槽侧壁的通孔然后被蚀刻到辅助层中并进入电介质层，并且制造金属触点用于发射极，集电极和基极的电连接。

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