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1. 发明申请

US20100291741A1 Method of fabricating array substrate 有权
标题翻译：阵列基板的制作方法
公开(公告)号：US20100291741A1
公开(公告)日：2010-11-18
申请号：US12591501
申请日：2009-11-20
申请人： Hee-Dong Choi , Sang-Gul Lee , Seong-Moh Seo , Jun-Min Lee , Byung-Chui Ahn
发明人： Hee-Dong Choi , Sang-Gul Lee , Seong-Moh Seo , Jun-Min Lee , Byung-Chui Ahn
IPC分类号： H01L21/336
CPC分类号： H01L27/1274 , H01L27/1214 , H01L27/1288 , H01L29/4908
摘要： A method of fabricating an array substrate includes sequentially forming a first metal layer, a first inorganic insulating layer and an intrinsic amorphous silicon layer on a substrate, the first metal layer including a first metallic material layer and a second metallic material layer; crystallizing the intrinsic amorphous silicon; forming a gate electrode, a gate line, a gate insulating layer and an active layer; forming an interlayer insulating layer including first and second contact holes respectively exposing both sides of the active layer; forming first and second ohmic contact patterns respectively contacting the both sides of the active layers, a source electrode, a drain electrode, and a data line connecting the source electrode; forming a passivation layer on the source electrode, the drain electrode; and forming a pixel electrode on the passivation layer and contacting the drain electrode.
摘要翻译：制造阵列基板的方法包括在基板上依次形成第一金属层，第一无机绝缘层和本征非晶硅层，所述第一金属层包括第一金属材料层和第二金属材料层; 结晶本征非晶硅; 形成栅电极，栅极线，栅绝缘层和有源层; 形成包括分别暴露有源层的两侧的第一和第二接触孔的层间绝缘层; 形成分别接触有源层的两侧的第一和第二欧姆接触图案，源电极，漏电极和连接源电极的数据线; 在源极上形成钝化层，漏电极; 以及在所述钝化层上形成像素电极并与所述漏电极接触。

2. 发明授权

US07910414B2 Method of fabricating array substrate 有权
标题翻译：阵列基板的制作方法
公开(公告)号：US07910414B2
公开(公告)日：2011-03-22
申请号：US12591501
申请日：2009-11-20
申请人： Hee-Dong Choi , Sang-Gul Lee , Seong-Moh Seo , Jun-Min Lee , Byung-Chul Ahn
发明人： Hee-Dong Choi , Sang-Gul Lee , Seong-Moh Seo , Jun-Min Lee , Byung-Chul Ahn
IPC分类号： H01L21/00 , H01L21/84
CPC分类号： H01L27/1274 , H01L27/1214 , H01L27/1288 , H01L29/4908
摘要： A method of fabricating an array substrate includes sequentially forming a first metal layer, a first inorganic insulating layer and an intrinsic amorphous silicon layer on a substrate, the first metal layer including a first metallic material layer and a second metallic material layer; crystallizing the intrinsic amorphous silicon; forming a gate electrode, a gate line, a gate insulating layer and an active layer; forming an interlayer insulating layer including first and second contact holes respectively exposing both sides of the active layer; forming first and second ohmic contact patterns respectively contacting the both sides of the active layers, a source electrode, a drain electrode, and a data line connecting the source electrode; forming a passivation layer on the source electrode, the drain electrode; and forming a pixel electrode on the passivation layer and contacting the drain electrode.
摘要翻译：制造阵列基板的方法包括在基板上依次形成第一金属层，第一无机绝缘层和本征非晶硅层，所述第一金属层包括第一金属材料层和第二金属材料层; 结晶本征非晶硅; 形成栅电极，栅极线，栅绝缘层和有源层; 形成包括分别暴露有源层的两侧的第一和第二接触孔的层间绝缘层; 形成分别接触有源层的两侧的第一和第二欧姆接触图案，源电极，漏电极和连接源电极的数据线; 在源极上形成钝化层，漏电极; 以及在所述钝化层上形成像素电极并与所述漏电极接触。

3. 发明申请

US20100117090A1 ARRAY SUBSTRATE INCLUDING THIN FILM TRANSISTOR AND METHOD OF FABRICATING THE SAME 有权
标题翻译：包括薄膜晶体管的阵列衬底及其制造方法
公开(公告)号：US20100117090A1
公开(公告)日：2010-05-13
申请号：US12486453
申请日：2009-06-17
申请人： Hyung-Gu Roh , Byung-Chul Ahn , Hee-Dong Choi , Seong-Moh Seo , Jun-Min Lee
发明人： Hyung-Gu Roh , Byung-Chul Ahn , Hee-Dong Choi , Seong-Moh Seo , Jun-Min Lee
IPC分类号： H01L33/00 , H01L21/336 , H01L21/268
CPC分类号： H01L27/1285 , H01L21/268 , H01L27/1288
摘要： A method of fabricating an array substrate includes: forming a gate line and a gate electrode connected to the gate line; forming a gate insulating layer on the gate line and the gate insulting layer; sequentially forming an intrinsic amorphous silicon pattern and an impurity-doped amorphous silicon pattern on the gate insulating layer over the gate electrode; forming a data line on the gate insulating layer and source and drain electrodes on the impurity-doped amorphous silicon pattern, the data line crossing the gate line to define a pixel region, and the source and drain electrodes spaced apart from each other; removing a portion of the impurity-doped amorphous silicon pattern exposed through the source and drain electrodes to define an ohmic contact layer; irradiating a first laser beam onto the intrinsic amorphous silicon pattern through the source and drain electrode to form an active layer including a first portion of polycrystalline silicon and a second portion of amorphous silicon at both sides of the first portion; forming a passivation layer on the data line, the source electrode and the drain electrode, the passivation layer having a drain contact hole exposing the drain electrode; and forming a pixel electrode on the passivation layer in the pixel region, the pixel electrode connected to the drain electrode through the drain contact hole.
摘要翻译：制造阵列基板的方法包括：形成栅极线和连接到栅极线的栅电极; 在栅极线和栅极绝缘层上形成栅极绝缘层; 在栅电极上的栅极绝缘层上依次形成本征非晶硅图案和杂质掺杂非晶硅图案; 在栅极绝缘层上形成数据线，在掺杂杂质的非晶硅图案上的源电极和漏极之间形成数据线，该数据线与栅极线交叉以限定一个像素区域，以及源极和漏极彼此间隔开; 去除通过源极和漏极暴露的杂质掺杂非晶硅图案的一部分，以限定欧姆接触层; 通过源极和漏极将第一激光束照射到本征非晶硅图案上，以在第一部分的两侧形成包括多晶硅的第一部分和非晶硅的第二部分的有源层; 在数据线上形成钝化层，源电极和漏电极，钝化层具有暴露漏电极的漏极接触孔; 以及在所述像素区域中的钝化层上形成像素电极，所述像素电极通过所述漏极接触孔与所述漏电极连接。

4. 发明授权

US08021937B2 Array substrate including thin film transistor and method of fabricating the same 有权
标题翻译：阵列基板包括薄膜晶体管及其制造方法
公开(公告)号：US08021937B2
公开(公告)日：2011-09-20
申请号：US12486453
申请日：2009-06-17
申请人： Hyung-Gu Roh , Byung-Chul Ahn , Hee-Dong Choi , Seong-Moh Seo , Jun-Min Lee
发明人： Hyung-Gu Roh , Byung-Chul Ahn , Hee-Dong Choi , Seong-Moh Seo , Jun-Min Lee
IPC分类号： H01L21/336
CPC分类号： H01L27/1285 , H01L21/268 , H01L27/1288
摘要： A method of fabricating an array substrate includes: forming a gate line and a gate electrode connected to the gate line; forming a gate insulating layer on the gate line and the gate insulting layer; sequentially forming an intrinsic amorphous silicon pattern and an impurity-doped amorphous silicon pattern on the gate insulating layer over the gate electrode; forming a data line on the gate insulating layer and source and drain electrodes on the impurity-doped amorphous silicon pattern, the data line crossing the gate line to define a pixel region, and the source and drain electrodes spaced apart from each other; removing a portion of the impurity-doped amorphous silicon pattern exposed through the source and drain electrodes to define an ohmic contact layer; irradiating a first laser beam onto the intrinsic amorphous silicon pattern through the source and drain electrode to form an active layer including a first portion of polycrystalline silicon and a second portion of amorphous silicon at both sides of the first portion; forming a passivation layer on the data line, the source electrode and the drain electrode, the passivation layer having a drain contact hole exposing the drain electrode; and forming a pixel electrode on the passivation layer in the pixel region, the pixel electrode connected to the drain electrode through the drain contact hole.
摘要翻译：制造阵列基板的方法包括：形成栅极线和连接到栅极线的栅电极; 在栅极线和栅极绝缘层上形成栅极绝缘层; 在栅电极上的栅极绝缘层上依次形成本征非晶硅图案和杂质掺杂非晶硅图案; 在栅极绝缘层上形成数据线，在掺杂杂质的非晶硅图案上的源电极和漏极之间形成数据线，该数据线与栅极线交叉以限定一个像素区域，以及源极和漏极彼此间隔开; 去除通过源极和漏极暴露的杂质掺杂非晶硅图案的一部分，以限定欧姆接触层; 通过源极和漏极将第一激光束照射到本征非晶硅图案上，以在第一部分的两侧形成包括多晶硅的第一部分和非晶硅的第二部分的有源层; 在数据线上形成钝化层，源电极和漏电极，钝化层具有暴露漏电极的漏极接触孔; 以及在所述像素区域中的钝化层上形成像素电极，所述像素电极通过所述漏极接触孔与所述漏电极连接。

5. 发明申请

US20110018000A1 DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME 有权
标题翻译：显示装置及其制造方法
公开(公告)号：US20110018000A1
公开(公告)日：2011-01-27
申请号：US12813308
申请日：2010-06-10
申请人： Hee-Dong CHOI , Hye-Young Choi , Jun-Min Lee
发明人： Hee-Dong CHOI , Hye-Young Choi , Jun-Min Lee
IPC分类号： H01L33/16 , H01L21/336
CPC分类号： H01L27/1259 , H01L27/1214 , H01L27/1274 , H01L27/1288
摘要： Disclosed is a method of fabricating a display device that includes forming a buffer layer; forming a gate electrode of extrinsic polycrystalline silicon, a gate insulating layer, an active layer of intrinsic polycrystalline silicon and an auxiliary active layer of intrinsic amorphous silicon on the buffer layer; forming an ohmic contact layer of extrinsic amorphous silicon and contacting the auxiliary active layer, source and drain electrodes and a data line; patterning a first passivation layer, an insulating interlayer and the gate insulating layer to form a gate contact hole exposing the gate electrode; forming a gate line on the first passivation layer, made of a metal material, and contacting the gate electrode through the gate contact hole; forming a second passivation layer on the gate line; patterning the first and second passivation layers to form a drain contact hole exposing the drain electrode; and forming a pixel electrode on the second passivation layer in the pixel region and contacting the drain electrode through the drain contact hole.
摘要翻译：公开了一种制造显示装置的方法，包括形成缓冲层; 在绝缘多晶硅上形成栅电极，栅极绝缘层，本征多晶硅的有源层和本征非晶硅的辅助有源层在缓冲层上; 形成外部非晶硅的欧姆接触层，并与辅助有源层，源极和漏极以及数据线接触; 图案化第一钝化层，绝缘中间层和栅极绝缘层，以形成暴露栅电极的栅极接触孔; 在所述第一钝化层上形成由金属材料制成的栅极线，并且通过所述栅极接触孔与所述栅电极接触; 在栅极线上形成第二钝化层; 图案化第一和第二钝化层以形成暴露漏电极的漏极接触孔; 以及在所述像素区域中的所述第二钝化层上形成像素电极，并且通过所述漏极接触孔与所述漏电极接触。

6. 发明授权

US08198631B2 Display device and method of fabricating the same 有权
标题翻译：显示装置及其制造方法
公开(公告)号：US08198631B2
公开(公告)日：2012-06-12
申请号：US12813308
申请日：2010-06-10
申请人： Hee-Dong Choi , Hye-Young Choi , Jun-Min Lee
发明人： Hee-Dong Choi , Hye-Young Choi , Jun-Min Lee
IPC分类号： H01L29/04 , H01L21/336
CPC分类号： H01L27/1259 , H01L27/1214 , H01L27/1274 , H01L27/1288
摘要： Disclosed is a method of fabricating a display device that includes forming a buffer layer; forming a gate electrode of extrinsic polycrystalline silicon, a gate insulating layer, an active layer of intrinsic polycrystalline silicon and an auxiliary active layer of intrinsic amorphous silicon on the buffer layer; forming an ohmic contact layer of extrinsic amorphous silicon and contacting the auxiliary active layer, source and drain electrodes and a data line; patterning a first passivation layer, an insulating interlayer and the gate insulating layer to form a gate contact hole exposing the gate electrode; forming a gate line on the first passivation layer, made of a metal material, and contacting the gate electrode through the gate contact hole; forming a second passivation layer on the gate line; patterning the first and second passivation layers to form a drain contact hole exposing the drain electrode; and forming a pixel electrode on the second passivation layer in the pixel region and contacting the drain electrode through the drain contact hole.
摘要翻译：公开了一种制造显示装置的方法，包括形成缓冲层; 在绝缘多晶硅上形成栅电极，栅极绝缘层，本征多晶硅的有源层和本征非晶硅的辅助有源层在缓冲层上; 形成外部非晶硅的欧姆接触层，并与辅助有源层，源极和漏极以及数据线接触; 图案化第一钝化层，绝缘中间层和栅极绝缘层，以形成暴露栅电极的栅极接触孔; 在所述第一钝化层上形成由金属材料制成的栅极线，并且通过所述栅极接触孔与所述栅电极接触; 在栅极线上形成第二钝化层; 图案化第一和第二钝化层以形成暴露漏电极的漏极接触孔; 以及在所述像素区域中的所述第二钝化层上形成像素电极，并且通过所述漏极接触孔与所述漏电极接触。

7. 发明授权

US10062270B2 Alarm system response time reduction 有权
公开(公告)号：US10062270B2
公开(公告)日：2018-08-28
申请号：US15432316
申请日：2017-02-14
申请人： Jay Skolnik , Daniel Skolnik , Connor Harness , Jun-Min Lee
发明人： Jay Skolnik , Daniel Skolnik , Connor Harness , Jun-Min Lee
IPC分类号： G08B25/14 , G08B19/00 , G08B25/10 , G08B25/00 , G08B27/00
CPC分类号： G08B25/14 , G08B25/006 , G08B27/003
摘要： An alarm system is monitored by an alert system that supplements the capabilities of the alarm system. The sensors, such as door, window, fire, and CO sensor can be monitored by the alarm system which can raise an alarm when a sensor is triggered. The alert system detects that the alarm system has raised an alarm. The alert system can then communicate the alarm locally to other alert system installations. People at those other alert system installations are thereby alerted to the alarm and can respond to it.

8. 发明申请

US20170236404A1 ALARM SYSTEM RESPONSE TIME REDUCTION 审中-公开
公开(公告)号：US20170236404A1
公开(公告)日：2017-08-17
申请号：US15432316
申请日：2017-02-14
申请人： Jay Skolnik , Daniel Skolnik , Connor Harness , Jun-Min Lee
发明人： Jay Skolnik , Daniel Skolnik , Connor Harness , Jun-Min Lee
IPC分类号： G08B25/14 , G08B19/00 , G08B25/10
CPC分类号： G08B25/14 , G08B25/006 , G08B27/003
摘要： An alarm system is monitored, by an alert system that supplements the capabilities of the alarm system. The sensors, such as door, window, fire, and CO sensor can be monitored by the alarm system which can raise an alarm when a sensor is triggered. The alert system detects that the alarm system has raised an alarm. The alert system can then communicate the alarm locally to other alert system installations. People at those other alert system installations are thereby alerted to the alarm and can respond to it.

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