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1. 发明授权

US07910414B2 Method of fabricating array substrate 有权
标题翻译：阵列基板的制作方法
公开(公告)号：US07910414B2
公开(公告)日：2011-03-22
申请号：US12591501
申请日：2009-11-20
申请人： Hee-Dong Choi , Sang-Gul Lee , Seong-Moh Seo , Jun-Min Lee , Byung-Chul Ahn
发明人： Hee-Dong Choi , Sang-Gul Lee , Seong-Moh Seo , Jun-Min Lee , Byung-Chul Ahn
IPC分类号： H01L21/00 , H01L21/84
CPC分类号： H01L27/1274 , H01L27/1214 , H01L27/1288 , H01L29/4908
摘要： A method of fabricating an array substrate includes sequentially forming a first metal layer, a first inorganic insulating layer and an intrinsic amorphous silicon layer on a substrate, the first metal layer including a first metallic material layer and a second metallic material layer; crystallizing the intrinsic amorphous silicon; forming a gate electrode, a gate line, a gate insulating layer and an active layer; forming an interlayer insulating layer including first and second contact holes respectively exposing both sides of the active layer; forming first and second ohmic contact patterns respectively contacting the both sides of the active layers, a source electrode, a drain electrode, and a data line connecting the source electrode; forming a passivation layer on the source electrode, the drain electrode; and forming a pixel electrode on the passivation layer and contacting the drain electrode.
摘要翻译：制造阵列基板的方法包括在基板上依次形成第一金属层，第一无机绝缘层和本征非晶硅层，所述第一金属层包括第一金属材料层和第二金属材料层; 结晶本征非晶硅; 形成栅电极，栅极线，栅绝缘层和有源层; 形成包括分别暴露有源层的两侧的第一和第二接触孔的层间绝缘层; 形成分别接触有源层的两侧的第一和第二欧姆接触图案，源电极，漏电极和连接源电极的数据线; 在源极上形成钝化层，漏电极; 以及在所述钝化层上形成像素电极并与所述漏电极接触。

2. 发明申请

US20100291741A1 Method of fabricating array substrate 有权
标题翻译：阵列基板的制作方法
公开(公告)号：US20100291741A1
公开(公告)日：2010-11-18
申请号：US12591501
申请日：2009-11-20
申请人： Hee-Dong Choi , Sang-Gul Lee , Seong-Moh Seo , Jun-Min Lee , Byung-Chui Ahn
发明人： Hee-Dong Choi , Sang-Gul Lee , Seong-Moh Seo , Jun-Min Lee , Byung-Chui Ahn
IPC分类号： H01L21/336
CPC分类号： H01L27/1274 , H01L27/1214 , H01L27/1288 , H01L29/4908
摘要： A method of fabricating an array substrate includes sequentially forming a first metal layer, a first inorganic insulating layer and an intrinsic amorphous silicon layer on a substrate, the first metal layer including a first metallic material layer and a second metallic material layer; crystallizing the intrinsic amorphous silicon; forming a gate electrode, a gate line, a gate insulating layer and an active layer; forming an interlayer insulating layer including first and second contact holes respectively exposing both sides of the active layer; forming first and second ohmic contact patterns respectively contacting the both sides of the active layers, a source electrode, a drain electrode, and a data line connecting the source electrode; forming a passivation layer on the source electrode, the drain electrode; and forming a pixel electrode on the passivation layer and contacting the drain electrode.
摘要翻译：制造阵列基板的方法包括在基板上依次形成第一金属层，第一无机绝缘层和本征非晶硅层，所述第一金属层包括第一金属材料层和第二金属材料层; 结晶本征非晶硅; 形成栅电极，栅极线，栅绝缘层和有源层; 形成包括分别暴露有源层的两侧的第一和第二接触孔的层间绝缘层; 形成分别接触有源层的两侧的第一和第二欧姆接触图案，源电极，漏电极和连接源电极的数据线; 在源极上形成钝化层，漏电极; 以及在所述钝化层上形成像素电极并与所述漏电极接触。

3. 发明授权

US07842563B2 Thin film transistor, method of fabricating the same, and flat panel display using thin film transistor 有权
标题翻译：薄膜晶体管，其制造方法和使用薄膜晶体管的平板显示器
公开(公告)号：US07842563B2
公开(公告)日：2010-11-30
申请号：US11751902
申请日：2007-05-22
申请人： Jae-Bon Koo , Sang-Gul Lee
发明人： Jae-Bon Koo , Sang-Gul Lee
IPC分类号： H01L21/00
CPC分类号： H01L29/66757 , H01L29/4908 , H01L29/78621 , H01L29/78627
摘要： A thin film transistor may include an active layer formed on an insulating substrate and formed with source/drain regions and a channel region; a gate insulating film formed on the active layer; and a gate electrode formed on the gate insulating film. The gate electrode may be formed of a conductive metal film pattern and a conductive oxide film covering the conductive metal film pattern. The source/drain regions may include an LDD region, and the LDD region may at least partially overlap with the gate electrode.
摘要翻译：薄膜晶体管可以包括形成在绝缘基板上并形成有源极/漏极区域和沟道区域的有源层; 形成在有源层上的栅极绝缘膜; 以及形成在栅极绝缘膜上的栅电极。栅电极可以由导电金属膜图案和覆盖导电金属膜图案的导电氧化物膜形成。源极/漏极区域可以包括LDD区域，并且LDD区域可以至少部分地与栅电极重叠。

4. 发明申请

US20050110084A1 Thin film transistor, method of fabricating the same, and flat panel display using thin film transistor 有权
标题翻译：薄膜晶体管，其制造方法和使用薄膜晶体管的平板显示器
公开(公告)号：US20050110084A1
公开(公告)日：2005-05-26
申请号：US10992131
申请日：2004-11-19
申请人： Jae-Bon Koo , Sang-Gul Lee
发明人： Jae-Bon Koo , Sang-Gul Lee
IPC分类号： H01L21/28 , G02F1/136 , H01L21/3205 , H01L21/336 , H01L21/77 , H01L21/84 , H01L23/52 , H01L27/12 , H01L29/423 , H01L29/49 , H01L29/786 , H01L21/00 , H01L29/76 , H01L29/94
CPC分类号： H01L29/66757 , H01L29/4908 , H01L29/78621 , H01L29/78627
摘要： A thin film transistor may include an active layer formed on an insulating substrate and formed with source/drain regions and a channel region; a gate insulating film formed on the active layer; and a gate electrode formed on the gate insulating film. The gate electrode may be formed of a conductive metal film pattern and a conductive oxide film covering the conductive metal film pattern. The source/drain regions may include an LDD region, and the LDD region may at least partially overlap with the gate electrode.
摘要翻译：薄膜晶体管可以包括形成在绝缘基板上并形成有源极/漏极区域和沟道区域的有源层; 形成在有源层上的栅极绝缘膜; 以及形成在栅极绝缘膜上的栅电极。栅电极可以由导电金属膜图案和覆盖导电金属膜图案的导电氧化物膜形成。源极/漏极区域可以包括LDD区域，并且LDD区域可以至少部分地与栅电极重叠。

5. 发明授权

US06570183B1 Liquid crystal display for preventing galvanic phenomenon 有权
标题翻译：用于防止电流现象的液晶显示
公开(公告)号：US06570183B1
公开(公告)日：2003-05-27
申请号：US09435579
申请日：1999-11-08
申请人： Yong-In Park , Sang-Gul Lee , Jae-Beom Choi , Jong-Hoon Yi
发明人： Yong-In Park , Sang-Gul Lee , Jae-Beom Choi , Jong-Hoon Yi
IPC分类号： H01L2976
CPC分类号： H01L27/124 , H01L27/1214 , H01L27/1248 , H01L29/41733 , H01L29/458 , H01L29/66757 , H01L29/66765
摘要： A thin film transistor having a source/drain electrode on an insulating substrate is provided with a metal oxide layer interposed between a source/drain electrode and a metal connecting line. The formation of the metal oxide layer prevents the occurrence of the galvanic phenomenon.
摘要翻译：在绝缘基板上具有源极/漏极的薄膜晶体管设置有介于源极/漏极和金属连接线之间的金属氧化物层。金属氧化物层的形成防止了电偶现象的发生。

6. 发明授权

US07915102B2 Methods of fabricating thin film transistor and organic light emitting display device using the same 有权
标题翻译：制造薄膜晶体管的方法和使用其的有机发光显示装置
公开(公告)号：US07915102B2
公开(公告)日：2011-03-29
申请号：US11473455
申请日：2006-06-22
申请人： Eui-Hoon Hwang , Sang-Gul Lee
发明人： Eui-Hoon Hwang , Sang-Gul Lee
IPC分类号： H01L21/84
CPC分类号： H01L27/1288 , H01L27/1214 , H01L27/127
摘要： Methods of fabricating a TFT and an OLED using the same are provided. The method of fabricating a CMOS TFT includes: preparing a substrate having first and second TFT regions; forming a gate electrode on the substrate; forming a gate insulating layer on the entire surface of the substrate including the gate electrode; forming a semiconductor layer on a predetermined region of the gate insulating layer using a mask; exposing the back of the mask using the gate electrode; injecting n-type impurity ions into the semiconductor layers of the first and second TFT regions using the back-exposed mask and forming a channel region and source and drain regions; ashing both sides of the back-exposed mask; injecting low concentration impurity ions into the semiconductor layers of the first and second TFT regions using the ashed mask and forming an LDD region; and injecting p-type impurity ions into the semiconductor layer of the second TFT region and forming source and drain regions.
摘要翻译：提供了使用其制造TFT和OLED的方法。制造CMOS TFT的方法包括：制备具有第一和第二TFT区域的衬底; 在所述基板上形成栅电极; 在包括所述栅电极的所述基板的整个表面上形成栅极绝缘层; 使用掩模在所述栅极绝缘层的预定区域上形成半导体层; 使用栅极暴露掩模的背面; 使用反向曝光掩模将n型杂质离子注入到第一和第二TFT区域的半导体层中，并形成沟道区域和源极和漏极区域; 灰化背面裸露的两面; 使用所述灰化掩模将低浓度杂质离子注入到所述第一和第二TFT区域的半导体层中，并形成LDD区域; 并将p型杂质离子注入到第二TFT区域的半导体层中并形成源区和漏区。

7. 发明申请

US20070224744A1 THIN FILM TRANSISTOR, METHOD OF FABRICATING THE SAME, AND FLAT PANEL DISPLAY USING THIN FILM TRANSISTOR 有权
标题翻译：薄膜晶体管，其制造方法和使用薄膜晶体管的平板显示器
公开(公告)号：US20070224744A1
公开(公告)日：2007-09-27
申请号：US11751902
申请日：2007-05-22
申请人： Jae-Bon Koo , Sang-Gul Lee
发明人： Jae-Bon Koo , Sang-Gul Lee
IPC分类号： H01L21/336
CPC分类号： H01L29/66757 , H01L29/4908 , H01L29/78621 , H01L29/78627
摘要： A thin film transistor may include an active layer formed on an insulating substrate and formed with source/drain regions and a channel region; a gate insulating film formed on the active layer; and a gate electrode formed on the gate insulating film. The gate electrode may be formed of a conductive metal film pattern and a conductive oxide film covering the conductive metal film pattern. The source/drain regions may include an LDD region, and the LDD region may at least partially overlap with the gate electrode.
摘要翻译：薄膜晶体管可以包括形成在绝缘基板上并形成有源极/漏极区域和沟道区域的有源层; 形成在有源层上的栅极绝缘膜; 以及形成在栅极绝缘膜上的栅电极。栅电极可以由导电金属膜图案和覆盖导电金属膜图案的导电氧化物膜形成。源极/漏极区域可以包括LDD区域，并且LDD区域可以至少部分地与栅电极重叠。

8. 发明授权

US06338987B1 Method for forming polycrystalline silicon layer and method for fabricating thin film transistor 有权
标题翻译：多晶硅层的形成方法及薄膜晶体管的制造方法
公开(公告)号：US06338987B1
公开(公告)日：2002-01-15
申请号：US09377440
申请日：1999-08-19
申请人： Jong-Hoon Yi , Sang-Gul Lee , Won-Kyu Park
发明人： Jong-Hoon Yi , Sang-Gul Lee , Won-Kyu Park
IPC分类号： H01L2100
CPC分类号： H01L21/02667 , H01L21/02532 , H01L21/2022 , H01L27/12 , H01L27/124 , H01L27/1277 , H01L27/1285 , H01L29/41733 , H01L29/66757 , H01L29/78675
摘要： A method for forming a polycrystalline silicon layer for TFT according to the present invention includes steps of: depositing an amorphous silicon layer and a silicon oxidation layer on a substrate in this order; and implanting semiconductor ions into the amorphous silicon layer and the silicon oxidation layer while heating the substrate, thereby converting the amorphous silicon layer into a polycrystalline silicon layer, and forming an amorphous oxidation layer between the amorphous silicon layer and the silicon oxidation layer.
摘要翻译：根据本发明的用于形成TFT的多晶硅层的方法包括以下步骤：在基板上依次沉积非晶硅层和硅氧化层; 以及在加热所述衬底的同时将半导体离子注入到所述非晶硅层和所述硅氧化层中，从而将所述非晶硅层转化为多晶硅层，以及在所述非晶硅层和所述硅氧化层之间形成非晶氧化层。

9. 发明授权

US08273638B2 Thin film transistor using a metal induced crystallization process and method for fabricating the same and active matrix flat panel display using the thin film transistor 有权
标题翻译：使用金属诱导结晶工艺的薄膜晶体管及其制造方法以及使用该薄膜晶体管的有源矩阵平板显示器
公开(公告)号：US08273638B2
公开(公告)日：2012-09-25
申请号：US11968365
申请日：2008-01-02
申请人： Jae-Bon Koo , Sang-Gul Lee
发明人： Jae-Bon Koo , Sang-Gul Lee
IPC分类号： C30B1/08 , C09K19/00
CPC分类号： H01L27/12 , H01L21/02422 , H01L21/02532 , H01L21/02672 , H01L27/1277 , H01L29/78603
摘要： Provided is a thin film transistor that may be manufactured using Metal Induced Crystallization (MIC) and method for fabricating the same. Also provided is an active matrix flat panel display using the thin film transistor, which may be created by forming a crystallization inducing metal layer below a buffer layer and diffusing the crystallization inducing metal layer. The thin film transistor may include a crystallization inducing metal layer formed on an insulating substrate, a buffer layer formed on the crystallization inducing metal layer, and an active layer formed on the buffer layer and including source/drain regions, and including polycrystalline silicon crystallized by the MIC process.
摘要翻译：提供了可以使用金属诱导结晶（MIC）制造的薄膜晶体管及其制造方法。还提供了使用薄膜晶体管的有源矩阵平板显示器，其可以通过在缓冲层下方形成结晶诱导金属层并扩散结晶诱导金属层来产生。薄膜晶体管可以包括形成在绝缘基板上的结晶诱导金属层，形成在结晶诱导金属层上的缓冲层，以及形成在缓冲层上并包括源极/漏极区域的有源层，并且包括由 MIC过程。

10. 发明申请

US20050116305A1 Thin film transistor 审中-公开
标题翻译：薄膜晶体管
公开(公告)号：US20050116305A1
公开(公告)日：2005-06-02
申请号：US10992645
申请日：2004-11-22
申请人： Eui-Hoon Hwang , Sang-Gul Lee , Deuk-Jong Kim
发明人： Eui-Hoon Hwang , Sang-Gul Lee , Deuk-Jong Kim
IPC分类号： H01L21/336 , H01L29/423 , H01L29/786 , H01L21/335 , H01L21/338 , H01L21/8232 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/66757 , H01L29/42384 , H01L29/66765 , H01L29/78609 , H01L29/78675 , H01L29/78678
摘要： A thin film transistor according to the present invention may include a gate insulating layer; and a lower pattern placed below the gate insulating layer to contact therewith and having an edge with a taper angle of at most about 80°. With this design, dielectric strength of the gate insulating layer can be enhanced. The lower pattern can be a gate electrode layer.
摘要翻译：根据本发明的薄膜晶体管可以包括栅极绝缘层; 以及放置在栅极绝缘层下方以与其接触并具有至多约80°的锥角的边缘的下部图案。通过这种设计，可以提高栅极绝缘层的介电强度。下图案可以是栅极电极层。

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