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1. 发明申请

US20100287447A1 MEMORY SYSTEM IDENTIFYING AND CORRECTING ERASURE USING REPEATED APPLICATION OF READ OPERATION 审中-公开
标题翻译：使用重复读取操作的存储系统识别和校正擦除
公开(公告)号：US20100287447A1
公开(公告)日：2010-11-11
申请号：US12773179
申请日：2010-05-04
申请人： Hee Seok EUN , Jae Hong KIM , Seung-Hwan SONG , Ho-Chul LEE , Yong June KIM , Han Woong YOO , Jun Jin KONG
发明人： Hee Seok EUN , Jae Hong KIM , Seung-Hwan SONG , Ho-Chul LEE , Yong June KIM , Han Woong YOO , Jun Jin KONG
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： H03M13/455 , G06F11/1068 , G11C16/26
摘要： Provided is a read method for a memory system. The read method determines whether a read data error is correctable. The read method applies a plurality of read operations at a set read voltage level to identify erasure candidates, when the error is uncorrectable. The read method performs erasure decoding using an error correction code or an error detection code for the erasure candidates.
摘要翻译：提供了一种用于存储器系统的读取方法。读取方法确定读取数据错误是否可校正。读取方法以设定的读取电压电平施加多个读取操作以识别擦除候选，当错误是不可校正的。读取方法使用用于擦除候选的纠错码或错误检测码来执行擦除解码。

2. 发明申请

US20100296350A1 METHOD OF SETTING READ VOLTAGE MINIMIZING READ DATA ERRORS 有权
标题翻译：设置读取电压最小化读取数据错误的方法
公开(公告)号：US20100296350A1
公开(公告)日：2010-11-25
申请号：US12774814
申请日：2010-05-06
申请人： Yong June KIM , Jae Hong KIM , Jun Jin KONG , Hong Rak SON , Seung-Hwan SONG
发明人： Yong June KIM , Jae Hong KIM , Jun Jin KONG , Hong Rak SON , Seung-Hwan SONG
IPC分类号： G11C7/06
CPC分类号： G11C11/5642 , G11C29/00 , G11C2211/5634
摘要： A method setting a read voltage to minimize data read errors in a semiconductor memory device including multi-bit memory cells. In the method, a read voltage associated with a minimal number of read data error is set based on a statistic value of a voltage distribution corresponding to each one of a plurality of voltage states.
摘要翻译：一种设置读取电压以最小化包括多位存储器单元的半导体存储器件中的数据读取错误的方法。在该方法中，基于与多个电压状态中的每一个相对应的电压分布的统计值来设置与最小数量的读取数据错误相关联的读取电压。

3. 发明申请

US20100118608A1 NON-VOLATILE MEMORY DEVICE, MEMORY CARD AND SYSTEM, AND METHOD DETERMINING READ VOLTAGE IN SAME 失效
标题翻译：非易失性存储器件，存储卡和系统以及确定读取电压的方法
公开(公告)号：US20100118608A1
公开(公告)日：2010-05-13
申请号：US12614545
申请日：2009-11-09
申请人： Seung-Hwan SONG , Jaehong KIM , Kyoung Lae CHO , Yong June KIM , Jun Jin KONG , Jong Han KIM
发明人： Seung-Hwan SONG , Jaehong KIM , Kyoung Lae CHO , Yong June KIM , Jun Jin KONG , Jong Han KIM
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/26 , G11C11/5642 , G11C29/00 , G11C2211/5634
摘要： A non-volatile semiconductor memory device and related method of determining a read voltage are disclosed. The non-volatile semiconductor memory device includes; a memory cell array including a plurality of memory cells, a read voltage determination unit configured to determine an optimal read voltage by comparing reference data obtained during a program operation with comparative data obtained during a subsequent read operation and changing a current read voltage to a new read voltage based on a result of the comparison, and a read voltage generation unit configured to generate the new read voltage in response to a read voltage control signal provided by the read voltage determination unit.
摘要翻译：公开了一种非易失性半导体存储器件及确定读取电压的相关方法。非易失性半导体存储器件包括：包括多个存储单元的存储单元阵列，读电压确定单元，被配置为通过将在编程操作期间获得的参考数据与在随后的读取操作期间获得的比较数据进行比较来确定最佳读取电压，并将当前读取电压改变为新的基于比较结果的读取电压和读取电压生成单元，被配置为响应于由读取电压确定单元提供的读取电压控制信号而产生新的读取电压。

4. 发明申请

US20100174966A1 DEVICE AND METHOD PROVIDING 1-BIT ERROR CORRECTION 有权
标题翻译：提供1位错误校正的设备和方法
公开(公告)号：US20100174966A1
公开(公告)日：2010-07-08
申请号：US12651586
申请日：2010-01-04
申请人： Yong June KIM , Jae Hong KIM , Jun Jin KONG
发明人： Yong June KIM , Jae Hong KIM , Jun Jin KONG
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： G06F11/1008 , H03M13/1105 , H03M13/1108
摘要： A 1-bit error correction method is provided. In the method, a variable node at which an error has occurred is detected based on a number of unsatisfied check nodes that do not satisfy a parity condition among check nodes connected to each of variable nodes and an error in a bit corresponding to the detected variable node is corrected.
摘要翻译：提供1位纠错方法。在该方法中，基于在连接到每个可变节点的校验节点中不满足奇偶校验条件的不满足校验节点的数量和对应于检测变量的位的错误来检测发生错误的变量节点节点被更正。

5. 发明申请

US20090276687A1 METHOD OF ENCODING AND DECODING MULTI-BIT LEVEL DATA 有权
标题翻译：编码和解码多级数据的方法
公开(公告)号：US20090276687A1
公开(公告)日：2009-11-05
申请号：US12429718
申请日：2009-04-24
申请人： Yong June KIM , Jae Hong KIM , Kyoung Lae CHO , Jun Jin KONG , Ki Jun LEE , Ha Bong CHUNG , Keun Sung CHOI
发明人： Yong June KIM , Jae Hong KIM , Kyoung Lae CHO , Jun Jin KONG , Ki Jun LEE , Ha Bong CHUNG , Keun Sung CHOI
IPC分类号： H03M13/19 , G06F11/10 , H03M13/45
CPC分类号： H03M13/451 , G06F11/1072
摘要： A method of encoding multi-bit level data includes: determining a range of an error pattern generated according to a transmission symbol, encoding an M-bit level of a P-bit level corresponding to the transmission symbol based on the range of the error pattern, and excluding encoding of a P-M bit level of the P-bit level. The variable P is a natural number of a value at least two, and the variable M is a natural number less than P.
摘要翻译：一种编码多位电平数据的方法包括：根据传输符号确定产生的误差模式的范围，根据误差模式的范围来编码与发送符号对应的P位电平的M位电平，并且排除P位电平的PM位电平的编码。变量P是至少为2的值的自然数，变量M是小于P的自然数。

6. 发明申请

US20110040929A1 METHOD AND APPARATUS FOR MODIFYING DATA SEQUENCES STORED IN MEMORY DEVICE 审中-公开
标题翻译：用于修改存储器件中存储的数据序列的方法和装置
公开(公告)号：US20110040929A1
公开(公告)日：2011-02-17
申请号：US12796896
申请日：2010-06-09
申请人： Yong June KIM , Jae Hong KIM , Jun Jin KONG
发明人： Yong June KIM , Jae Hong KIM , Jun Jin KONG
IPC分类号： G06F12/02 , G06F12/00
CPC分类号： G06F11/10
摘要： A method of modifying data sequences in a memory system comprises receiving program data having a first data sequence, and determining whether the received first data sequence matches one of “m” predefined sequences stored in the memory system. The method further comprises replacing the received first data sequence with a replacement sequence upon determining that the received first data sequence matches one of the “m” predefined sequences, and outputting the replacement sequence from the memory system. The replacement sequence typically comprises pattern bits indicating a pattern of the first data sequence and location bits indicating a start location of the first data sequence.
摘要翻译：一种在存储器系统中修改数据序列的方法包括：接收具有第一数据序列的程序数据，以及确定所接收的第一数据序列是否匹配存储在存储器系统中的“m”个预定序列之一。该方法还包括在确定所接收的第一数据序列与“m”个预定义序列中的一个匹配并从存储器系统输出替换序列时，用替换序列替换所接收的第一数据序列。替换序列通常包括指示第一数据序列的模式的模式比特和指示第一数据序列的开始位置的位置比特。

7. 发明申请

US20100088574A1 DATA STORAGE SYSTEM AND DEVICE WITH RANDOMIZER/DE-RANDOMIZER 有权
标题翻译：数据存储系统和带有RANDOMIZER / DE-RANDOMIZER的设备
公开(公告)号：US20100088574A1
公开(公告)日：2010-04-08
申请号：US12573246
申请日：2009-10-05
申请人： Yong June KIM , Jun Jin KONG , Jae Hong KIM , Kyoung Lae CHO
发明人： Yong June KIM , Jun Jin KONG , Jae Hong KIM , Kyoung Lae CHO
IPC分类号： G06F11/10 , G06F12/00
CPC分类号： G06F11/1008
摘要： A data storage device receives write data and includes a controller configured to determine a characteristic of the write data and provide a first control signal in response to the determined characteristic, a randomizer configured to selectively randomize or not randomize the write data in response to the first control signal to thereby generate randomized write data, and a data storage unit configured to store the randomized write data.
摘要翻译：数据存储装置接收写入数据，并且包括控制器，被配置为确定写入数据的特性并响应于所确定的特性提供第一控制信号;随机化器，被配置为响应于第一个数据，选择性地随机化或不使写入数据随机化从而生成随机写入数据，以及数据存储单元，被配置为存储随机写入数据。

8. 发明申请

US20110216590A1 NONVOLATILE MEMORY DEVICE USING INTERLEAVING TECHNOLOGY AND PROGRAMMMING METHOD THEREOF 有权
标题翻译：使用交互技术的非易失性存储器件及其编程方法
公开(公告)号：US20110216590A1
公开(公告)日：2011-09-08
申请号：US13040626
申请日：2011-03-04
申请人： Hee Seok EUN , Yong June KIM
发明人： Hee Seok EUN , Yong June KIM
IPC分类号： G11C16/10
CPC分类号： G11C16/10
摘要： A nonvolatile memory device using interleaving technology is provided. The nonvolatile memory device includes a first controller configured to allocate one of 2N threshold voltage states to N-bit data where N is 2 or a natural number greater than 2, a second controller configured to set a difference between adjacent threshold voltage states among the 2N threshold voltage states so that the difference increases as a threshold voltage increases, and a programming unit configured to form a threshold voltage distribution state corresponding to the allocated threshold voltage state and to program the N-bit data to a multi-level cell. The second controller controls the difference between the adjacent threshold voltage states to equalize the number of read errors for all intersections among the 2N threshold voltage states at the end of life.
摘要翻译：提供了一种使用交错技术的非易失性存储器件。非易失性存储器件包括：第一控制器，被配置为将2N个阈值电压状态中的一个分配给N为2或大于2的自然数的N位数据;第二控制器，被配置为将2N的阈值电压状态之间的差设定为2N 阈值电压状态使得差异随阈值电压增加而增加，并且编程单元被配置为形成与所分配的阈值电压状态相对应的阈值电压分布状态，并将N位数据编程到多电平单元。第二控制器控制相邻阈值电压状态之间的差异，以平衡在寿命结束时的2N个阈值电压状态之间的所有交点的读取误差的数量。

9. 发明申请

US20120215963A1 Semiconductor Memory Systems that Include Data Randomizers and Related Devices, Controllers and Methods 审中-公开
标题翻译：包含数据随机器和相关器件，控制器和方法的半导体存储器系统
公开(公告)号：US20120215963A1
公开(公告)日：2012-08-23
申请号：US13303512
申请日：2011-11-23
申请人： Yong June KIM , Jung Soo CHUNG , Jun Jin KONG , Kyoung Lae CHO
发明人： Yong June KIM , Jung Soo CHUNG , Jun Jin KONG , Kyoung Lae CHO
IPC分类号： G06F12/00 , G06F12/02
CPC分类号： G06F13/16 , G11C7/1006
摘要： A semiconductor memory system and a programming method performed by the same. The semiconductor memory system includes: a semiconductor memory device having a storage area; a memory controller for controlling programming and reading of the storage area of the semiconductor memory device; at least one first randomizer for changing program data to be programmed into the storage area to first random data by using a first sequence in a first period; and at least one second randomizer for changing the first random data to second random data by using a second sequence in a second period that is different from the first period.
摘要翻译：半导体存储器系统及其编程方法。半导体存储器系统包括：具有存储区域的半导体存储器件; 用于控制半导体存储器件的存储区域的编程和读取的存储器控制器; 至少一个第一随机化器，用于通过在第一周期中使用第一序列来将要被编程到所述存储区域中的程序数据改变为第一随机数据; 以及至少一个第二随机化器，用于通过在与第一周期不同的第二周期中使用第二序列来将第一随机数据改变为第二随机数据。

10. 发明申请

US20120290783A1 MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME 审中-公开
标题翻译：包括其的存储器件和存储器系统
公开(公告)号：US20120290783A1
公开(公告)日：2012-11-15
申请号：US13467255
申请日：2012-05-09
申请人： Jung Soo CHUNG , Yong June KIM , Jun Jin KONG , Hongrak SON
发明人： Jung Soo CHUNG , Yong June KIM , Jun Jin KONG , Hongrak SON
IPC分类号： G06F12/00
CPC分类号： G11C7/1006 , G11C7/1012 , G11C11/5628 , G11C16/0483
摘要： A memory device including a randomizer and a memory system including the memory device are provided. The memory device includes: a randomizer including a sequence generator which generates a first sequence from a seed and a converter which converts the first sequence into a second sequence in response to a conversion factor, the randomizer randomizing data to be programmed using the second sequence and outputting the randomized data; and a storage area which receives the randomized data from the randomizer and storing the randomized data.
摘要翻译：提供了包括随机化器和包括存储器件的存储器系统的存储器件。存储装置包括：随机化器，其包括从种子生成第一序列的序列发生器和响应于转换因子将第一序列转换为第二序列的转换器，随机化器使用第二序列随机化要编程的数据，以及输出随机数据; 以及存储区域，其从随机化器接收随机数据并存储随机数据。

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