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    • 6. 发明授权
    • Stochastic reset circuit
    • 随机复位电路
    • US07265595B1
    • 2007-09-04
    • US11367139
    • 2006-03-03
    • Harold KutzTimothy WilliamsMorgan Whately
    • Harold KutzTimothy WilliamsMorgan Whately
    • H03L7/00
    • G11C7/20G11C5/143G11C8/10H03K17/223H03K2217/0036
    • In one embodiment, an integrated circuit device includes a power on reset (POR) circuit and a stochastic reset circuit configured to control enabling and disabling of the POR circuit. The stochastic reset circuit may have a value from among many possible values. The POR circuit may be enabled during a power up sequence of the device when the value of the stochastic reset during the power up is not a value designated to allow disabling of the POR circuit. The stochastic reset circuit may be configured such that the probability of the POR circuit being disabled during the power up is extremely low. After the power up sequence, the stochastic reset circuit may be controlled to allow disabling of the POR circuit to conserve power.
    • 在一个实施例中,集成电路器件包括上电复位(POR)电路和被配置为控制使能和禁止POR电路的随机复位电路。 随机复位电路可以具有许多可能值中的值。 当上电期间的随机复位值不是指定为允许禁止POR电路的值时,POR电路可以在器件的上电序列期间使能。 随机复位电路可以被配置为使得在上电期间POR电路被禁用的概率非常低。 在上电序列之后,可以控制随机复位电路以允许禁止POR电路以节省功率。
    • 9. 发明授权
    • Multifunction input/output circuit
    • 多功能输入/输出电路
    • US08217700B1
    • 2012-07-10
    • US12496590
    • 2009-07-01
    • Timothy WilliamsHarold KutzWarren SnyderDavid G. Wright
    • Timothy WilliamsHarold KutzWarren SnyderDavid G. Wright
    • H03L5/00
    • H03K19/1732
    • In one example, a chip includes integrated components configured to operate in the digital domain and the analog domain. An I/O pad located on the chip is configured to provide an external device access to the integrated components. A multifunction I/O interface cell between the I/O pad and the integrated components is configured to selectively connect different combinations of the components to the same I/O pad at different times. The multifunction I/O interface cell may include a first switching device connected to ground, a second switching device connected to a reference voltage, an analog input/output buffer, and a digital input/output buffer.
    • 在一个示例中,芯片包括被配置为在数字域和模拟域中操作的集成组件。 位于芯片上的I / O焊盘被配置为提供对集成部件的外部设备访问。 I / O焊盘和集成组件之间的多功能I / O接口单元被配置为在不同时间有选择地将组件的不同组合连接到相同的I / O焊盘。 多功能I / O接口单元可以包括连接到地的第一开关器件,连接到参考电压的第二开关器件,模拟输入/输出缓冲器和数字输入/输出缓冲器。
    • 10. 发明申请
    • STOCHASTIC RESET CIRCUIT
    • STOCHASTIC RESET电路
    • US20070205815A1
    • 2007-09-06
    • US11367139
    • 2006-03-03
    • Harold KutzTimothy WilliamsMorgan Whately
    • Harold KutzTimothy WilliamsMorgan Whately
    • H03L7/00
    • G11C7/20G11C5/143G11C8/10H03K17/223H03K2217/0036
    • In one embodiment, an integrated circuit device includes a power on reset (POR) circuit and a stochastic reset circuit configured to control enabling and disabling of the POR circuit. The stochastic reset circuit may have a value from among many possible values. The POR circuit may be enabled during a power up sequence of the device when the value of the stochastic reset during the power up is not a value designated to allow disabling of the POR circuit. The stochastic reset circuit may be configured such that the probability of the POR circuit being disabled during the power up is extremely low. After the power up sequence, the stochastic reset circuit may be controlled to allow disabling of the POR circuit to conserve power.
    • 在一个实施例中,集成电路器件包括上电复位(POR)电路和被配置为控制使能和禁止POR电路的随机复位电路。 随机复位电路可以具有许多可能值中的值。 当上电期间的随机复位值不是指定为允许禁止POR电路的值时,POR电路可以在器件的上电序列期间使能。 随机复位电路可以被配置为使得在上电期间POR电路被禁用的概率非常低。 在上电序列之后,可以控制随机复位电路以允许禁止POR电路以节省功率。