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1. 发明授权

US5742539A Integrated circuit for content addressable memory 失效
标题翻译：用于内容可寻址存储器的集成电路
公开(公告)号：US5742539A
公开(公告)日：1998-04-21
申请号：US767294
申请日：1996-12-16
申请人： Hajime Kinugasa , Naoki Kanazawa
发明人： Hajime Kinugasa , Naoki Kanazawa
IPC分类号： G11C15/04 , G11C8/14 , G11C15/00
CPC分类号： G11C8/14 , G11C15/00
摘要： A semiconductor integrated circuit includes a memory unit that receives data that is to be searched for and matches the data to be searched for with previously stored data; an encoder unit that receives and encodes the memory address of the matched data; and a decoder unit that receives and decodes the encoded memory address and accesses a predetermined word of the memory unit on the basis of the decoded memory address, and the encoder unit and the decoder unit are positioned adjacent to each other on a first side of the memory unit. Consequently, it is possible to connect with a shortened distance the memory address signal lines which are output from the encoder unit and input into the decoder unit to reduce the delay time caused by the wiring, thereby making it possible to improve the operational speed of the circuitry.
摘要翻译：半导体集成电路包括存储单元，其接收要搜索的数据并与先前存储的数据匹配要搜索的数据; 编码器单元，其接收并编码匹配数据的存储器地址; 以及解码器单元，其基于解码的存储器地址接收和解码编码的存储器地址并访问存储器单元的预定字，并且编码器单元和解码器单元在第一侧上彼此相邻地定位存储单元因此，可以将从编码器单元输出并输入到解码器单元的存储器地址信号线的缩短距离连接起来，以减少由布线引起的延迟时间，从而可以提高电路。

2. 发明申请

US20080041116A1 Rotating body control device and washing machine including the same 审中-公开
标题翻译：旋转体控制装置和包括其的洗衣机
公开(公告)号：US20080041116A1
公开(公告)日：2008-02-21
申请号：US11882096
申请日：2007-07-30
申请人： Naoki Kanazawa , Seilchiro Suzuki , Shoichi Matsui , Sadayuki Sato
发明人： Naoki Kanazawa , Seilchiro Suzuki , Shoichi Matsui , Sadayuki Sato
IPC分类号： D06F29/02 , G01M1/02
CPC分类号： G01M1/36 , D06F37/225
摘要： Disclosed herein are a rotating body control device and a washing machine. The rotating body control device includes: a balancing unit including an annular race which is integrally formed with the rotating body and is concentric with the rotation shaft of the rotating body and a plurality of rolling bodies which are movably seated in the race; a detecting unit detecting a bit signal, which is generated according to a variation in relative position between the rolling bodies seated in the race and the eccentric amount of the rotating body which occurs during the rotation of the rotating body; an analyzing unit which analyzes a variation in amplitude of the bit signal detected by the detecting unit; and a control unit which controls the rotation of the rotating body according to the analyzed result of the analyzing unit.
摘要翻译：这里公开了旋转体控制装置和洗衣机。旋转体控制装置包括：平衡单元，其包括与旋转体一体形成并与旋转体的旋转轴同心的环形座圈和可移动地安置在座圈中的多个滚动体; 检测单元，其检测位置信号，所述位信号是根据位于所述座圈中的滚动体之间的相对位置的变化和所述旋转体旋转期间发生的所述旋转体的偏心量而产生的; 分析单元，其分析由所述检测单元检测到的位信号的幅度变化; 以及控制单元，其根据分析单元的分析结果来控制旋转体的旋转。

3. 发明授权

US5619446A Hierarchical encoder including timing and data detection devices for a content addressable memory 失效
标题翻译：分层编码器，包括用于内容可寻址存储器的定时和数据检测装置
公开(公告)号：US5619446A
公开(公告)日：1997-04-08
申请号：US1751
申请日：1993-01-07
申请人： Masato Yoneda , Hiroshi Sasama , Naoki Kanazawa
发明人： Masato Yoneda , Hiroshi Sasama , Naoki Kanazawa
IPC分类号： G06F7/74 , G06F17/30 , G11C15/04 , G06F12/02
CPC分类号： G06F7/74 , G06F17/30982 , G11C15/04
摘要： A Content Addressable Memory (CAM) encoder comprises either a prefetch circuit or a flag data sense circuit. While a hit signal in the first priority subblock is being encoded, a hit signal in the second priority subblock can be stored in the prefetch circuit. Therefore, the encoding operation is performed without subblock-to-subblock switch time and enables a large capacity CAM to operate at high speeds. Moreover, a semiconductor integrated circuit detects the differential current between the current flowing through a first signal line and the reference current flowing through a second signal line. Moreover, it can operate as the number detection circuit to detect the number of hit signal in the subblock and operates as the timing control circuit to predict the termination of the encoding operation. Therefore, this semiconductor integrated circuit can allow the encoder to encode very efficiently at high speed.
摘要翻译：内容可寻址存储器（CAM）编码器包括预取电路或标志数据检测电路。当第一优先子块中的命中信号被编码时，第二优先级子块中的命中信号可被存储在预取电路中。因此，在没有子块到子块切换时间的情况下执行编码操作，并且能够使大容量CAM以高速运行。此外，半导体集成电路检测流过第一信号线的电流与流过第二信号线的参考电流之间的差分电流。此外，它可以作为数字检测电路来操作以检测子块中的命中信号的数量，并且用作定时控制电路以预测编码操作的终止。因此，该半导体集成电路可以允许编码器以高速非常有效地进行编码。

4. 发明授权

US06859376B2 Signal detection circuit for detecting multiple match in arranged signal lines 失效
标题翻译：用于在布置的信号线中检测多个匹配的信号检测电路
公开(公告)号：US06859376B2
公开(公告)日：2005-02-22
申请号：US10372230
申请日：2003-02-25
申请人： Naoki Kanazawa , Ryuichi Hata
发明人： Naoki Kanazawa , Ryuichi Hata
IPC分类号： G11C15/04 , G11C15/00
CPC分类号： G11C15/04
摘要： A signal detection circuit detects the presence or absence of signals having the same logic in a plurality of arranged signal lines, can be used as a circuit suitable for multi-hit detection in a content addressable memory. The signal detection circuit includes a first signal transmission line to transmit a first signal indicating the presence of two or more logical signals to be detected and a second signal transmission line to transmit a second signal indicating the presence of one or more of the logic signals to be detected. Each of the first and second signal transmission lines includes logic circuits. The signal detection circuit may have a hierarchical structure.
摘要翻译：信号检测电路检测在多个布置的信号线中是否存在具有相同逻辑的信号，可以用作适用于内容可寻址存储器中的多命中检测的电路。信号检测电路包括：第一信号传输线，用于发送指示要被检测的两个或多个逻辑信号的存在的第一信号;以及第二信号传输线，用于将指示存在一个或多个逻辑信号的第二信号传送到被检测。第一和第二信号传输线中的每一个包括逻辑电路。信号检测电路可以具有分层结构。

5. 发明授权

US06249449B1 Hierarchical encoder including timing and data detection devices for a content addressable memory 失效
标题翻译：分层编码器，包括用于内容可寻址存储器的定时和数据检测装置
公开(公告)号：US06249449B1
公开(公告)日：2001-06-19
申请号：US09428278
申请日：1999-10-27
申请人： Masato Yoneda , Hiroshi Sasama , Naoki Kanazawa
发明人： Masato Yoneda , Hiroshi Sasama , Naoki Kanazawa
IPC分类号： G11C1504
CPC分类号： G06F17/30982 , G06F7/74 , G11C15/04
摘要： An associative memory to which an encoder is applied has a plurality of associative memory subblocks each having a plurality of memory words. A hit flag resulting from match retrieval of retrieval data and the contents of the memory word, and an empty flag indicating whether or not the contents of the memory word are valid as objects for match retrieval are output from each memory word of each associative memory subblock. The address of an invalid memory word is readily controllable since the address of the memory word corresponding to the empty flag can be output as in a case where the address of the memory word corresponding to the hit flag is output. Moreover, since the hit flag and the empty flag are allowed to share a detection line with each other for common use in this encoder, the layout area of the associative memory is reduced and it is possible to build up a high-density associative memory.
摘要翻译：应用编码器的关联存储器具有多个相关存储器子块，每个具有多个存储器字。从检索数据的匹配检索和存储器字的内容产生的命中标记，以及指示存储器字的内容是否作为用于匹配检索的对象是否有效的空标志从每个相关存储器子块的每个存储器字输出。无效存储器字的地址容易被控制，因为与输出与命中标志相对应的存储器字的地址的情况下可以输出与空标志相对应的存储字的地址。此外，由于允许命中标志和空标志在该编码器中共同使用检测线，所以关联存储器的布局区域减少，并且可以建立高密度关联存储器。

6. 发明申请

US20060220676A1 Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：US20060220676A1
公开(公告)日：2006-10-05
申请号：US11393851
申请日：2006-03-31
申请人： Naoki Kanazawa
发明人： Naoki Kanazawa
IPC分类号： H03K19/003
CPC分类号： H03K5/2481 , H03K19/0016
摘要： A semiconductor device includes an internal circuit having a data holding circuit, and at least one leakage current cut-off circuit provided between the internal circuit and a power supply or a ground, and is capable of preventing data in the data holding circuit from being destroyed. A ground-side cut-off circuit includes a switch and a control circuit. The switch electrically connects or cuts a path between a source of a ground-side transistor of the internal circuit and the ground. The control circuit turns off the switch upon detecting that source potential of the ground-side transistor is substantially equal to that of the ground. Upon detecting that the source potential of the ground-side transistor rises to a predetermined potential lower than a potential necessary for holding the data in the data holding circuit, the control circuit turns on the switch.
摘要翻译：半导体器件包括具有数据保持电路的内部电路和设置在内部电路与电源或接地之间的至少一个漏电流切断电路，并且能够防止数据保持电路中的数据被破坏。接地侧截止电路包括开关和控制电路。该开关电连接或切断内部电路的接地侧晶体管的源极与地之间的路径。在检测到接地侧晶体管的源极电位基本上等于地电位的情况下，控制电路关断开关。当检测到接地侧晶体管的源极电位上升到比数据保持电路中保持数据所需的电位低的预定电位时，控制电路接通开关。

7. 发明授权

US06317383B1 Detection circuit for detecting timing of two node signals 有权
标题翻译：用于检测两个节点信号的定时的检测电路
公开(公告)号：US06317383B1
公开(公告)日：2001-11-13
申请号：US09534533
申请日：2000-03-27
申请人： Naoki Kanazawa
发明人： Naoki Kanazawa
IPC分类号： G11C800
CPC分类号： G11C7/22
摘要： A detection circuit detects the timings of transitions of two node signals. The detection circuit has two nodes A and B, a P-channel transistor and an N-channel transistor provided between a power supply and a ground so as to be connected in series in the order of the power supply, the P-channel transistor, and the N-channel transistor, and each of the gates thereof is connected to each of the two nodes A and B, and a floating-preventing latch circuit connected to a connection node formed by the P-channel transistor and the N-channel transistor. Particularly, in the detection circuit, the gate of the P-channel transistor is connected to the node A and the gate of the N-channel transistor is connected to the node B in which the two node signals A and B are initially LOW, the node signal A rises to HIGH first, then the node signal B rises to HIGH, the node signals A and B remain HIGH for a predetermined period, the node signal B falls to LOW first, and then the node signal A falls to LOW. Also, a detection circuit for detecting the timing of charge and discharge completion of the bit line for use in a semiconductor memory according to the present invention is provided.
摘要翻译：检测电路检测两个节点信号的转换的定时。检测电路具有两个节点A和B，一个P沟道晶体管和一个设置在电源和地之间的N沟道晶体管，以按照电源顺序串联连接，P沟道晶体管，和N沟道晶体管，并且其栅极中的每一个连接到两个节点A和B中的每一个，以及连接到由P沟道晶体管和N沟道晶体管形成的连接节点的浮动防止锁存电路。特别地，在检测电路中，P沟道晶体管的栅极连接到节点A，并且N沟道晶体管的栅极连接到其中两个节点信号A和B最初为低的节点B，节点信号A首先上升到高电平，则节点信号B上升到高电平，节点信号A和B保持高电平达预定时间段，节点信号B首先降低到低电平，然后节点信号A降到低电平。此外，提供了用于检测根据本发明的用于半导体存储器中的位线的充电和放电完成的定时的检测电路。

8. 发明授权

US5726942A Hierarchical encoder including timing and data detection devices for a content addressable memory 失效
标题翻译：分层编码器，包括用于内容可寻址存储器的定时和数据检测装置
公开(公告)号：US5726942A
公开(公告)日：1998-03-10
申请号：US760292
申请日：1996-12-04
申请人： Masato Yoneda , Hiroshi Sasama , Naoki Kanazawa
发明人： Masato Yoneda , Hiroshi Sasama , Naoki Kanazawa
IPC分类号： G06F7/74 , G06F17/30 , G11C15/04 , G11C7/06
CPC分类号： G06F7/74 , G06F17/30982 , G11C15/04
摘要： A encoder has a prefetch circuit or a flag data sense circuit built into the priority encoder provided for a CAM block. While a hit signal in the first priority subblock is being encoded, a hit signal in the second priority subblock can be stored in the prefetch circuit. Therefore, the encoding operation is performed without subblock-to-subblock switch time and this makes the encoder best suitable for a large capacity CAM which is required to operate at high speed. Moreover, a semiconductor integrated circuit of the present invention detects the differential current between the current flowing through one signal line and the reference current flowing through the other signal line. Moreover, it can operate as the number detection circuit to detect the number of hit signal in the subblock, and it can operate as the timing control circuit to previously notify the encode termination of the hit signal in the subblock of the encoder described above. Therefore, this semiconductor integrated circuit can allow the encoder to encode very efficiently at high speed. Moreover, a dynamic sense amplifier is able to operate with a great operating margin.
摘要翻译：编码器具有内置在为CAM块提供的优先编码器中的预取电路或标志数据检测电路。当第一优先子块中的命中信号被编码时，第二优先级子块中的命中信号可被存储在预取电路中。因此，在没有子块到子块切换时间的情况下执行编码操作，这使得编码器最适合于高速操作所需的大容量CAM。此外，本发明的半导体集成电路检测流过一条信号线的电流与流过另一条信号线的基准电流之间的差分电流。此外，它可以作为号码检测电路来操作以检测子块中的命中信号的数量，并且它可以作为定时控制电路进行操作以预先通知上述编码器的子块中的命中信号的编码终止。因此，该半导体集成电路可以允许编码器以高速非常有效地进行编码。此外，动态感测放大器能够以较大的运行裕度运行。

9. 发明授权

US07942023B2 Drum type washing machine 有权
标题翻译：鼓式洗衣机
公开(公告)号：US07942023B2
公开(公告)日：2011-05-17
申请号：US12343590
申请日：2008-12-24
申请人： Naoki Kanazawa
发明人： Naoki Kanazawa
IPC分类号： D06F33/02
CPC分类号： D06F33/02 , D06F39/003
摘要： Disclosed herein are a drum type washing machine and a control program therefore. The washing machine includes a control mechanism to control a motor. The control mechanism includes a torque control unit to perform torque addition processes of adding pulse type torque during only a period for which a drum makes one rotation in a uniform torque control state in which torque of the motor is uniformly controlled at least two times and to perform the second torque addition process after n+0.5 rotations of the drum (n is an integer not less than 1) on the basis of the first torque addition process, and a weight calculation unit to calculate an average value of rotational accelerations of the motor at the respective torque addition processes and to calculate a weight of laundry received in the drum based on the average value.
摘要翻译：因此，本文公开了一种滚筒式洗衣机和控制程序。洗衣机包括用于控制电动机的控制机构。该控制机构包括扭矩控制单元，其在仅在电动机的转矩被均匀地控制至少两次的均匀转矩控制状态期间，在鼓进行一次旋转的期间内，进行相加脉冲型转矩的转矩附加处理，基于第一扭矩加法处理，在滚筒的n + 0.5转之后进行第二扭矩加法处理（n为1以上的整数），以及权重计算单元，计算马达的旋转加速度的平均值并且基于平均值计算在滚筒中接收的衣物的重量。

10. 发明申请

US20080041115A1 Washing machine and method of calculating amount of laundry 审中-公开
标题翻译：洗衣机和洗衣量的计算方法
公开(公告)号：US20080041115A1
公开(公告)日：2008-02-21
申请号：US11878236
申请日：2007-07-23
申请人： Naoki Kanazawa , Soiichiro Suzuki , Shoichi Matsui , Sadayuki Sato
发明人： Naoki Kanazawa , Soiichiro Suzuki , Shoichi Matsui , Sadayuki Sato
IPC分类号： D06F23/00 , D06F37/30 , G01P15/00
CPC分类号： G01P15/00 , D06F33/02 , D06F39/003 , D06F2202/065 , D06F2202/12
摘要： Provided are a washing machine and a method of calculating the amount of laundry. The washing machine includes a spin basket which has an inner space to put laundry therein and is rotatably mounted about a rotation shaft in a rotational direction by driving a motor and includes: a rotation time calculating unit which calculates a time period when the spin basket rotates once; a pulse torque generating unit which supplies a predetermined current or voltage to the motor during the time period when the spin basket rotates once and generates a pulse torque through an output shaft from the motor; an acceleration measuring unit which measures rotation acceleration of the output shaft of the motor according to the pulse torque generated from the motor; and a weight calculating unit which calculates the weight of the laundry put in the inner space of the spin basket by the rotation acceleration.
摘要翻译：提供一种洗衣机和一种计算衣物量的方法。洗衣机包括：旋转筐，其具有内部空间以将衣物放置在其中，并通过驱动电动机以旋转方向可旋转地安装在旋转轴上，旋转时间计算单元计算旋转筐旋转时的时间周期一旦; 脉冲转矩产生单元，其在旋转筐旋转一次的时间段期间向电动机提供预定电流或电压，并通过来自电动机的输出轴产生脉冲转矩; 加速度测量单元，其根据从马达产生的脉冲转矩来测量马达的输出轴的旋转加速度; 以及权重计算单元，其计算通过旋转加速度放置在旋转筒的内部空间中的衣物的重量。

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